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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
EcoNet EN751221 clock/reset driver is significantly similar to the
EN7523 / EN7581, however the EN751221 does not have a neat batch of clock
divider registers so there are fewer known clocks, and the frequency of
each clock is derived differently. This clock driver will probably work
correctly on EN751627, EN7528, and EN7580.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Caleb James DeLisle
and committed by
Stephen Boyd
d8b03452
35af99f7
+221
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+3
-3
drivers/clk/Kconfig
+3
-3
drivers/clk/Kconfig
···
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If you say yes here you get support for the CS2000 clock multiplier.
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config COMMON_CLK_EN7523
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bool "Clock driver for Airoha EN7523 SoC system clocks"
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bool "Clock driver for Airoha/EcoNet SoC system clocks"
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depends on OF
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depends on ARCH_AIROHA || COMPILE_TEST
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depends on ARCH_AIROHA || ECONET || COMPILE_TEST
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default ARCH_AIROHA
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help
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This driver provides the fixed clocks and gates present on Airoha
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ARM silicon.
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and EcoNet silicon.
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config COMMON_CLK_EP93XX
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tristate "Clock driver for Cirrus Logic ep93xx SoC"
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-5
drivers/clk/clk-en7523.c
+218
-5
drivers/clk/clk-en7523.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
···
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7523-reset.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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#include <dt-bindings/clock/econet,en751221-scu.h>
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#include <dt-bindings/reset/econet,en751221-scu.h>
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#define RST_NR_PER_BANK 32
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···
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#define REG_RESET_CONTROL_PCIEHB BIT(29)
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#define REG_RESET_CONTROL_PCIE1 BIT(27)
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#define REG_RESET_CONTROL_PCIE2 BIT(26)
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#define REG_HIR 0x064
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#define REG_HIR_MASK GENMASK(31, 16)
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/* EN7581 */
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
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#define REG_CRYPTO_CLKSRC2 0x20c
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/* EN751221 */
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#define EN751221_REG_SPI_DIV 0x0cc
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#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
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#define EN751221_SPI_BASE 500000000
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#define EN751221_SPI_BASE_EN7526C 400000000
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#define EN751221_SPI_DIV_DEFAULT 40
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#define EN751221_REG_BUS 0x284
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#define EN751221_REG_BUS_MASK GENMASK(21, 12)
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#define EN751221_REG_SSR3 0x094
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#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
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#define REG_RST_CTRL2 0x830
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#define REG_RST_CTRL1 0x834
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#define EN751221_REG_RST_DMT 0x84
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#define EN751221_REG_RST_USB 0xec
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#define EN751221_MAX_CLKS 5
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enum en_hir {
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HIR_UNKNOWN = -1,
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HIR_TC3169 = 0,
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HIR_TC3182 = 1,
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HIR_RT65168 = 2,
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HIR_RT63165 = 3,
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HIR_RT63365 = 4,
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HIR_MT751020 = 5,
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HIR_MT7505 = 6,
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HIR_EN751221 = 7,
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HIR_EN7526C = 8,
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HIR_EN751627 = 9,
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HIR_EN7580 = 10,
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HIR_EN7528 = 11,
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HIR_EN7523 = 12,
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HIR_EN7581 = 13,
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HIR_MAX = 14,
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};
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struct en_clk_desc {
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int id;
···
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static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
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static const u32 crypto_base[] = { 540000000, 480000000 };
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static const u32 emmc7581_base[] = { 200000000, 150000000 };
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/* EN751221 */
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static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
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static const struct en_clk_desc en7523_base_clks[] = {
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{
···
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REG_RST_CTRL1,
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};
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static const u16 en751221_rst_ofs[] = {
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REG_RST_CTRL2,
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REG_RST_CTRL1,
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EN751221_REG_RST_DMT,
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EN751221_REG_RST_USB,
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};
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static const u16 en7523_rst_map[] = {
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/* RST_CTRL2 */
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[EN7523_XPON_PHY_RST] = 0,
···
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[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
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};
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static const u16 en751221_rst_map[] = {
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/* RST_CTRL2 */
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[EN751221_XPON_PHY_RST] = 0,
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[EN751221_GFAST_RST] = 1,
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[EN751221_CPU_TIMER2_RST] = 2,
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[EN751221_UART3_RST] = 3,
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[EN751221_UART4_RST] = 4,
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[EN751221_UART5_RST] = 5,
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[EN751221_I2C2_RST] = 6,
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[EN751221_XSI_MAC_RST] = 7,
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[EN751221_XSI_PHY_RST] = 8,
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/* RST_CTRL1 */
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[EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
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[EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
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[EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
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[EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
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[EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
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[EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
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[EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
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[EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
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[EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
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[EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
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[EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
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[EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
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[EN751221_UART_RST] = RST_NR_PER_BANK + 12,
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[EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
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[EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
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[EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
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[EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
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[EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
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[EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
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[EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
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[EN751221_FE_RST] = RST_NR_PER_BANK + 21,
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[EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
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[EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
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[EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
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[EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
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[EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
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[EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
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[EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
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[EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
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[EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
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/* RST_DMT */
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[EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
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/* RST_USB */
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[EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
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[EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
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};
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static int en7581_reset_register(struct device *dev, void __iomem *base,
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const u16 *rst_map, int nr_resets);
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const u16 *rst_map, int nr_resets,
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const u16 *rst_reg_ofs);
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static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
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{
···
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en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
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return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
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ARRAY_SIZE(en7523_rst_map));
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ARRAY_SIZE(en7523_rst_map),
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en7581_rst_ofs);
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}
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static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
···
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};
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static int en7581_reset_register(struct device *dev, void __iomem *base,
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const u16 *rst_map, int nr_resets)
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const u16 *rst_map, int nr_resets,
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const u16 *rst_reg_ofs)
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{
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struct en_rst_data *rst_data;
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···
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if (!rst_data)
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return -ENOMEM;
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rst_data->bank_ofs = en7581_rst_ofs;
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rst_data->bank_ofs = rst_reg_ofs;
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rst_data->idx_map = rst_map;
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rst_data->base = base;
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···
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writel(val | 3, base + REG_NP_SCU_PCIC);
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return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
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ARRAY_SIZE(en7581_rst_map));
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ARRAY_SIZE(en7581_rst_map),
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en7581_rst_ofs);
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}
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static enum en_hir get_hw_id(void __iomem *np_base)
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{
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u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
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if (val < HIR_MAX)
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return (enum en_hir)val;
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pr_warn("Unable to determine EcoNet SoC\n");
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return HIR_UNKNOWN;
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}
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static void en751221_try_register_clk(struct device *dev, int key,
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struct clk_hw_onecell_data *clk_data,
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const char *name, u32 rate)
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{
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struct clk_hw *hw;
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if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS))
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return;
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hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
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if (IS_ERR(hw))
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pr_err("Failed to register clk %s: %pe\n", name, hw);
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else
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clk_data->hws[key] = hw;
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}
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static void en751221_register_clocks(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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struct regmap *map, void __iomem *np_base)
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{
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enum en_hir hid = get_hw_id(np_base);
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struct clk_hw *hw;
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u32 rate;
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u32 div;
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int err;
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/* PCI */
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hw = en7523_register_pcie_clk(dev, np_base);
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clk_data->hws[EN751221_CLK_PCIE] = hw;
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/* SPI */
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rate = EN751221_SPI_BASE;
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if (hid == HIR_EN7526C)
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rate = EN751221_SPI_BASE_EN7526C;
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err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
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if (err) {
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pr_err("Failed reading fixed clk div %s: %d\n",
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"spi", err);
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} else {
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div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
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if (!div)
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div = EN751221_SPI_DIV_DEFAULT;
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en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
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"spi", rate / div);
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}
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/* BUS */
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rate = FIELD_GET(EN751221_REG_BUS_MASK,
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readl(np_base + EN751221_REG_BUS));
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rate *= 1000000;
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en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
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rate);
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/* CPU */
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en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
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rate * 4);
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/* GSW */
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rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
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readl(np_base + EN751221_REG_SSR3));
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en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
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gsw751221_base[rate]);
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}
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static int en751221_clk_hw_init(struct platform_device *pdev,
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struct clk_hw_onecell_data *clk_data)
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{
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struct regmap *map;
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void __iomem *base;
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map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
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if (IS_ERR(map))
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return PTR_ERR(map);
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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en751221_register_clocks(&pdev->dev, clk_data, map, base);
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return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
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ARRAY_SIZE(en751221_rst_map),
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en751221_rst_ofs);
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}
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static int en7523_clk_probe(struct platform_device *pdev)
···
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.hw_init = en7581_clk_hw_init,
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};
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static const struct en_clk_soc_data en751221_data = {
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.num_clocks = EN751221_MAX_CLKS,
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.pcie_ops = {
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.is_enabled = en7523_pci_is_enabled,
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.prepare = en7523_pci_prepare,
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.unprepare = en7523_pci_unprepare,
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},
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.hw_init = en751221_clk_hw_init,
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};
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static const struct of_device_id of_match_clk_en7523[] = {
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{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
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{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
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{ .compatible = "econet,en751221-scu", .data = &en751221_data },
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{ /* sentinel */ }
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};
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