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clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

When a consumer turns on/off a power domain dependent on another power
domain in hardware, the parent power domain shall be turned on/off by
the power domain provider as well, and to get it the power domain hardware
hierarchy shall be described in the CAMCC driver.

Establish the power domain hierarchy with a Titan GDSC set as a parent of
all other GDSC power domains provided by the SM8550 camera clock controller
to enforce a correct sequence of enabling and disabling power domains by
the consumers, this fixes the CAMCC as a supplier of power domains to CAMSS
IP and its driver.

Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20251021234450.2271279-2-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Vladimir Zapolskiy and committed by
Bjorn Andersson d8f1121e 8abe970e

+10
+10
drivers/clk/qcom/camcc-sm8550.c
··· 3204 3204 }, 3205 3205 }; 3206 3206 3207 + static struct gdsc cam_cc_titan_top_gdsc; 3208 + 3207 3209 static struct gdsc cam_cc_bps_gdsc = { 3208 3210 .gdscr = 0x10004, 3209 3211 .en_rest_wait_val = 0x2, ··· 3215 3213 .name = "cam_cc_bps_gdsc", 3216 3214 }, 3217 3215 .pwrsts = PWRSTS_OFF_ON, 3216 + .parent = &cam_cc_titan_top_gdsc.pd, 3218 3217 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3219 3218 }; 3220 3219 ··· 3228 3225 .name = "cam_cc_ife_0_gdsc", 3229 3226 }, 3230 3227 .pwrsts = PWRSTS_OFF_ON, 3228 + .parent = &cam_cc_titan_top_gdsc.pd, 3231 3229 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3232 3230 }; 3233 3231 ··· 3241 3237 .name = "cam_cc_ife_1_gdsc", 3242 3238 }, 3243 3239 .pwrsts = PWRSTS_OFF_ON, 3240 + .parent = &cam_cc_titan_top_gdsc.pd, 3244 3241 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3245 3242 }; 3246 3243 ··· 3254 3249 .name = "cam_cc_ife_2_gdsc", 3255 3250 }, 3256 3251 .pwrsts = PWRSTS_OFF_ON, 3252 + .parent = &cam_cc_titan_top_gdsc.pd, 3257 3253 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3258 3254 }; 3259 3255 ··· 3267 3261 .name = "cam_cc_ipe_0_gdsc", 3268 3262 }, 3269 3263 .pwrsts = PWRSTS_OFF_ON, 3264 + .parent = &cam_cc_titan_top_gdsc.pd, 3270 3265 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3271 3266 }; 3272 3267 ··· 3280 3273 .name = "cam_cc_sbi_gdsc", 3281 3274 }, 3282 3275 .pwrsts = PWRSTS_OFF_ON, 3276 + .parent = &cam_cc_titan_top_gdsc.pd, 3283 3277 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3284 3278 }; 3285 3279 ··· 3293 3285 .name = "cam_cc_sfe_0_gdsc", 3294 3286 }, 3295 3287 .pwrsts = PWRSTS_OFF_ON, 3288 + .parent = &cam_cc_titan_top_gdsc.pd, 3296 3289 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3297 3290 }; 3298 3291 ··· 3306 3297 .name = "cam_cc_sfe_1_gdsc", 3307 3298 }, 3308 3299 .pwrsts = PWRSTS_OFF_ON, 3300 + .parent = &cam_cc_titan_top_gdsc.pd, 3309 3301 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3310 3302 }; 3311 3303