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arm64/mm: Directly use TTBRx_EL1_ASID_MASK

Replace all TTBR_ASID_MASK macro instances with TTBRx_EL1_ASID_MASK which
is a standard field mask from tools sysreg format. Drop the now redundant
custom macro TTBR_ASID_MASK. No functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oupton@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.linux.dev
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Anshuman Khandual and committed by
Catalin Marinas d989010b 2615924e

+10 -10
+1 -1
arch/arm64/include/asm/asm-uaccess.h
··· 15 15 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 16 16 .macro __uaccess_ttbr0_disable, tmp1 17 17 mrs \tmp1, ttbr1_el1 // swapper_pg_dir 18 - bic \tmp1, \tmp1, #TTBR_ASID_MASK 18 + bic \tmp1, \tmp1, #TTBRx_EL1_ASID_MASK 19 19 sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir 20 20 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 21 21 add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET
-1
arch/arm64/include/asm/mmu.h
··· 10 10 #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ 11 11 #define USER_ASID_BIT 48 12 12 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) 13 - #define TTBR_ASID_MASK (UL(0xffff) << 48) 14 13 15 14 #ifndef __ASSEMBLER__ 16 15
+2 -1
arch/arm64/include/asm/mmu_context.h
··· 210 210 if (mm == &init_mm) 211 211 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 212 212 else 213 - ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; 213 + ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | 214 + FIELD_PREP(TTBRx_EL1_ASID_MASK, ASID(mm)); 214 215 215 216 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); 216 217 }
+3 -3
arch/arm64/include/asm/uaccess.h
··· 62 62 63 63 local_irq_save(flags); 64 64 ttbr = read_sysreg(ttbr1_el1); 65 - ttbr &= ~TTBR_ASID_MASK; 65 + ttbr &= ~TTBRx_EL1_ASID_MASK; 66 66 /* reserved_pg_dir placed before swapper_pg_dir */ 67 67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); 68 68 /* Set reserved ASID */ ··· 85 85 86 86 /* Restore active ASID */ 87 87 ttbr1 = read_sysreg(ttbr1_el1); 88 - ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */ 89 - ttbr1 |= ttbr0 & TTBR_ASID_MASK; 88 + ttbr1 &= ~TTBRx_EL1_ASID_MASK; /* safety measure */ 89 + ttbr1 |= ttbr0 & TTBRx_EL1_ASID_MASK; 90 90 write_sysreg(ttbr1, ttbr1_el1); 91 91 92 92 /* Restore user page table */
+1 -1
arch/arm64/kernel/entry.S
··· 473 473 */ 474 474 SYM_CODE_START_LOCAL(__swpan_entry_el1) 475 475 mrs x21, ttbr0_el1 476 - tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 476 + tst x21, #TTBRx_EL1_ASID_MASK // Check for the reserved ASID 477 477 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 478 478 b.eq 1f // TTBR0 access already disabled 479 479 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
+3 -3
arch/arm64/mm/context.c
··· 358 358 359 359 /* SW PAN needs a copy of the ASID in TTBR0 for entry */ 360 360 if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN)) 361 - ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid); 361 + ttbr0 |= FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); 362 362 363 363 /* Set ASID in TTBR1 since TCR.A1 is set */ 364 - ttbr1 &= ~TTBR_ASID_MASK; 365 - ttbr1 |= FIELD_PREP(TTBR_ASID_MASK, asid); 364 + ttbr1 &= ~TTBRx_EL1_ASID_MASK; 365 + ttbr1 |= FIELD_PREP(TTBRx_EL1_ASID_MASK, asid); 366 366 367 367 cpu_set_reserved_ttbr0_nosync(); 368 368 write_sysreg(ttbr1, ttbr1_el1);