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arm64: tlb: Pass the corresponding mm to __tlbi_sync_s1ish()

The mm structure will be used for workarounds that need limiting to
specific tasks.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

Catalin Marinas d9fb08ba 6bfbf574

+5 -5
+4 -4
arch/arm64/include/asm/tlbflush.h
··· 185 185 * Complete broadcast TLB maintenance issued by the host which invalidates 186 186 * stage 1 information in the host's own translation regime. 187 187 */ 188 - static inline void __tlbi_sync_s1ish(void) 188 + static inline void __tlbi_sync_s1ish(struct mm_struct *mm) 189 189 { 190 190 dsb(ish); 191 191 __repeat_tlbi_sync(vale1is, 0); ··· 323 323 asid = __TLBI_VADDR(0, ASID(mm)); 324 324 __tlbi(aside1is, asid); 325 325 __tlbi_user(aside1is, asid); 326 - __tlbi_sync_s1ish(); 326 + __tlbi_sync_s1ish(mm); 327 327 mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); 328 328 } 329 329 ··· 377 377 unsigned long uaddr) 378 378 { 379 379 flush_tlb_page_nosync(vma, uaddr); 380 - __tlbi_sync_s1ish(); 380 + __tlbi_sync_s1ish(vma->vm_mm); 381 381 } 382 382 383 383 static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm) ··· 532 532 { 533 533 __flush_tlb_range_nosync(vma->vm_mm, start, end, stride, 534 534 last_level, tlb_level); 535 - __tlbi_sync_s1ish(); 535 + __tlbi_sync_s1ish(vma->vm_mm); 536 536 } 537 537 538 538 static inline void local_flush_tlb_contpte(struct vm_area_struct *vma,
+1 -1
arch/arm64/kernel/sys_compat.c
··· 37 37 * We pick the reserved-ASID to minimise the impact. 38 38 */ 39 39 __tlbi(aside1is, __TLBI_VADDR(0, 0)); 40 - __tlbi_sync_s1ish(); 40 + __tlbi_sync_s1ish(current->mm); 41 41 } 42 42 43 43 ret = caches_clean_inval_user_pou(start, start + chunk);