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counter: 104-quad-8: Implement and utilize register structures

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures.

Link: https://lore.kernel.org/r/20220707171709.36010-1-william.gray@linaro.org/
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Tested-by: Fred Eckert <Frede@cmslaser.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Link: https://lore.kernel.org/r/285fdc7c03892251f50bdbf2c28c19998243a6a3.1657813472.git.william.gray@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

William Breathitt Gray and committed by
Greg Kroah-Hartman daae1ee5 b6e9cded

+93 -73
+93 -73
drivers/counter/104-quad-8.c
··· 34 34 #define QUAD8_NUM_COUNTERS 8 35 35 36 36 /** 37 + * struct channel_reg - channel register structure 38 + * @data: Count data 39 + * @control: Channel flags and control 40 + */ 41 + struct channel_reg { 42 + u8 data; 43 + u8 control; 44 + }; 45 + 46 + /** 47 + * struct quad8_reg - device register structure 48 + * @channel: quadrature counter data and control 49 + * @interrupt_status: channel interrupt status 50 + * @channel_oper: enable/reset counters and interrupt functions 51 + * @index_interrupt: enable channel interrupts 52 + * @reserved: reserved for Factory Use 53 + * @index_input_levels: index signal logical input level 54 + * @cable_status: differential encoder cable status 55 + */ 56 + struct quad8_reg { 57 + struct channel_reg channel[QUAD8_NUM_COUNTERS]; 58 + u8 interrupt_status; 59 + u8 channel_oper; 60 + u8 index_interrupt; 61 + u8 reserved[3]; 62 + u8 index_input_levels; 63 + u8 cable_status; 64 + }; 65 + 66 + /** 37 67 * struct quad8 - device private data structure 38 68 * @lock: lock to prevent clobbering device states during R/W ops 39 69 * @counter: instance of the counter_device ··· 78 48 * @synchronous_mode: array of index function synchronous mode configurations 79 49 * @index_polarity: array of index function polarity configurations 80 50 * @cable_fault_enable: differential encoder cable status enable configurations 81 - * @base: base port address of the device 51 + * @reg: I/O address offset for the device registers 82 52 */ 83 53 struct quad8 { 84 54 spinlock_t lock; ··· 93 63 unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; 94 64 unsigned int index_polarity[QUAD8_NUM_COUNTERS]; 95 65 unsigned int cable_fault_enable; 96 - void __iomem *base; 66 + struct quad8_reg __iomem *reg; 97 67 }; 98 68 99 - #define QUAD8_REG_INTERRUPT_STATUS 0x10 100 - #define QUAD8_REG_CHAN_OP 0x11 101 - #define QUAD8_REG_INDEX_INTERRUPT 0x12 102 - #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16 103 - #define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17 104 69 /* Borrow Toggle flip-flop */ 105 70 #define QUAD8_FLAG_BT BIT(0) 106 71 /* Carry Toggle flip-flop */ ··· 143 118 if (signal->id < 16) 144 119 return -EINVAL; 145 120 146 - state = ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) & 147 - BIT(signal->id - 16); 121 + state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16); 148 122 149 123 *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; 150 124 ··· 154 130 struct counter_count *count, u64 *val) 155 131 { 156 132 struct quad8 *const priv = counter_priv(counter); 157 - void __iomem *const base_offset = priv->base + 2 * count->id; 133 + struct channel_reg __iomem *const chan = priv->reg->channel + count->id; 158 134 unsigned int flags; 159 135 unsigned int borrow; 160 136 unsigned int carry; 161 137 unsigned long irqflags; 162 138 int i; 163 139 164 - flags = ioread8(base_offset + 1); 140 + flags = ioread8(&chan->control); 165 141 borrow = flags & QUAD8_FLAG_BT; 166 142 carry = !!(flags & QUAD8_FLAG_CT); 167 143 ··· 172 148 173 149 /* Reset Byte Pointer; transfer Counter to Output Latch */ 174 150 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, 175 - base_offset + 1); 151 + &chan->control); 176 152 177 153 for (i = 0; i < 3; i++) 178 - *val |= (unsigned long)ioread8(base_offset) << (8 * i); 154 + *val |= (unsigned long)ioread8(&chan->data) << (8 * i); 179 155 180 156 spin_unlock_irqrestore(&priv->lock, irqflags); 181 157 ··· 186 162 struct counter_count *count, u64 val) 187 163 { 188 164 struct quad8 *const priv = counter_priv(counter); 189 - void __iomem *const base_offset = priv->base + 2 * count->id; 165 + struct channel_reg __iomem *const chan = priv->reg->channel + count->id; 190 166 unsigned long irqflags; 191 167 int i; 192 168 ··· 197 173 spin_lock_irqsave(&priv->lock, irqflags); 198 174 199 175 /* Reset Byte Pointer */ 200 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 176 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 201 177 202 178 /* Counter can only be set via Preset Register */ 203 179 for (i = 0; i < 3; i++) 204 - iowrite8(val >> (8 * i), base_offset); 180 + iowrite8(val >> (8 * i), &chan->data); 205 181 206 182 /* Transfer Preset Register to Counter */ 207 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); 183 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control); 208 184 209 185 /* Reset Byte Pointer */ 210 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 186 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 211 187 212 188 /* Set Preset Register back to original value */ 213 189 val = priv->preset[count->id]; 214 190 for (i = 0; i < 3; i++) 215 - iowrite8(val >> (8 * i), base_offset); 191 + iowrite8(val >> (8 * i), &chan->data); 216 192 217 193 /* Reset Borrow, Carry, Compare, and Sign flags */ 218 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); 194 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); 219 195 /* Reset Error flag */ 220 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); 196 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); 221 197 222 198 spin_unlock_irqrestore(&priv->lock, irqflags); 223 199 ··· 270 246 unsigned int *const quadrature_mode = priv->quadrature_mode + id; 271 247 unsigned int *const scale = priv->quadrature_scale + id; 272 248 unsigned int *const synchronous_mode = priv->synchronous_mode + id; 273 - void __iomem *const base_offset = priv->base + 2 * id + 1; 249 + u8 __iomem *const control = &priv->reg->channel[id].control; 274 250 unsigned long irqflags; 275 251 unsigned int mode_cfg; 276 252 unsigned int idr_cfg; ··· 290 266 if (*synchronous_mode) { 291 267 *synchronous_mode = 0; 292 268 /* Disable synchronous function mode */ 293 - iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); 269 + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 294 270 } 295 271 } else { 296 272 *quadrature_mode = 1; ··· 316 292 } 317 293 318 294 /* Load mode configuration to Counter Mode Register */ 319 - iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); 295 + iowrite8(QUAD8_CTR_CMR | mode_cfg, control); 320 296 321 297 spin_unlock_irqrestore(&priv->lock, irqflags); 322 298 ··· 329 305 { 330 306 const struct quad8 *const priv = counter_priv(counter); 331 307 unsigned int ud_flag; 332 - void __iomem *const flag_addr = priv->base + 2 * count->id + 1; 308 + u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; 333 309 334 310 /* U/D flag: nonzero = up, zero = down */ 335 311 ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD; ··· 426 402 struct counter_event_node *event_node; 427 403 unsigned int next_irq_trigger; 428 404 unsigned long ior_cfg; 429 - void __iomem *base_offset; 430 405 431 406 spin_lock_irqsave(&priv->lock, irqflags); 432 407 ··· 460 437 ior_cfg = priv->ab_enable[event_node->channel] | 461 438 priv->preset_enable[event_node->channel] << 1 | 462 439 priv->irq_trigger[event_node->channel] << 3; 463 - base_offset = priv->base + 2 * event_node->channel + 1; 464 - iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); 440 + iowrite8(QUAD8_CTR_IOR | ior_cfg, 441 + &priv->reg->channel[event_node->channel].control); 465 442 466 443 /* Enable IRQ line */ 467 444 irq_enabled |= BIT(event_node->channel); 468 445 } 469 446 470 - iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); 447 + iowrite8(irq_enabled, &priv->reg->index_interrupt); 471 448 472 449 spin_unlock_irqrestore(&priv->lock, irqflags); 473 450 ··· 531 508 { 532 509 struct quad8 *const priv = counter_priv(counter); 533 510 const size_t channel_id = signal->id - 16; 534 - void __iomem *const base_offset = priv->base + 2 * channel_id + 1; 511 + u8 __iomem *const control = &priv->reg->channel[channel_id].control; 535 512 unsigned long irqflags; 536 513 unsigned int idr_cfg = index_polarity << 1; 537 514 ··· 542 519 priv->index_polarity[channel_id] = index_polarity; 543 520 544 521 /* Load Index Control configuration to Index Control Register */ 545 - iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); 522 + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 546 523 547 524 spin_unlock_irqrestore(&priv->lock, irqflags); 548 525 ··· 572 549 { 573 550 struct quad8 *const priv = counter_priv(counter); 574 551 const size_t channel_id = signal->id - 16; 575 - void __iomem *const base_offset = priv->base + 2 * channel_id + 1; 552 + u8 __iomem *const control = &priv->reg->channel[channel_id].control; 576 553 unsigned long irqflags; 577 554 unsigned int idr_cfg = synchronous_mode; 578 555 ··· 589 566 priv->synchronous_mode[channel_id] = synchronous_mode; 590 567 591 568 /* Load Index Control configuration to Index Control Register */ 592 - iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); 569 + iowrite8(QUAD8_CTR_IDR | idr_cfg, control); 593 570 594 571 spin_unlock_irqrestore(&priv->lock, irqflags); 595 572 ··· 637 614 struct quad8 *const priv = counter_priv(counter); 638 615 unsigned int count_mode; 639 616 unsigned int mode_cfg; 640 - void __iomem *const base_offset = priv->base + 2 * count->id + 1; 617 + u8 __iomem *const control = &priv->reg->channel[count->id].control; 641 618 unsigned long irqflags; 642 619 643 620 /* Map Generic Counter count mode to 104-QUAD-8 count mode */ ··· 671 648 mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; 672 649 673 650 /* Load mode configuration to Counter Mode Register */ 674 - iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); 651 + iowrite8(QUAD8_CTR_CMR | mode_cfg, control); 675 652 676 653 spin_unlock_irqrestore(&priv->lock, irqflags); 677 654 ··· 692 669 struct counter_count *count, u8 enable) 693 670 { 694 671 struct quad8 *const priv = counter_priv(counter); 695 - void __iomem *const base_offset = priv->base + 2 * count->id; 672 + u8 __iomem *const control = &priv->reg->channel[count->id].control; 696 673 unsigned long irqflags; 697 674 unsigned int ior_cfg; 698 675 ··· 704 681 priv->irq_trigger[count->id] << 3; 705 682 706 683 /* Load I/O control configuration */ 707 - iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); 684 + iowrite8(QUAD8_CTR_IOR | ior_cfg, control); 708 685 709 686 spin_unlock_irqrestore(&priv->lock, irqflags); 710 687 ··· 720 697 struct counter_count *count, u32 *noise_error) 721 698 { 722 699 const struct quad8 *const priv = counter_priv(counter); 723 - void __iomem *const base_offset = priv->base + 2 * count->id + 1; 700 + u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; 724 701 725 - *noise_error = !!(ioread8(base_offset) & QUAD8_FLAG_E); 702 + *noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E); 726 703 727 704 return 0; 728 705 } ··· 740 717 static void quad8_preset_register_set(struct quad8 *const priv, const int id, 741 718 const unsigned int preset) 742 719 { 743 - void __iomem *const base_offset = priv->base + 2 * id; 720 + struct channel_reg __iomem *const chan = priv->reg->channel + id; 744 721 int i; 745 722 746 723 priv->preset[id] = preset; 747 724 748 725 /* Reset Byte Pointer */ 749 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 726 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 750 727 751 728 /* Set Preset Register */ 752 729 for (i = 0; i < 3; i++) 753 - iowrite8(preset >> (8 * i), base_offset); 730 + iowrite8(preset >> (8 * i), &chan->data); 754 731 } 755 732 756 733 static int quad8_count_preset_write(struct counter_device *counter, ··· 839 816 u8 preset_enable) 840 817 { 841 818 struct quad8 *const priv = counter_priv(counter); 842 - void __iomem *const base_offset = priv->base + 2 * count->id + 1; 819 + u8 __iomem *const control = &priv->reg->channel[count->id].control; 843 820 unsigned long irqflags; 844 821 unsigned int ior_cfg; 845 822 ··· 854 831 priv->irq_trigger[count->id] << 3; 855 832 856 833 /* Load I/O control configuration to Input / Output Control Register */ 857 - iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); 834 + iowrite8(QUAD8_CTR_IOR | ior_cfg, control); 858 835 859 836 spin_unlock_irqrestore(&priv->lock, irqflags); 860 837 ··· 881 858 } 882 859 883 860 /* Logic 0 = cable fault */ 884 - status = ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); 861 + status = ioread8(&priv->reg->cable_status); 885 862 886 863 spin_unlock_irqrestore(&priv->lock, irqflags); 887 864 ··· 922 899 /* Enable is active low in Differential Encoder Cable Status register */ 923 900 cable_fault_enable = ~priv->cable_fault_enable; 924 901 925 - iowrite8(cable_fault_enable, 926 - priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); 902 + iowrite8(cable_fault_enable, &priv->reg->cable_status); 927 903 928 904 spin_unlock_irqrestore(&priv->lock, irqflags); 929 905 ··· 946 924 { 947 925 struct quad8 *const priv = counter_priv(counter); 948 926 const size_t channel_id = signal->id / 2; 949 - void __iomem *const base_offset = priv->base + 2 * channel_id; 927 + struct channel_reg __iomem *const chan = priv->reg->channel + channel_id; 950 928 unsigned long irqflags; 951 929 952 930 spin_lock_irqsave(&priv->lock, irqflags); ··· 954 932 priv->fck_prescaler[channel_id] = prescaler; 955 933 956 934 /* Reset Byte Pointer */ 957 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 935 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 958 936 959 937 /* Set filter clock factor */ 960 - iowrite8(prescaler, base_offset); 938 + iowrite8(prescaler, &chan->data); 961 939 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, 962 - base_offset + 1); 940 + &chan->control); 963 941 964 942 spin_unlock_irqrestore(&priv->lock, irqflags); 965 943 ··· 1107 1085 { 1108 1086 struct counter_device *counter = private; 1109 1087 struct quad8 *const priv = counter_priv(counter); 1110 - void __iomem *const base = priv->base; 1111 1088 unsigned long irq_status; 1112 1089 unsigned long channel; 1113 1090 u8 event; 1114 1091 1115 - irq_status = ioread8(base + QUAD8_REG_INTERRUPT_STATUS); 1092 + irq_status = ioread8(&priv->reg->interrupt_status); 1116 1093 if (!irq_status) 1117 1094 return IRQ_NONE; 1118 1095 ··· 1140 1119 } 1141 1120 1142 1121 /* Clear pending interrupts on device */ 1143 - iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); 1122 + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); 1144 1123 1145 1124 return IRQ_HANDLED; 1146 1125 } 1147 1126 1148 - static void quad8_init_counter(void __iomem *const base_offset) 1127 + static void quad8_init_counter(struct channel_reg __iomem *const chan) 1149 1128 { 1150 1129 unsigned long i; 1151 1130 1152 1131 /* Reset Byte Pointer */ 1153 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 1132 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 1154 1133 /* Reset filter clock factor */ 1155 - iowrite8(0, base_offset); 1134 + iowrite8(0, &chan->data); 1156 1135 iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, 1157 - base_offset + 1); 1136 + &chan->control); 1158 1137 /* Reset Byte Pointer */ 1159 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); 1138 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); 1160 1139 /* Reset Preset Register */ 1161 1140 for (i = 0; i < 3; i++) 1162 - iowrite8(0x00, base_offset); 1141 + iowrite8(0x00, &chan->data); 1163 1142 /* Reset Borrow, Carry, Compare, and Sign flags */ 1164 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); 1143 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); 1165 1144 /* Reset Error flag */ 1166 - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); 1145 + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); 1167 1146 /* Binary encoding; Normal count; non-quadrature mode */ 1168 - iowrite8(QUAD8_CTR_CMR, base_offset + 1); 1147 + iowrite8(QUAD8_CTR_CMR, &chan->control); 1169 1148 /* Disable A and B inputs; preset on index; FLG1 as Carry */ 1170 - iowrite8(QUAD8_CTR_IOR, base_offset + 1); 1149 + iowrite8(QUAD8_CTR_IOR, &chan->control); 1171 1150 /* Disable index function; negative index polarity */ 1172 - iowrite8(QUAD8_CTR_IDR, base_offset + 1); 1151 + iowrite8(QUAD8_CTR_IDR, &chan->control); 1173 1152 } 1174 1153 1175 1154 static int quad8_probe(struct device *dev, unsigned int id) ··· 1190 1169 return -ENOMEM; 1191 1170 priv = counter_priv(counter); 1192 1171 1193 - priv->base = devm_ioport_map(dev, base[id], QUAD8_EXTENT); 1194 - if (!priv->base) 1172 + priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT); 1173 + if (!priv->reg) 1195 1174 return -ENOMEM; 1196 1175 1197 1176 /* Initialize Counter device and driver data */ ··· 1206 1185 spin_lock_init(&priv->lock); 1207 1186 1208 1187 /* Reset Index/Interrupt Register */ 1209 - iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT); 1188 + iowrite8(0x00, &priv->reg->index_interrupt); 1210 1189 /* Reset all counters and disable interrupt function */ 1211 - iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP); 1190 + iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper); 1212 1191 /* Set initial configuration for all counters */ 1213 1192 for (i = 0; i < QUAD8_NUM_COUNTERS; i++) 1214 - quad8_init_counter(priv->base + 2 * i); 1193 + quad8_init_counter(priv->reg->channel + i); 1215 1194 /* Disable Differential Encoder Cable Status for all channels */ 1216 - iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); 1195 + iowrite8(0xFF, &priv->reg->cable_status); 1217 1196 /* Enable all counters and enable interrupt function */ 1218 - iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, 1219 - priv->base + QUAD8_REG_CHAN_OP); 1197 + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); 1220 1198 1221 1199 err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, 1222 1200 IRQF_SHARED, counter->name, counter);