tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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amdgpu/ttm: use amdgpu_gtt_mgr_alloc_entries

Use amdgpu_gtt_mgr_alloc_entries for each entity instead
of reserving a fixed number of pages.

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Pierre-Eric Pelloux-Prayer and committed by
Alex Deucher db3b7488 71aec08f

+43 -24
+42 -24
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 2011 2011 adev->rmmio_remap.bo = NULL; 2012 2012 } 2013 2013 2014 - static int amdgpu_ttm_buffer_entity_init(struct amdgpu_ttm_buffer_entity *entity, 2014 + static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, 2015 + struct amdgpu_ttm_buffer_entity *entity, 2015 2016 enum drm_sched_priority prio, 2016 2017 struct drm_gpu_scheduler **scheds, 2017 2018 int num_schedulers, 2018 - int starting_gart_window, 2019 2019 u32 num_gart_windows) 2020 2020 { 2021 - int i, r; 2021 + int i, r, num_pages; 2022 2022 2023 2023 r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); 2024 2024 if (r) 2025 2025 return r; 2026 2026 2027 - 2028 2027 mutex_init(&entity->lock); 2029 2028 2030 2029 if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) 2031 - return starting_gart_window; 2030 + return -EINVAL; 2031 + if (num_gart_windows == 0) 2032 + return 0; 2033 + 2034 + num_pages = num_gart_windows * AMDGPU_GTT_MAX_TRANSFER_SIZE; 2035 + r = amdgpu_gtt_mgr_alloc_entries(mgr, &entity->gart_node, num_pages, 2036 + DRM_MM_INSERT_BEST); 2037 + if (r) { 2038 + drm_sched_entity_destroy(&entity->base); 2039 + return r; 2040 + } 2032 2041 2033 2042 for (i = 0; i < num_gart_windows; i++) { 2034 2043 entity->gart_window_offs[i] = 2035 - (u64)starting_gart_window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 2036 - AMDGPU_GPU_PAGE_SIZE; 2037 - starting_gart_window++; 2044 + amdgpu_gtt_node_to_byte_offset(&entity->gart_node) + 2045 + i * AMDGPU_GTT_MAX_TRANSFER_SIZE * PAGE_SIZE; 2038 2046 } 2039 2047 2040 - return starting_gart_window; 2048 + return 0; 2041 2049 } 2042 2050 2043 - static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_ttm_buffer_entity *entity) 2051 + static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, 2052 + struct amdgpu_ttm_buffer_entity *entity) 2044 2053 { 2054 + amdgpu_gtt_mgr_free_entries(mgr, &entity->gart_node); 2045 2055 drm_sched_entity_destroy(&entity->base); 2046 2056 } 2047 2057 ··· 2355 2345 2356 2346 ring = adev->mman.buffer_funcs_ring; 2357 2347 sched = &ring->sched; 2358 - r = amdgpu_ttm_buffer_entity_init(&adev->mman.default_entity, 2359 - DRM_SCHED_PRIORITY_KERNEL, &sched, 1, 2360 - 0, 0); 2348 + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, 2349 + &adev->mman.default_entity, 2350 + DRM_SCHED_PRIORITY_KERNEL, 2351 + &sched, 1, 0); 2361 2352 if (r < 0) { 2362 2353 dev_err(adev->dev, 2363 2354 "Failed setting up TTM entity (%d)\n", r); 2364 2355 return; 2365 2356 } 2366 2357 2367 - r = amdgpu_ttm_buffer_entity_init(&adev->mman.clear_entity, 2368 - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 2369 - r, 1); 2358 + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, 2359 + &adev->mman.clear_entity, 2360 + DRM_SCHED_PRIORITY_NORMAL, 2361 + &sched, 1, 1); 2370 2362 if (r < 0) { 2371 2363 dev_err(adev->dev, 2372 2364 "Failed setting up TTM BO clear entity (%d)\n", r); 2373 2365 goto error_free_default_entity; 2374 2366 } 2375 2367 2376 - r = amdgpu_ttm_buffer_entity_init(&adev->mman.move_entity, 2377 - DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 2378 - r, 2); 2368 + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, 2369 + &adev->mman.move_entity, 2370 + DRM_SCHED_PRIORITY_NORMAL, 2371 + &sched, 1, 2); 2379 2372 if (r < 0) { 2380 2373 dev_err(adev->dev, 2381 2374 "Failed setting up TTM BO move entity (%d)\n", r); 2382 2375 goto error_free_clear_entity; 2383 2376 } 2384 2377 } else { 2385 - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); 2386 - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); 2387 - amdgpu_ttm_buffer_entity_fini(&adev->mman.move_entity); 2378 + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2379 + &adev->mman.default_entity); 2380 + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2381 + &adev->mman.clear_entity); 2382 + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2383 + &adev->mman.move_entity); 2388 2384 /* Drop all the old fences since re-creating the scheduler entities 2389 2385 * will allocate new contexts. 2390 2386 */ ··· 2408 2392 return; 2409 2393 2410 2394 error_free_clear_entity: 2411 - amdgpu_ttm_buffer_entity_fini(&adev->mman.clear_entity); 2395 + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2396 + &adev->mman.clear_entity); 2412 2397 error_free_default_entity: 2413 - amdgpu_ttm_buffer_entity_fini(&adev->mman.default_entity); 2398 + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, 2399 + &adev->mman.default_entity); 2414 2400 } 2415 2401 2416 2402 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
··· 56 56 struct amdgpu_ttm_buffer_entity { 57 57 struct drm_sched_entity base; 58 58 struct mutex lock; 59 + struct drm_mm_node gart_node; 59 60 u64 gart_window_offs[2]; 60 61 }; 61 62