Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
usb: dwc3: dwc3-octeon: Move node parsing into driver probe
Parse and verify device tree node first, then setup UCTL bridge
using verified values. This avoids needless allocations
in case DT misconfiguration was found in the middle of setup.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZMd/x3MHA4/QowMO@lenoch
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Ladislav Michl
and committed by
Greg Kroah-Hartman
dc0092ce
c6110163
+60
-75
+60
-75
drivers/usb/dwc3/dwc3-octeon.c
+60
-75
drivers/usb/dwc3/dwc3-octeon.c
···
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}
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static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
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int ref_clk_sel, int ref_clk_fsel, int mpll_mul,
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int power_gpio, int power_active_low)
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{
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int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
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u32 clock_rate;
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u64 val;
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int div;
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struct device *dev = octeon->dev;
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void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL;
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void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG;
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-
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if (dev->of_node) {
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const char *ss_clock_type;
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const char *hs_clock_type;
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i = of_property_read_u32(dev->of_node,
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"refclk-frequency", &clock_rate);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-ss", &ss_clock_type);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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i = of_property_read_string(dev->of_node,
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"refclk-type-hs", &hs_clock_type);
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if (i) {
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dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
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ref_clk_sel = 0;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 2;
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else
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
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ref_clk_sel = 1;
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else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
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ref_clk_sel = 3;
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else {
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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ref_clk_sel = 3;
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}
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} else
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dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
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(clock_rate != 100000000))
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dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n",
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clock_rate);
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} else {
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dev_err(dev, "No USB UCTL device node\n");
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return -EINVAL;
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}
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/*
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* Step 1: Wait for all voltages to be stable...that surely
···
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val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
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ref_clk_fsel = 0x07;
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switch (clock_rate) {
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default:
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dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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clock_rate);
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fallthrough;
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case 100000000:
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mpll_mul = 0x19;
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if (ref_clk_sel < 2)
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ref_clk_fsel = 0x27;
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break;
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case 50000000:
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mpll_mul = 0x32;
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break;
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case 125000000:
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mpll_mul = 0x28;
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break;
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}
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val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
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···
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct dwc3_octeon *octeon;
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const char *hs_clock_type, *ss_clock_type;
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int ref_clk_sel, ref_clk_fsel, mpll_mul;
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int power_active_low, power_gpio;
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int err, len;
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u32 clock_rate;
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if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) {
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dev_err(dev, "No UCTL \"refclk-frequency\"\n");
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return -EINVAL;
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}
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if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) {
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dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
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return -EINVAL;
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}
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if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) {
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dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
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return -EINVAL;
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}
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ref_clk_sel = 2;
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if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
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ref_clk_sel = 0;
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else if (strcmp(hs_clock_type, "pll_ref_clk"))
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
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if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) {
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ref_clk_sel = 1;
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} else {
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ref_clk_sel = 3;
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if (strcmp(hs_clock_type, "pll_ref_clk"))
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dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
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hs_clock_type);
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}
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} else {
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dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
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ss_clock_type);
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}
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ref_clk_fsel = 0x07;
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switch (clock_rate) {
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default:
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dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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clock_rate);
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fallthrough;
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case 100000000:
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mpll_mul = 0x19;
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if (ref_clk_sel < 2)
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ref_clk_fsel = 0x27;
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break;
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case 50000000:
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mpll_mul = 0x32;
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break;
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case 125000000:
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mpll_mul = 0x28;
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break;
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}
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power_gpio = DWC3_GPIO_POWER_NONE;
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power_active_low = 0;
···
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if (IS_ERR(octeon->base))
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return PTR_ERR(octeon->base);
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err = dwc3_octeon_setup(octeon, power_gpio, power_active_low);
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err = dwc3_octeon_setup(octeon, ref_clk_sel, ref_clk_fsel, mpll_mul,
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power_gpio, power_active_low);
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if (err)
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return err;
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