Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull more powerpc updates from Michael Ellerman:
"The change to the Linux page table geometry was delayed for more
testing with 16G pages, and there's the new CPU features stuff which
just needed one more polish before going in. Plus a few changes from
Scott which came in a bit late. And then various fixes, mostly minor.
Summary highlights:
- rework the Linux page table geometry to lower memory usage on
64-bit Book3S (IBM chips) using the Hash MMU.
- support for a new device tree binding for discovering CPU features
on future firmwares.
- Freescale updates from Scott:
"Includes a fix for a powerpc/next mm regression on 64e, a fix for
a kernel hang on 64e when using a debugger inside a relocated
kernel, a qman fix, and misc qe improvements."
Thanks to: Christophe Leroy, Gavin Shan, Horia Geantă, LiuHailong,
Nicholas Piggin, Roy Pledge, Scott Wood, Valentin Longchamp"
* tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/64s: Support new device tree binding for discovering CPU features
powerpc: Don't print cpu_spec->cpu_name if it's NULL
of/fdt: introduce of_scan_flat_dt_subnodes and of_get_flat_dt_phandle
powerpc/64s: Fix unnecessary machine check handler relocation branch
powerpc/mm/book3s/64: Rework page table geometry for lower memory usage
powerpc: Fix distclean with Makefile.postlink
powerpc/64e: Don't place the stack beyond TASK_SIZE
powerpc/powernv: Block PCI config access on BCM5718 during EEH recovery
powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
soc/fsl/qbman: Disable IRQs for deferred QBMan work
soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm functions
soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
soc/fsl/qe: round brg_freq to 1kHz granularity
soc/fsl/qe: get rid of immrbar_virt_to_phys()
net: ethernet: ucc_geth: fix MEM_PART_MURAM mode
powerpc/64e: Fix hang when debugging programs with relocated kernel
+1546
-54
+248
Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt
+248
Documentation/devicetree/bindings/powerpc/ibm,powerpc-cpu-features.txt
···
1
+
*** NOTE ***
2
+
This document is copied from OPAL firmware
3
+
(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
4
+
5
+
There is more complete overview and documentation of features in that
6
+
source tree. All patches and modifications should go there.
7
+
************
8
+
9
+
ibm,powerpc-cpu-features binding
10
+
================================
11
+
12
+
This device tree binding describes CPU features available to software, with
13
+
enablement, privilege, and compatibility metadata.
14
+
15
+
More general description of design and implementation of this binding is
16
+
found in design.txt, which also points to documentation of specific features.
17
+
18
+
19
+
/cpus/ibm,powerpc-cpu-features node binding
20
+
-------------------------------------------
21
+
22
+
Node: ibm,powerpc-cpu-features
23
+
24
+
Description: Container of CPU feature nodes.
25
+
26
+
The node name must be "ibm,powerpc-cpu-features".
27
+
28
+
It is implemented as a child of the node "/cpus", but this must not be
29
+
assumed by parsers.
30
+
31
+
The node is optional but should be provided by new OPAL firmware.
32
+
33
+
Properties:
34
+
35
+
- compatible
36
+
Usage: required
37
+
Value type: string
38
+
Definition: "ibm,powerpc-cpu-features"
39
+
40
+
This compatibility refers to backwards compatibility of the overall
41
+
design with parsers that behave according to these guidelines. This can
42
+
be extended in a backward compatible manner which would not warrant a
43
+
revision of the compatible property.
44
+
45
+
- isa
46
+
Usage: required
47
+
Value type: <u32>
48
+
Definition:
49
+
50
+
isa that the CPU is currently running in. This provides instruction set
51
+
compatibility, less the individual feature nodes. For example, an ISA v3.0
52
+
implementation that lacks the "transactional-memory" cpufeature node
53
+
should not use transactional memory facilities.
54
+
55
+
Value corresponds to the "Power ISA Version" multiplied by 1000.
56
+
For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07.
57
+
The minor digit is available for revisions.
58
+
59
+
- display-name
60
+
Usage: optional
61
+
Value type: string
62
+
Definition:
63
+
64
+
A human readable name for the CPU.
65
+
66
+
/cpus/ibm,powerpc-cpu-features/example-feature node bindings
67
+
----------------------------------------------------------------
68
+
69
+
Each child node of cpu-features represents a CPU feature / capability.
70
+
71
+
Node: A string describing an architected CPU feature, e.g., "floating-point".
72
+
73
+
Description: A feature or capability supported by the CPUs.
74
+
75
+
The name of the node is a human readable string that forms the interface
76
+
used to describe features to software. Features are currently documented
77
+
in the code where they are implemented in skiboot/core/cpufeatures.c
78
+
79
+
Presence of the node indicates the feature is available.
80
+
81
+
Properties:
82
+
83
+
- isa
84
+
Usage: required
85
+
Value type: <u32>
86
+
Definition:
87
+
88
+
First level of the Power ISA that the feature appears in.
89
+
Software should filter out features when constraining the
90
+
environment to a particular ISA version.
91
+
92
+
Value is defined similarly to /cpus/features/isa
93
+
94
+
- usable-privilege
95
+
Usage: required
96
+
Value type: <u32> bit mask
97
+
Definition:
98
+
Bit numbers are LSB0
99
+
bit 0 - PR (problem state / user mode)
100
+
bit 1 - OS (privileged state)
101
+
bit 2 - HV (hypervisor state)
102
+
All other bits reserved and should be zero.
103
+
104
+
This property describes the privilege levels and/or software components
105
+
that can use the feature.
106
+
107
+
If bit 0 is set, then the hwcap-bit-nr property will exist.
108
+
109
+
110
+
- hv-support
111
+
Usage: optional
112
+
Value type: <u32> bit mask
113
+
Definition:
114
+
Bit numbers are LSB0
115
+
bit 0 - HFSCR
116
+
All other bits reserved and should be zero.
117
+
118
+
This property describes the HV privilege support required to enable the
119
+
feature to lesser privilege levels. If the property does not exist then no
120
+
support is required.
121
+
122
+
If no bits are set, the hypervisor must have explicit/custom support for
123
+
this feature.
124
+
125
+
If the HFSCR bit is set, then the hfscr-bit-nr property will exist and
126
+
the feature may be enabled by setting this bit in the HFSCR register.
127
+
128
+
129
+
- os-support
130
+
Usage: optional
131
+
Value type: <u32> bit mask
132
+
Definition:
133
+
Bit numbers are LSB0
134
+
bit 0 - FSCR
135
+
All other bits reserved and should be zero.
136
+
137
+
This property describes the OS privilege support required to enable the
138
+
feature to lesser privilege levels. If the property does not exist then no
139
+
support is required.
140
+
141
+
If no bits are set, the operating system must have explicit/custom support
142
+
for this feature.
143
+
144
+
If the FSCR bit is set, then the fscr-bit-nr property will exist and
145
+
the feature may be enabled by setting this bit in the FSCR register.
146
+
147
+
148
+
- hfscr-bit-nr
149
+
Usage: optional
150
+
Value type: <u32>
151
+
Definition: HFSCR bit position (LSB0)
152
+
153
+
This property exists when the hv-support property HFSCR bit is set. This
154
+
property describes the bit number in the HFSCR register that the
155
+
hypervisor must set in order to enable this feature.
156
+
157
+
This property also exists if an HFSCR bit corresponds with this feature.
158
+
This makes CPU feature parsing slightly simpler.
159
+
160
+
161
+
- fscr-bit-nr
162
+
Usage: optional
163
+
Value type: <u32>
164
+
Definition: FSCR bit position (LSB0)
165
+
166
+
This property exists when the os-support property FSCR bit is set. This
167
+
property describes the bit number in the FSCR register that the
168
+
operating system must set in order to enable this feature.
169
+
170
+
This property also exists if an FSCR bit corresponds with this feature.
171
+
This makes CPU feature parsing slightly simpler.
172
+
173
+
174
+
- hwcap-bit-nr
175
+
Usage: optional
176
+
Value type: <u32>
177
+
Definition: Linux ELF AUX vector bit position (LSB0)
178
+
179
+
This property may exist when the usable-privilege property value has PR bit set.
180
+
This property describes the bit number that should be set in the ELF AUX
181
+
hardware capability vectors in order to advertise this feature to userspace.
182
+
Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond
183
+
to 0-31 in AT_HWCAP2 vector, and so on. Missing AT_HWCAPx vectors implies
184
+
that the feature is not enabled or can not be advertised. Operating systems
185
+
may provide a number of unassigned hardware capability bits to allow for new
186
+
features to be advertised.
187
+
188
+
Some properties representing features created before this binding are
189
+
advertised to userspace without a one-to-one hwcap bit number may not specify
190
+
this bit. Operating system will handle those bits specifically. All new
191
+
features usable by userspace will have a hwcap-bit-nr property.
192
+
193
+
194
+
- dependencies
195
+
Usage: optional
196
+
Value type: <prop-encoded-array>
197
+
Definition:
198
+
199
+
If this property exists then it is a list of phandles to cpu feature
200
+
nodes that must be enabled for this feature to be enabled.
201
+
202
+
203
+
Example
204
+
-------
205
+
206
+
/cpus/ibm,powerpc-cpu-features {
207
+
compatible = "ibm,powerpc-cpu-features";
208
+
209
+
isa = <3020>;
210
+
211
+
darn {
212
+
isa = <3000>;
213
+
usable-privilege = <1 | 2 | 4>;
214
+
hwcap-bit-nr = <xx>;
215
+
};
216
+
217
+
scv {
218
+
isa = <3000>;
219
+
usable-privilege = <1 | 2>;
220
+
os-support = <0>;
221
+
hwcap-bit-nr = <xx>;
222
+
};
223
+
224
+
stop {
225
+
isa = <3000>;
226
+
usable-privilege = <2 | 4>;
227
+
hv-support = <0>;
228
+
os-support = <0>;
229
+
};
230
+
231
+
vsx2 (hypothetical) {
232
+
isa = <3010>;
233
+
usable-privilege = <1 | 2 | 4>;
234
+
hv-support = <0>;
235
+
os-support = <0>;
236
+
hwcap-bit-nr = <xx>;
237
+
};
238
+
239
+
vsx2-newinsns {
240
+
isa = <3020>;
241
+
usable-privilege = <1 | 2 | 4>;
242
+
os-support = <1>;
243
+
fscr-bit-nr = <xx>;
244
+
hwcap-bit-nr = <xx>;
245
+
dependencies = <&vsx2>;
246
+
};
247
+
248
+
};
+20
-1
Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
+20
-1
Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
···
13
13
- #gpio-cells : Should be two. The first cell is the pin number and the
14
14
second cell is used to specify optional parameters (currently unused).
15
15
- gpio-controller : Marks the port as GPIO controller.
16
+
Optional properties:
17
+
- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
18
+
on CPM1), this item tells which ports have an associated interrupt (ports are
19
+
listed in the same order as in PCINT register)
20
+
- interrupts : This property provides the list of interrupt for each GPIO having
21
+
one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
22
+
many interrupts as number of ones in the mask property. The first interrupt in
23
+
the list corresponds to the most significant bit of the mask.
24
+
- interrupt-parent : Parent for the above interrupt property.
16
25
17
-
Example of three SOC GPIO banks defined as gpio-controller nodes:
26
+
Example of four SOC GPIO banks defined as gpio-controller nodes:
18
27
19
28
CPM1_PIO_A: gpio-controller@950 {
20
29
#gpio-cells = <2>;
···
36
27
#gpio-cells = <2>;
37
28
compatible = "fsl,cpm1-pario-bank-b";
38
29
reg = <0xab8 0x10>;
30
+
gpio-controller;
31
+
};
32
+
33
+
CPM1_PIO_C: gpio-controller@960 {
34
+
#gpio-cells = <2>;
35
+
compatible = "fsl,cpm1-pario-bank-c";
36
+
reg = <0x960 0x10>;
37
+
fsl,cpm1-gpio-irq-mask = <0x0fff>;
38
+
interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
39
+
interrupt-parent = <&CPM_PIC>;
39
40
gpio-controller;
40
41
};
41
42
+16
arch/powerpc/Kconfig
+16
arch/powerpc/Kconfig
···
380
380
381
381
menu "Kernel options"
382
382
383
+
config PPC_DT_CPU_FTRS
384
+
bool "Device-tree based CPU feature discovery & setup"
385
+
depends on PPC_BOOK3S_64
386
+
default n
387
+
help
388
+
This enables code to use a new device tree binding for describing CPU
389
+
compatibility and features. Saying Y here will attempt to use the new
390
+
binding if the firmware provides it. Currently only the skiboot
391
+
firmware provides this binding.
392
+
If you're not sure say Y.
393
+
394
+
config PPC_CPUFEATURES_ENABLE_UNKNOWN
395
+
bool "cpufeatures pass through unknown features to guest/userspace"
396
+
depends on PPC_DT_CPU_FTRS
397
+
default y
398
+
383
399
config HIGHMEM
384
400
bool "High memory support"
385
401
depends on PPC32
+1
-1
arch/powerpc/Makefile.postlink
+1
-1
arch/powerpc/Makefile.postlink
+3
-3
arch/powerpc/include/asm/book3s/64/hash-64k.h
+3
-3
arch/powerpc/include/asm/book3s/64/hash-64k.h
···
2
2
#define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
3
3
4
4
#define H_PTE_INDEX_SIZE 8
5
-
#define H_PMD_INDEX_SIZE 5
6
-
#define H_PUD_INDEX_SIZE 5
7
-
#define H_PGD_INDEX_SIZE 15
5
+
#define H_PMD_INDEX_SIZE 10
6
+
#define H_PUD_INDEX_SIZE 7
7
+
#define H_PGD_INDEX_SIZE 8
8
8
9
9
/*
10
10
* 64k aligned address free up few of the lower bits of RPN for us
+2
arch/powerpc/include/asm/cpm1.h
+2
arch/powerpc/include/asm/cpm1.h
+3
-3
arch/powerpc/include/asm/cpu_has_feature.h
+3
-3
arch/powerpc/include/asm/cpu_has_feature.h
···
1
-
#ifndef __ASM_POWERPC_CPUFEATURES_H
2
-
#define __ASM_POWERPC_CPUFEATURES_H
1
+
#ifndef __ASM_POWERPC_CPU_HAS_FEATURE_H
2
+
#define __ASM_POWERPC_CPU_HAS_FEATURE_H
3
3
4
4
#ifndef __ASSEMBLY__
5
5
···
52
52
#endif
53
53
54
54
#endif /* __ASSEMBLY__ */
55
-
#endif /* __ASM_POWERPC_CPUFEATURE_H */
55
+
#endif /* __ASM_POWERPC_CPU_HAS_FEATURE_H */
+2
arch/powerpc/include/asm/cputable.h
+2
arch/powerpc/include/asm/cputable.h
···
118
118
119
119
extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
120
120
121
+
extern void set_cur_cpu_spec(struct cpu_spec *s);
121
122
extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
123
+
extern void identify_cpu_name(unsigned int pvr);
122
124
extern void do_feature_fixups(unsigned long value, void *fixup_start,
123
125
void *fixup_end);
124
126
+26
arch/powerpc/include/asm/dt_cpu_ftrs.h
+26
arch/powerpc/include/asm/dt_cpu_ftrs.h
···
1
+
#ifndef __ASM_POWERPC_DT_CPU_FTRS_H
2
+
#define __ASM_POWERPC_DT_CPU_FTRS_H
3
+
4
+
/*
5
+
* Copyright 2017, IBM Corporation
6
+
* cpufeatures is the new way to discover CPU features with /cpus/features
7
+
* devicetree. This supersedes PVR based discovery ("cputable"), and older
8
+
* device tree feature advertisement.
9
+
*/
10
+
11
+
#include <linux/types.h>
12
+
#include <asm/asm-compat.h>
13
+
#include <asm/feature-fixups.h>
14
+
#include <uapi/asm/cputable.h>
15
+
16
+
#ifdef CONFIG_PPC_DT_CPU_FTRS
17
+
bool dt_cpu_ftrs_init(void *fdt);
18
+
void dt_cpu_ftrs_scan(void);
19
+
bool dt_cpu_ftrs_in_use(void);
20
+
#else
21
+
static inline bool dt_cpu_ftrs_init(void *fdt) { return false; }
22
+
static inline void dt_cpu_ftrs_scan(void) { }
23
+
static inline bool dt_cpu_ftrs_in_use(void) { return false; }
24
+
#endif
25
+
26
+
#endif /* __ASM_POWERPC_DT_CPU_FTRS_H */
+5
arch/powerpc/include/asm/processor.h
+5
arch/powerpc/include/asm/processor.h
···
151
151
152
152
#ifdef __powerpc64__
153
153
154
+
#ifdef CONFIG_PPC_BOOK3S_64
154
155
/* Limit stack to 128TB */
155
156
#define STACK_TOP_USER64 TASK_SIZE_128TB
157
+
#else
158
+
#define STACK_TOP_USER64 TASK_SIZE_USER64
159
+
#endif
160
+
156
161
#define STACK_TOP_USER32 TASK_SIZE_USER32
157
162
158
163
#define STACK_TOP (is_32bit_task() ? \
+1
arch/powerpc/include/asm/reg.h
+1
arch/powerpc/include/asm/reg.h
+7
arch/powerpc/include/uapi/asm/cputable.h
+7
arch/powerpc/include/uapi/asm/cputable.h
···
47
47
#define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.00 */
48
48
#define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */
49
49
50
+
/*
51
+
* IMPORTANT!
52
+
* All future PPC_FEATURE definitions should be allocated in cooperation with
53
+
* OPAL / skiboot firmware, in accordance with the ibm,powerpc-cpu-features
54
+
* device tree binding.
55
+
*/
56
+
50
57
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
+1
arch/powerpc/kernel/Makefile
+1
arch/powerpc/kernel/Makefile
···
56
56
obj-$(CONFIG_PPC_RTAS_DAEMON) += rtasd.o
57
57
obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o
58
58
obj-$(CONFIG_RTAS_PROC) += rtas-proc.o
59
+
obj-$(CONFIG_PPC_DT_CPU_FTRS) += dt_cpu_ftrs.o
59
60
obj-$(CONFIG_EEH) += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
60
61
eeh_driver.o eeh_event.o eeh_sysfs.o
61
62
obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
+35
-2
arch/powerpc/kernel/cputable.c
+35
-2
arch/powerpc/kernel/cputable.c
···
23
23
#include <asm/mmu.h>
24
24
#include <asm/setup.h>
25
25
26
-
struct cpu_spec* cur_cpu_spec = NULL;
26
+
static struct cpu_spec the_cpu_spec __read_mostly;
27
+
28
+
struct cpu_spec* cur_cpu_spec __read_mostly = NULL;
27
29
EXPORT_SYMBOL(cur_cpu_spec);
28
30
29
31
/* The platform string corresponding to the real PVR */
···
2181
2179
#endif /* CONFIG_E500 */
2182
2180
};
2183
2181
2184
-
static struct cpu_spec the_cpu_spec;
2182
+
void __init set_cur_cpu_spec(struct cpu_spec *s)
2183
+
{
2184
+
struct cpu_spec *t = &the_cpu_spec;
2185
+
2186
+
t = PTRRELOC(t);
2187
+
*t = *s;
2188
+
2189
+
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
2190
+
}
2185
2191
2186
2192
static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
2187
2193
struct cpu_spec *s)
···
2275
2265
2276
2266
return NULL;
2277
2267
}
2268
+
2269
+
/*
2270
+
* Used by cpufeatures to get the name for CPUs with a PVR table.
2271
+
* If they don't hae a PVR table, cpufeatures gets the name from
2272
+
* cpu device-tree node.
2273
+
*/
2274
+
void __init identify_cpu_name(unsigned int pvr)
2275
+
{
2276
+
struct cpu_spec *s = cpu_specs;
2277
+
struct cpu_spec *t = &the_cpu_spec;
2278
+
int i;
2279
+
2280
+
s = PTRRELOC(s);
2281
+
t = PTRRELOC(t);
2282
+
2283
+
for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
2284
+
if ((pvr & s->pvr_mask) == s->pvr_value) {
2285
+
t->cpu_name = s->cpu_name;
2286
+
return;
2287
+
}
2288
+
}
2289
+
}
2290
+
2278
2291
2279
2292
#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
2280
2293
struct static_key_true cpu_feature_keys[NUM_CPU_FTR_KEYS] = {
+1031
arch/powerpc/kernel/dt_cpu_ftrs.c
+1031
arch/powerpc/kernel/dt_cpu_ftrs.c
···
1
+
/*
2
+
* Copyright 2017, Nicholas Piggin, IBM Corporation
3
+
* Licensed under GPLv2.
4
+
*/
5
+
6
+
#define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
7
+
8
+
#include <linux/export.h>
9
+
#include <linux/init.h>
10
+
#include <linux/jump_label.h>
11
+
#include <linux/memblock.h>
12
+
#include <linux/printk.h>
13
+
#include <linux/sched.h>
14
+
#include <linux/string.h>
15
+
#include <linux/threads.h>
16
+
17
+
#include <asm/cputable.h>
18
+
#include <asm/dt_cpu_ftrs.h>
19
+
#include <asm/mmu.h>
20
+
#include <asm/oprofile_impl.h>
21
+
#include <asm/prom.h>
22
+
#include <asm/setup.h>
23
+
24
+
25
+
/* Device-tree visible constants follow */
26
+
#define ISA_V2_07B 2070
27
+
#define ISA_V3_0B 3000
28
+
29
+
#define USABLE_PR (1U << 0)
30
+
#define USABLE_OS (1U << 1)
31
+
#define USABLE_HV (1U << 2)
32
+
33
+
#define HV_SUPPORT_HFSCR (1U << 0)
34
+
#define OS_SUPPORT_FSCR (1U << 0)
35
+
36
+
/* For parsing, we define all bits set as "NONE" case */
37
+
#define HV_SUPPORT_NONE 0xffffffffU
38
+
#define OS_SUPPORT_NONE 0xffffffffU
39
+
40
+
struct dt_cpu_feature {
41
+
const char *name;
42
+
uint32_t isa;
43
+
uint32_t usable_privilege;
44
+
uint32_t hv_support;
45
+
uint32_t os_support;
46
+
uint32_t hfscr_bit_nr;
47
+
uint32_t fscr_bit_nr;
48
+
uint32_t hwcap_bit_nr;
49
+
/* fdt parsing */
50
+
unsigned long node;
51
+
int enabled;
52
+
int disabled;
53
+
};
54
+
55
+
#define CPU_FTRS_BASE \
56
+
(CPU_FTR_USE_TB | \
57
+
CPU_FTR_LWSYNC | \
58
+
CPU_FTR_FPU_UNAVAILABLE |\
59
+
CPU_FTR_NODSISRALIGN |\
60
+
CPU_FTR_NOEXECUTE |\
61
+
CPU_FTR_COHERENT_ICACHE | \
62
+
CPU_FTR_STCX_CHECKS_ADDRESS |\
63
+
CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
64
+
CPU_FTR_DAWR | \
65
+
CPU_FTR_ARCH_206 |\
66
+
CPU_FTR_ARCH_207S)
67
+
68
+
#define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
69
+
70
+
#define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
71
+
PPC_FEATURE_ARCH_2_06 |\
72
+
PPC_FEATURE_ICACHE_SNOOP)
73
+
#define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
74
+
PPC_FEATURE2_ISEL)
75
+
/*
76
+
* Set up the base CPU
77
+
*/
78
+
79
+
extern void __flush_tlb_power8(unsigned int action);
80
+
extern void __flush_tlb_power9(unsigned int action);
81
+
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
82
+
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
83
+
84
+
static int hv_mode;
85
+
86
+
static struct {
87
+
u64 lpcr;
88
+
u64 hfscr;
89
+
u64 fscr;
90
+
} system_registers;
91
+
92
+
static void (*init_pmu_registers)(void);
93
+
94
+
static void cpufeatures_flush_tlb(void)
95
+
{
96
+
unsigned long rb;
97
+
unsigned int i, num_sets;
98
+
99
+
/*
100
+
* This is a temporary measure to keep equivalent TLB flush as the
101
+
* cputable based setup code.
102
+
*/
103
+
switch (PVR_VER(mfspr(SPRN_PVR))) {
104
+
case PVR_POWER8:
105
+
case PVR_POWER8E:
106
+
case PVR_POWER8NVL:
107
+
num_sets = POWER8_TLB_SETS;
108
+
break;
109
+
case PVR_POWER9:
110
+
num_sets = POWER9_TLB_SETS_HASH;
111
+
break;
112
+
default:
113
+
num_sets = 1;
114
+
pr_err("unknown CPU version for boot TLB flush\n");
115
+
break;
116
+
}
117
+
118
+
asm volatile("ptesync" : : : "memory");
119
+
rb = TLBIEL_INVAL_SET;
120
+
for (i = 0; i < num_sets; i++) {
121
+
asm volatile("tlbiel %0" : : "r" (rb));
122
+
rb += 1 << TLBIEL_INVAL_SET_SHIFT;
123
+
}
124
+
asm volatile("ptesync" : : : "memory");
125
+
}
126
+
127
+
static void __restore_cpu_cpufeatures(void)
128
+
{
129
+
/*
130
+
* LPCR is restored by the power on engine already. It can be changed
131
+
* after early init e.g., by radix enable, and we have no unified API
132
+
* for saving and restoring such SPRs.
133
+
*
134
+
* This ->restore hook should really be removed from idle and register
135
+
* restore moved directly into the idle restore code, because this code
136
+
* doesn't know how idle is implemented or what it needs restored here.
137
+
*
138
+
* The best we can do to accommodate secondary boot and idle restore
139
+
* for now is "or" LPCR with existing.
140
+
*/
141
+
142
+
mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
143
+
if (hv_mode) {
144
+
mtspr(SPRN_LPID, 0);
145
+
mtspr(SPRN_HFSCR, system_registers.hfscr);
146
+
}
147
+
mtspr(SPRN_FSCR, system_registers.fscr);
148
+
149
+
if (init_pmu_registers)
150
+
init_pmu_registers();
151
+
152
+
cpufeatures_flush_tlb();
153
+
}
154
+
155
+
static char dt_cpu_name[64];
156
+
157
+
static struct cpu_spec __initdata base_cpu_spec = {
158
+
.cpu_name = NULL,
159
+
.cpu_features = CPU_FTRS_BASE,
160
+
.cpu_user_features = COMMON_USER_BASE,
161
+
.cpu_user_features2 = COMMON_USER2_BASE,
162
+
.mmu_features = 0,
163
+
.icache_bsize = 32, /* minimum block size, fixed by */
164
+
.dcache_bsize = 32, /* cache info init. */
165
+
.num_pmcs = 0,
166
+
.pmc_type = PPC_PMC_DEFAULT,
167
+
.oprofile_cpu_type = NULL,
168
+
.oprofile_type = PPC_OPROFILE_INVALID,
169
+
.cpu_setup = NULL,
170
+
.cpu_restore = __restore_cpu_cpufeatures,
171
+
.flush_tlb = NULL,
172
+
.machine_check_early = NULL,
173
+
.platform = NULL,
174
+
};
175
+
176
+
static void __init cpufeatures_setup_cpu(void)
177
+
{
178
+
set_cur_cpu_spec(&base_cpu_spec);
179
+
180
+
cur_cpu_spec->pvr_mask = -1;
181
+
cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
182
+
183
+
/* Initialize the base environment -- clear FSCR/HFSCR. */
184
+
hv_mode = !!(mfmsr() & MSR_HV);
185
+
if (hv_mode) {
186
+
/* CPU_FTR_HVMODE is used early in PACA setup */
187
+
cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
188
+
mtspr(SPRN_HFSCR, 0);
189
+
}
190
+
mtspr(SPRN_FSCR, 0);
191
+
192
+
/*
193
+
* LPCR does not get cleared, to match behaviour with secondaries
194
+
* in __restore_cpu_cpufeatures. Once the idle code is fixed, this
195
+
* could clear LPCR too.
196
+
*/
197
+
}
198
+
199
+
static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
200
+
{
201
+
if (f->hv_support == HV_SUPPORT_NONE) {
202
+
} else if (f->hv_support & HV_SUPPORT_HFSCR) {
203
+
u64 hfscr = mfspr(SPRN_HFSCR);
204
+
hfscr |= 1UL << f->hfscr_bit_nr;
205
+
mtspr(SPRN_HFSCR, hfscr);
206
+
} else {
207
+
/* Does not have a known recipe */
208
+
return 0;
209
+
}
210
+
211
+
if (f->os_support == OS_SUPPORT_NONE) {
212
+
} else if (f->os_support & OS_SUPPORT_FSCR) {
213
+
u64 fscr = mfspr(SPRN_FSCR);
214
+
fscr |= 1UL << f->fscr_bit_nr;
215
+
mtspr(SPRN_FSCR, fscr);
216
+
} else {
217
+
/* Does not have a known recipe */
218
+
return 0;
219
+
}
220
+
221
+
if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
222
+
uint32_t word = f->hwcap_bit_nr / 32;
223
+
uint32_t bit = f->hwcap_bit_nr % 32;
224
+
225
+
if (word == 0)
226
+
cur_cpu_spec->cpu_user_features |= 1U << bit;
227
+
else if (word == 1)
228
+
cur_cpu_spec->cpu_user_features2 |= 1U << bit;
229
+
else
230
+
pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
231
+
}
232
+
233
+
return 1;
234
+
}
235
+
236
+
static int __init feat_enable(struct dt_cpu_feature *f)
237
+
{
238
+
if (f->hv_support != HV_SUPPORT_NONE) {
239
+
if (f->hfscr_bit_nr != -1) {
240
+
u64 hfscr = mfspr(SPRN_HFSCR);
241
+
hfscr |= 1UL << f->hfscr_bit_nr;
242
+
mtspr(SPRN_HFSCR, hfscr);
243
+
}
244
+
}
245
+
246
+
if (f->os_support != OS_SUPPORT_NONE) {
247
+
if (f->fscr_bit_nr != -1) {
248
+
u64 fscr = mfspr(SPRN_FSCR);
249
+
fscr |= 1UL << f->fscr_bit_nr;
250
+
mtspr(SPRN_FSCR, fscr);
251
+
}
252
+
}
253
+
254
+
if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
255
+
uint32_t word = f->hwcap_bit_nr / 32;
256
+
uint32_t bit = f->hwcap_bit_nr % 32;
257
+
258
+
if (word == 0)
259
+
cur_cpu_spec->cpu_user_features |= 1U << bit;
260
+
else if (word == 1)
261
+
cur_cpu_spec->cpu_user_features2 |= 1U << bit;
262
+
else
263
+
pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
264
+
}
265
+
266
+
return 1;
267
+
}
268
+
269
+
static int __init feat_disable(struct dt_cpu_feature *f)
270
+
{
271
+
return 0;
272
+
}
273
+
274
+
static int __init feat_enable_hv(struct dt_cpu_feature *f)
275
+
{
276
+
u64 lpcr;
277
+
278
+
if (!hv_mode) {
279
+
pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
280
+
return 0;
281
+
}
282
+
283
+
mtspr(SPRN_LPID, 0);
284
+
285
+
lpcr = mfspr(SPRN_LPCR);
286
+
lpcr &= ~LPCR_LPES0; /* HV external interrupts */
287
+
mtspr(SPRN_LPCR, lpcr);
288
+
289
+
cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
290
+
291
+
return 1;
292
+
}
293
+
294
+
static int __init feat_enable_le(struct dt_cpu_feature *f)
295
+
{
296
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
297
+
return 1;
298
+
}
299
+
300
+
static int __init feat_enable_smt(struct dt_cpu_feature *f)
301
+
{
302
+
cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
303
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
304
+
return 1;
305
+
}
306
+
307
+
static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
308
+
{
309
+
u64 lpcr;
310
+
311
+
/* Set PECE wakeup modes for ISA 207 */
312
+
lpcr = mfspr(SPRN_LPCR);
313
+
lpcr |= LPCR_PECE0;
314
+
lpcr |= LPCR_PECE1;
315
+
lpcr |= LPCR_PECE2;
316
+
mtspr(SPRN_LPCR, lpcr);
317
+
318
+
return 1;
319
+
}
320
+
321
+
static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
322
+
{
323
+
cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
324
+
325
+
return 1;
326
+
}
327
+
328
+
static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
329
+
{
330
+
u64 lpcr;
331
+
332
+
/* Set PECE wakeup modes for ISAv3.0B */
333
+
lpcr = mfspr(SPRN_LPCR);
334
+
lpcr |= LPCR_PECE0;
335
+
lpcr |= LPCR_PECE1;
336
+
lpcr |= LPCR_PECE2;
337
+
mtspr(SPRN_LPCR, lpcr);
338
+
339
+
return 1;
340
+
}
341
+
342
+
static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
343
+
{
344
+
u64 lpcr;
345
+
346
+
lpcr = mfspr(SPRN_LPCR);
347
+
lpcr &= ~LPCR_ISL;
348
+
349
+
/* VRMASD */
350
+
lpcr |= LPCR_VPM0;
351
+
lpcr &= ~LPCR_VPM1;
352
+
lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
353
+
mtspr(SPRN_LPCR, lpcr);
354
+
355
+
cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
356
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
357
+
358
+
return 1;
359
+
}
360
+
361
+
static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
362
+
{
363
+
u64 lpcr;
364
+
365
+
lpcr = mfspr(SPRN_LPCR);
366
+
lpcr &= ~LPCR_ISL;
367
+
mtspr(SPRN_LPCR, lpcr);
368
+
369
+
cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
370
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
371
+
372
+
return 1;
373
+
}
374
+
375
+
376
+
static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
377
+
{
378
+
#ifdef CONFIG_PPC_RADIX_MMU
379
+
cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
380
+
cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
381
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
382
+
383
+
return 1;
384
+
#endif
385
+
return 0;
386
+
}
387
+
388
+
static int __init feat_enable_dscr(struct dt_cpu_feature *f)
389
+
{
390
+
u64 lpcr;
391
+
392
+
feat_enable(f);
393
+
394
+
lpcr = mfspr(SPRN_LPCR);
395
+
lpcr &= ~LPCR_DPFD;
396
+
lpcr |= (4UL << LPCR_DPFD_SH);
397
+
mtspr(SPRN_LPCR, lpcr);
398
+
399
+
return 1;
400
+
}
401
+
402
+
static void hfscr_pmu_enable(void)
403
+
{
404
+
u64 hfscr = mfspr(SPRN_HFSCR);
405
+
hfscr |= PPC_BIT(60);
406
+
mtspr(SPRN_HFSCR, hfscr);
407
+
}
408
+
409
+
static void init_pmu_power8(void)
410
+
{
411
+
if (hv_mode) {
412
+
mtspr(SPRN_MMCRC, 0);
413
+
mtspr(SPRN_MMCRH, 0);
414
+
}
415
+
416
+
mtspr(SPRN_MMCRA, 0);
417
+
mtspr(SPRN_MMCR0, 0);
418
+
mtspr(SPRN_MMCR1, 0);
419
+
mtspr(SPRN_MMCR2, 0);
420
+
mtspr(SPRN_MMCRS, 0);
421
+
}
422
+
423
+
static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
424
+
{
425
+
cur_cpu_spec->platform = "power8";
426
+
cur_cpu_spec->flush_tlb = __flush_tlb_power8;
427
+
cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
428
+
429
+
return 1;
430
+
}
431
+
432
+
static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
433
+
{
434
+
hfscr_pmu_enable();
435
+
436
+
init_pmu_power8();
437
+
init_pmu_registers = init_pmu_power8;
438
+
439
+
cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
440
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
441
+
if (pvr_version_is(PVR_POWER8E))
442
+
cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
443
+
444
+
cur_cpu_spec->num_pmcs = 6;
445
+
cur_cpu_spec->pmc_type = PPC_PMC_IBM;
446
+
cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
447
+
448
+
return 1;
449
+
}
450
+
451
+
static void init_pmu_power9(void)
452
+
{
453
+
if (hv_mode)
454
+
mtspr(SPRN_MMCRC, 0);
455
+
456
+
mtspr(SPRN_MMCRA, 0);
457
+
mtspr(SPRN_MMCR0, 0);
458
+
mtspr(SPRN_MMCR1, 0);
459
+
mtspr(SPRN_MMCR2, 0);
460
+
}
461
+
462
+
static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
463
+
{
464
+
cur_cpu_spec->platform = "power9";
465
+
cur_cpu_spec->flush_tlb = __flush_tlb_power9;
466
+
cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
467
+
468
+
return 1;
469
+
}
470
+
471
+
static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
472
+
{
473
+
hfscr_pmu_enable();
474
+
475
+
init_pmu_power9();
476
+
init_pmu_registers = init_pmu_power9;
477
+
478
+
cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
479
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
480
+
481
+
cur_cpu_spec->num_pmcs = 6;
482
+
cur_cpu_spec->pmc_type = PPC_PMC_IBM;
483
+
cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
484
+
485
+
return 1;
486
+
}
487
+
488
+
static int __init feat_enable_tm(struct dt_cpu_feature *f)
489
+
{
490
+
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
491
+
feat_enable(f);
492
+
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
493
+
return 1;
494
+
#endif
495
+
return 0;
496
+
}
497
+
498
+
static int __init feat_enable_fp(struct dt_cpu_feature *f)
499
+
{
500
+
feat_enable(f);
501
+
cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
502
+
503
+
return 1;
504
+
}
505
+
506
+
static int __init feat_enable_vector(struct dt_cpu_feature *f)
507
+
{
508
+
#ifdef CONFIG_ALTIVEC
509
+
feat_enable(f);
510
+
cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
511
+
cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
512
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
513
+
514
+
return 1;
515
+
#endif
516
+
return 0;
517
+
}
518
+
519
+
static int __init feat_enable_vsx(struct dt_cpu_feature *f)
520
+
{
521
+
#ifdef CONFIG_VSX
522
+
feat_enable(f);
523
+
cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
524
+
cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
525
+
526
+
return 1;
527
+
#endif
528
+
return 0;
529
+
}
530
+
531
+
static int __init feat_enable_purr(struct dt_cpu_feature *f)
532
+
{
533
+
cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
534
+
535
+
return 1;
536
+
}
537
+
538
+
static int __init feat_enable_ebb(struct dt_cpu_feature *f)
539
+
{
540
+
/*
541
+
* PPC_FEATURE2_EBB is enabled in PMU init code because it has
542
+
* historically been related to the PMU facility. This may have
543
+
* to be decoupled if EBB becomes more generic. For now, follow
544
+
* existing convention.
545
+
*/
546
+
f->hwcap_bit_nr = -1;
547
+
feat_enable(f);
548
+
549
+
return 1;
550
+
}
551
+
552
+
static int __init feat_enable_dbell(struct dt_cpu_feature *f)
553
+
{
554
+
u64 lpcr;
555
+
556
+
/* P9 has an HFSCR for privileged state */
557
+
feat_enable(f);
558
+
559
+
cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
560
+
561
+
lpcr = mfspr(SPRN_LPCR);
562
+
lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
563
+
mtspr(SPRN_LPCR, lpcr);
564
+
565
+
return 1;
566
+
}
567
+
568
+
static int __init feat_enable_hvi(struct dt_cpu_feature *f)
569
+
{
570
+
u64 lpcr;
571
+
572
+
/*
573
+
* POWER9 XIVE interrupts including in OPAL XICS compatibility
574
+
* are always delivered as hypervisor virtualization interrupts (HVI)
575
+
* rather than EE.
576
+
*
577
+
* However LPES0 is not set here, in the chance that an EE does get
578
+
* delivered to the host somehow, the EE handler would not expect it
579
+
* to be delivered in LPES0 mode (e.g., using SRR[01]). This could
580
+
* happen if there is a bug in interrupt controller code, or IC is
581
+
* misconfigured in systemsim.
582
+
*/
583
+
584
+
lpcr = mfspr(SPRN_LPCR);
585
+
lpcr |= LPCR_HVICE; /* enable hvi interrupts */
586
+
lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
587
+
lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
588
+
mtspr(SPRN_LPCR, lpcr);
589
+
590
+
return 1;
591
+
}
592
+
593
+
static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
594
+
{
595
+
cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
596
+
597
+
return 1;
598
+
}
599
+
600
+
struct dt_cpu_feature_match {
601
+
const char *name;
602
+
int (*enable)(struct dt_cpu_feature *f);
603
+
u64 cpu_ftr_bit_mask;
604
+
};
605
+
606
+
static struct dt_cpu_feature_match __initdata
607
+
dt_cpu_feature_match_table[] = {
608
+
{"hypervisor", feat_enable_hv, 0},
609
+
{"big-endian", feat_enable, 0},
610
+
{"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
611
+
{"smt", feat_enable_smt, 0},
612
+
{"interrupt-facilities", feat_enable, 0},
613
+
{"timer-facilities", feat_enable, 0},
614
+
{"timer-facilities-v3", feat_enable, 0},
615
+
{"debug-facilities", feat_enable, 0},
616
+
{"come-from-address-register", feat_enable, CPU_FTR_CFAR},
617
+
{"branch-tracing", feat_enable, 0},
618
+
{"floating-point", feat_enable_fp, 0},
619
+
{"vector", feat_enable_vector, 0},
620
+
{"vector-scalar", feat_enable_vsx, 0},
621
+
{"vector-scalar-v3", feat_enable, 0},
622
+
{"decimal-floating-point", feat_enable, 0},
623
+
{"decimal-integer", feat_enable, 0},
624
+
{"quadword-load-store", feat_enable, 0},
625
+
{"vector-crypto", feat_enable, 0},
626
+
{"mmu-hash", feat_enable_mmu_hash, 0},
627
+
{"mmu-radix", feat_enable_mmu_radix, 0},
628
+
{"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
629
+
{"virtual-page-class-key-protection", feat_enable, 0},
630
+
{"transactional-memory", feat_enable_tm, CPU_FTR_TM},
631
+
{"transactional-memory-v3", feat_enable_tm, 0},
632
+
{"idle-nap", feat_enable_idle_nap, 0},
633
+
{"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
634
+
{"idle-stop", feat_enable_idle_stop, 0},
635
+
{"machine-check-power8", feat_enable_mce_power8, 0},
636
+
{"performance-monitor-power8", feat_enable_pmu_power8, 0},
637
+
{"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
638
+
{"event-based-branch", feat_enable_ebb, 0},
639
+
{"target-address-register", feat_enable, 0},
640
+
{"branch-history-rolling-buffer", feat_enable, 0},
641
+
{"control-register", feat_enable, CPU_FTR_CTRL},
642
+
{"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
643
+
{"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
644
+
{"processor-utilization-of-resources-register", feat_enable_purr, 0},
645
+
{"subcore", feat_enable, CPU_FTR_SUBCORE},
646
+
{"no-execute", feat_enable, 0},
647
+
{"strong-access-ordering", feat_enable, CPU_FTR_SAO},
648
+
{"cache-inhibited-large-page", feat_enable_large_ci, 0},
649
+
{"coprocessor-icswx", feat_enable, CPU_FTR_ICSWX},
650
+
{"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
651
+
{"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
652
+
{"wait", feat_enable, 0},
653
+
{"atomic-memory-operations", feat_enable, 0},
654
+
{"branch-v3", feat_enable, 0},
655
+
{"copy-paste", feat_enable, 0},
656
+
{"decimal-floating-point-v3", feat_enable, 0},
657
+
{"decimal-integer-v3", feat_enable, 0},
658
+
{"fixed-point-v3", feat_enable, 0},
659
+
{"floating-point-v3", feat_enable, 0},
660
+
{"group-start-register", feat_enable, 0},
661
+
{"pc-relative-addressing", feat_enable, 0},
662
+
{"machine-check-power9", feat_enable_mce_power9, 0},
663
+
{"performance-monitor-power9", feat_enable_pmu_power9, 0},
664
+
{"event-based-branch-v3", feat_enable, 0},
665
+
{"random-number-generator", feat_enable, 0},
666
+
{"system-call-vectored", feat_disable, 0},
667
+
{"trace-interrupt-v3", feat_enable, 0},
668
+
{"vector-v3", feat_enable, 0},
669
+
{"vector-binary128", feat_enable, 0},
670
+
{"vector-binary16", feat_enable, 0},
671
+
{"wait-v3", feat_enable, 0},
672
+
};
673
+
674
+
/* XXX: how to configure this? Default + boot time? */
675
+
#ifdef CONFIG_PPC_CPUFEATURES_ENABLE_UNKNOWN
676
+
#define CPU_FEATURE_ENABLE_UNKNOWN 1
677
+
#else
678
+
#define CPU_FEATURE_ENABLE_UNKNOWN 0
679
+
#endif
680
+
681
+
static void __init cpufeatures_setup_start(u32 isa)
682
+
{
683
+
pr_info("setup for ISA %d\n", isa);
684
+
685
+
if (isa >= 3000) {
686
+
cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
687
+
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
688
+
}
689
+
}
690
+
691
+
static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
692
+
{
693
+
const struct dt_cpu_feature_match *m;
694
+
bool known = false;
695
+
int i;
696
+
697
+
for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
698
+
m = &dt_cpu_feature_match_table[i];
699
+
if (!strcmp(f->name, m->name)) {
700
+
known = true;
701
+
if (m->enable(f))
702
+
break;
703
+
704
+
pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
705
+
f->name);
706
+
return false;
707
+
}
708
+
}
709
+
710
+
if (!known && CPU_FEATURE_ENABLE_UNKNOWN) {
711
+
if (!feat_try_enable_unknown(f)) {
712
+
pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
713
+
f->name);
714
+
return false;
715
+
}
716
+
}
717
+
718
+
if (m->cpu_ftr_bit_mask)
719
+
cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
720
+
721
+
if (known)
722
+
pr_debug("enabling: %s\n", f->name);
723
+
else
724
+
pr_debug("enabling: %s (unknown)\n", f->name);
725
+
726
+
return true;
727
+
}
728
+
729
+
static __init void cpufeatures_cpu_quirks(void)
730
+
{
731
+
int version = mfspr(SPRN_PVR);
732
+
733
+
/*
734
+
* Not all quirks can be derived from the cpufeatures device tree.
735
+
*/
736
+
if ((version & 0xffffff00) == 0x004e0100)
737
+
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
738
+
}
739
+
740
+
static void __init cpufeatures_setup_finished(void)
741
+
{
742
+
cpufeatures_cpu_quirks();
743
+
744
+
if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
745
+
pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
746
+
cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
747
+
}
748
+
749
+
system_registers.lpcr = mfspr(SPRN_LPCR);
750
+
system_registers.hfscr = mfspr(SPRN_HFSCR);
751
+
system_registers.fscr = mfspr(SPRN_FSCR);
752
+
753
+
cpufeatures_flush_tlb();
754
+
755
+
pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
756
+
cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
757
+
}
758
+
759
+
static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
760
+
int depth, void *data)
761
+
{
762
+
if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
763
+
&& of_get_flat_dt_prop(node, "isa", NULL))
764
+
return 1;
765
+
766
+
return 0;
767
+
}
768
+
769
+
static bool __initdata using_dt_cpu_ftrs = false;
770
+
771
+
bool __init dt_cpu_ftrs_in_use(void)
772
+
{
773
+
return using_dt_cpu_ftrs;
774
+
}
775
+
776
+
bool __init dt_cpu_ftrs_init(void *fdt)
777
+
{
778
+
/* Setup and verify the FDT, if it fails we just bail */
779
+
if (!early_init_dt_verify(fdt))
780
+
return false;
781
+
782
+
if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
783
+
return false;
784
+
785
+
cpufeatures_setup_cpu();
786
+
787
+
using_dt_cpu_ftrs = true;
788
+
return true;
789
+
}
790
+
791
+
static int nr_dt_cpu_features;
792
+
static struct dt_cpu_feature *dt_cpu_features;
793
+
794
+
static int __init process_cpufeatures_node(unsigned long node,
795
+
const char *uname, int i)
796
+
{
797
+
const __be32 *prop;
798
+
struct dt_cpu_feature *f;
799
+
int len;
800
+
801
+
f = &dt_cpu_features[i];
802
+
memset(f, 0, sizeof(struct dt_cpu_feature));
803
+
804
+
f->node = node;
805
+
806
+
f->name = uname;
807
+
808
+
prop = of_get_flat_dt_prop(node, "isa", &len);
809
+
if (!prop) {
810
+
pr_warn("%s: missing isa property\n", uname);
811
+
return 0;
812
+
}
813
+
f->isa = be32_to_cpup(prop);
814
+
815
+
prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
816
+
if (!prop) {
817
+
pr_warn("%s: missing usable-privilege property", uname);
818
+
return 0;
819
+
}
820
+
f->usable_privilege = be32_to_cpup(prop);
821
+
822
+
prop = of_get_flat_dt_prop(node, "hv-support", &len);
823
+
if (prop)
824
+
f->hv_support = be32_to_cpup(prop);
825
+
else
826
+
f->hv_support = HV_SUPPORT_NONE;
827
+
828
+
prop = of_get_flat_dt_prop(node, "os-support", &len);
829
+
if (prop)
830
+
f->os_support = be32_to_cpup(prop);
831
+
else
832
+
f->os_support = OS_SUPPORT_NONE;
833
+
834
+
prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
835
+
if (prop)
836
+
f->hfscr_bit_nr = be32_to_cpup(prop);
837
+
else
838
+
f->hfscr_bit_nr = -1;
839
+
prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
840
+
if (prop)
841
+
f->fscr_bit_nr = be32_to_cpup(prop);
842
+
else
843
+
f->fscr_bit_nr = -1;
844
+
prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
845
+
if (prop)
846
+
f->hwcap_bit_nr = be32_to_cpup(prop);
847
+
else
848
+
f->hwcap_bit_nr = -1;
849
+
850
+
if (f->usable_privilege & USABLE_HV) {
851
+
if (!(mfmsr() & MSR_HV)) {
852
+
pr_warn("%s: HV feature passed to guest\n", uname);
853
+
return 0;
854
+
}
855
+
856
+
if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
857
+
pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
858
+
return 0;
859
+
}
860
+
861
+
if (f->hv_support == HV_SUPPORT_HFSCR) {
862
+
if (f->hfscr_bit_nr == -1) {
863
+
pr_warn("%s: missing hfscr_bit_nr\n", uname);
864
+
return 0;
865
+
}
866
+
}
867
+
} else {
868
+
if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
869
+
pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
870
+
return 0;
871
+
}
872
+
}
873
+
874
+
if (f->usable_privilege & USABLE_OS) {
875
+
if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
876
+
pr_warn("%s: unwanted fscr_bit_nr\n", uname);
877
+
return 0;
878
+
}
879
+
880
+
if (f->os_support == OS_SUPPORT_FSCR) {
881
+
if (f->fscr_bit_nr == -1) {
882
+
pr_warn("%s: missing fscr_bit_nr\n", uname);
883
+
return 0;
884
+
}
885
+
}
886
+
} else {
887
+
if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
888
+
pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
889
+
return 0;
890
+
}
891
+
}
892
+
893
+
if (!(f->usable_privilege & USABLE_PR)) {
894
+
if (f->hwcap_bit_nr != -1) {
895
+
pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
896
+
return 0;
897
+
}
898
+
}
899
+
900
+
/* Do all the independent features in the first pass */
901
+
if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
902
+
if (cpufeatures_process_feature(f))
903
+
f->enabled = 1;
904
+
else
905
+
f->disabled = 1;
906
+
}
907
+
908
+
return 0;
909
+
}
910
+
911
+
static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
912
+
{
913
+
const __be32 *prop;
914
+
int len;
915
+
int nr_deps;
916
+
int i;
917
+
918
+
if (f->enabled || f->disabled)
919
+
return;
920
+
921
+
prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
922
+
if (!prop) {
923
+
pr_warn("%s: missing dependencies property", f->name);
924
+
return;
925
+
}
926
+
927
+
nr_deps = len / sizeof(int);
928
+
929
+
for (i = 0; i < nr_deps; i++) {
930
+
unsigned long phandle = be32_to_cpu(prop[i]);
931
+
int j;
932
+
933
+
for (j = 0; j < nr_dt_cpu_features; j++) {
934
+
struct dt_cpu_feature *d = &dt_cpu_features[j];
935
+
936
+
if (of_get_flat_dt_phandle(d->node) == phandle) {
937
+
cpufeatures_deps_enable(d);
938
+
if (d->disabled) {
939
+
f->disabled = 1;
940
+
return;
941
+
}
942
+
}
943
+
}
944
+
}
945
+
946
+
if (cpufeatures_process_feature(f))
947
+
f->enabled = 1;
948
+
else
949
+
f->disabled = 1;
950
+
}
951
+
952
+
static int __init scan_cpufeatures_subnodes(unsigned long node,
953
+
const char *uname,
954
+
void *data)
955
+
{
956
+
int *count = data;
957
+
958
+
process_cpufeatures_node(node, uname, *count);
959
+
960
+
(*count)++;
961
+
962
+
return 0;
963
+
}
964
+
965
+
static int __init count_cpufeatures_subnodes(unsigned long node,
966
+
const char *uname,
967
+
void *data)
968
+
{
969
+
int *count = data;
970
+
971
+
(*count)++;
972
+
973
+
return 0;
974
+
}
975
+
976
+
static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
977
+
*uname, int depth, void *data)
978
+
{
979
+
const __be32 *prop;
980
+
int count, i;
981
+
u32 isa;
982
+
983
+
/* We are scanning "ibm,powerpc-cpu-features" nodes only */
984
+
if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
985
+
return 0;
986
+
987
+
prop = of_get_flat_dt_prop(node, "isa", NULL);
988
+
if (!prop)
989
+
/* We checked before, "can't happen" */
990
+
return 0;
991
+
992
+
isa = be32_to_cpup(prop);
993
+
994
+
/* Count and allocate space for cpu features */
995
+
of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
996
+
&nr_dt_cpu_features);
997
+
dt_cpu_features = __va(
998
+
memblock_alloc(sizeof(struct dt_cpu_feature)*
999
+
nr_dt_cpu_features, PAGE_SIZE));
1000
+
1001
+
cpufeatures_setup_start(isa);
1002
+
1003
+
/* Scan nodes into dt_cpu_features and enable those without deps */
1004
+
count = 0;
1005
+
of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1006
+
1007
+
/* Recursive enable remaining features with dependencies */
1008
+
for (i = 0; i < nr_dt_cpu_features; i++) {
1009
+
struct dt_cpu_feature *f = &dt_cpu_features[i];
1010
+
1011
+
cpufeatures_deps_enable(f);
1012
+
}
1013
+
1014
+
prop = of_get_flat_dt_prop(node, "display-name", NULL);
1015
+
if (prop && strlen((char *)prop) != 0) {
1016
+
strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1017
+
cur_cpu_spec->cpu_name = dt_cpu_name;
1018
+
}
1019
+
1020
+
cpufeatures_setup_finished();
1021
+
1022
+
memblock_free(__pa(dt_cpu_features),
1023
+
sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1024
+
1025
+
return 0;
1026
+
}
1027
+
1028
+
void __init dt_cpu_ftrs_scan(void)
1029
+
{
1030
+
of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1031
+
}
+12
arch/powerpc/kernel/exceptions-64e.S
+12
arch/powerpc/kernel/exceptions-64e.S
···
735
735
andis. r15,r14,(DBSR_IC|DBSR_BT)@h
736
736
beq+ 1f
737
737
738
+
#ifdef CONFIG_RELOCATABLE
739
+
ld r15,PACATOC(r13)
740
+
ld r14,interrupt_base_book3e@got(r15)
741
+
ld r15,__end_interrupts@got(r15)
742
+
#else
738
743
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
739
744
LOAD_REG_IMMEDIATE(r15,__end_interrupts)
745
+
#endif
740
746
cmpld cr0,r10,r14
741
747
cmpld cr1,r10,r15
742
748
blt+ cr0,1f
···
805
799
andis. r15,r14,(DBSR_IC|DBSR_BT)@h
806
800
beq+ 1f
807
801
802
+
#ifdef CONFIG_RELOCATABLE
803
+
ld r15,PACATOC(r13)
804
+
ld r14,interrupt_base_book3e@got(r15)
805
+
ld r15,__end_interrupts@got(r15)
806
+
#else
808
807
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
809
808
LOAD_REG_IMMEDIATE(r15,__end_interrupts)
809
+
#endif
810
810
cmpld cr0,r10,r14
811
811
cmpld cr1,r10,r15
812
812
blt+ cr0,1f
+1
-3
arch/powerpc/kernel/exceptions-64s.S
+1
-3
arch/powerpc/kernel/exceptions-64s.S
+20
-9
arch/powerpc/kernel/prom.c
+20
-9
arch/powerpc/kernel/prom.c
···
57
57
#include <asm/fadump.h>
58
58
#include <asm/epapr_hcalls.h>
59
59
#include <asm/firmware.h>
60
+
#include <asm/dt_cpu_ftrs.h>
60
61
61
62
#include <mm/mmu_decl.h>
62
63
···
376
375
* A POWER6 partition in "POWER6 architected" mode
377
376
* uses the 0x0f000002 PVR value; in POWER5+ mode
378
377
* it uses 0x0f000001.
378
+
*
379
+
* If we're using device tree CPU feature discovery then we don't
380
+
* support the cpu-version property, and it's the responsibility of the
381
+
* firmware/hypervisor to provide the correct feature set for the
382
+
* architecture level via the ibm,powerpc-cpu-features binding.
379
383
*/
380
-
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
381
-
if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
382
-
identify_cpu(0, be32_to_cpup(prop));
384
+
if (!dt_cpu_ftrs_in_use()) {
385
+
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
386
+
if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
387
+
identify_cpu(0, be32_to_cpup(prop));
388
+
389
+
check_cpu_feature_properties(node);
390
+
check_cpu_pa_features(node);
391
+
}
383
392
384
393
identical_pvr_fixup(node);
385
-
386
-
check_cpu_feature_properties(node);
387
-
check_cpu_pa_features(node);
388
394
init_mmu_slb_size(node);
389
395
390
396
#ifdef CONFIG_PPC64
391
-
if (nthreads > 1)
392
-
cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
393
-
else
397
+
if (nthreads == 1)
394
398
cur_cpu_spec->cpu_features &= ~CPU_FTR_SMT;
399
+
else if (!dt_cpu_ftrs_in_use())
400
+
cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
395
401
#endif
402
+
396
403
return 0;
397
404
}
398
405
···
729
720
allocate_pacas();
730
721
731
722
DBG("Scanning CPUs ...\n");
723
+
724
+
dt_cpu_ftrs_scan();
732
725
733
726
/* Retrieve CPU related informations from the flat tree
734
727
* (altivec support, boot CPU ID, ...)
+1
-1
arch/powerpc/kernel/setup-common.c
+1
-1
arch/powerpc/kernel/setup-common.c
···
261
261
seq_printf(m, "processor\t: %lu\n", cpu_id);
262
262
seq_printf(m, "cpu\t\t: ");
263
263
264
-
if (cur_cpu_spec->pvr_mask)
264
+
if (cur_cpu_spec->pvr_mask && cur_cpu_spec->cpu_name)
265
265
seq_printf(m, "%s", cur_cpu_spec->cpu_name);
266
266
else
267
267
seq_printf(m, "unknown (%08x)", pvr);
+8
-2
arch/powerpc/kernel/setup_64.c
+8
-2
arch/powerpc/kernel/setup_64.c
···
49
49
#include <asm/paca.h>
50
50
#include <asm/time.h>
51
51
#include <asm/cputable.h>
52
+
#include <asm/dt_cpu_ftrs.h>
52
53
#include <asm/sections.h>
53
54
#include <asm/btext.h>
54
55
#include <asm/nvram.h>
···
275
274
276
275
/* -------- printk is _NOT_ safe to use here ! ------- */
277
276
278
-
/* Identify CPU type */
279
-
identify_cpu(0, mfspr(SPRN_PVR));
277
+
/* Try new device tree based feature discovery ... */
278
+
if (!dt_cpu_ftrs_init(__va(dt_ptr)))
279
+
/* Otherwise use the old style CPU table */
280
+
identify_cpu(0, mfspr(SPRN_PVR));
280
281
281
282
/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
282
283
initialise_paca(&boot_paca, 0);
···
543
540
/* For use by binfmt_elf */
544
541
dcache_bsize = ppc64_caches.l1d.block_size;
545
542
icache_bsize = ppc64_caches.l1i.block_size;
543
+
544
+
cur_cpu_spec->dcache_bsize = dcache_bsize;
545
+
cur_cpu_spec->icache_bsize = icache_bsize;
546
546
547
547
DBG(" <- initialize_cache_info()\n");
548
548
}
+3
arch/powerpc/platforms/powernv/eeh-powernv.c
+3
arch/powerpc/platforms/powernv/eeh-powernv.c
···
412
412
* been set for the PE, we will set EEH_PE_CFG_BLOCKED for
413
413
* that PE to block its config space.
414
414
*
415
+
* Broadcom BCM5718 2-ports NICs (14e4:1656)
415
416
* Broadcom Austin 4-ports NICs (14e4:1657)
416
417
* Broadcom Shiner 4-ports 1G NICs (14e4:168a)
417
418
* Broadcom Shiner 2-ports 10G NICs (14e4:168e)
418
419
*/
419
420
if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
421
+
pdn->device_id == 0x1656) ||
422
+
(pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
420
423
pdn->device_id == 0x1657) ||
421
424
(pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
422
425
pdn->device_id == 0x168a) ||
+25
arch/powerpc/sysdev/cpm1.c
+25
arch/powerpc/sysdev/cpm1.c
···
377
377
setbits16(&iop->odr_sor, pin);
378
378
else
379
379
clrbits16(&iop->odr_sor, pin);
380
+
if (flags & CPM_PIN_FALLEDGE)
381
+
setbits16(&iop->intr, pin);
382
+
else
383
+
clrbits16(&iop->intr, pin);
380
384
}
381
385
}
382
386
···
532
528
533
529
/* shadowed data register to clear/set bits safely */
534
530
u16 cpdata;
531
+
532
+
/* IRQ associated with Pins when relevant */
533
+
int irq[16];
535
534
};
536
535
537
536
static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
···
585
578
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
586
579
}
587
580
581
+
static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
582
+
{
583
+
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
584
+
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
585
+
586
+
return cpm1_gc->irq[gpio] ? : -ENXIO;
587
+
}
588
+
588
589
static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
589
590
{
590
591
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
···
633
618
struct cpm1_gpio16_chip *cpm1_gc;
634
619
struct of_mm_gpio_chip *mm_gc;
635
620
struct gpio_chip *gc;
621
+
u16 mask;
636
622
637
623
cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
638
624
if (!cpm1_gc)
639
625
return -ENOMEM;
640
626
641
627
spin_lock_init(&cpm1_gc->lock);
628
+
629
+
if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
630
+
int i, j;
631
+
632
+
for (i = 0, j = 0; i < 16; i++)
633
+
if (mask & (1 << (15 - i)))
634
+
cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
635
+
}
642
636
643
637
mm_gc = &cpm1_gc->mm_gc;
644
638
gc = &mm_gc->gc;
···
658
634
gc->direction_output = cpm1_gpio16_dir_out;
659
635
gc->get = cpm1_gpio16_get;
660
636
gc->set = cpm1_gpio16_set;
637
+
gc->to_irq = cpm1_gpio16_to_irq;
661
638
662
639
return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
663
640
}
+3
-5
drivers/net/ethernet/freescale/ucc_geth.c
+3
-5
drivers/net/ethernet/freescale/ucc_geth.c
···
2594
2594
} else if (ugeth->ug_info->uf_info.bd_mem_part ==
2595
2595
MEM_PART_MURAM) {
2596
2596
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2597
-
(u32) immrbar_virt_to_phys(ugeth->
2598
-
p_tx_bd_ring[i]));
2597
+
(u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2599
2598
out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2600
2599
last_bd_completed_address,
2601
-
(u32) immrbar_virt_to_phys(endOfRing));
2600
+
(u32)qe_muram_dma(endOfRing));
2602
2601
}
2603
2602
}
2604
2603
···
2843
2844
} else if (ugeth->ug_info->uf_info.bd_mem_part ==
2844
2845
MEM_PART_MURAM) {
2845
2846
out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2846
-
(u32) immrbar_virt_to_phys(ugeth->
2847
-
p_rx_bd_ring[i]));
2847
+
(u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2848
2848
}
2849
2849
/* rest of fields handled by QE */
2850
2850
}
+38
drivers/of/fdt.c
+38
drivers/of/fdt.c
···
756
756
}
757
757
758
758
/**
759
+
* of_scan_flat_dt_subnodes - scan sub-nodes of a node call callback on each.
760
+
* @it: callback function
761
+
* @data: context data pointer
762
+
*
763
+
* This function is used to scan sub-nodes of a node.
764
+
*/
765
+
int __init of_scan_flat_dt_subnodes(unsigned long parent,
766
+
int (*it)(unsigned long node,
767
+
const char *uname,
768
+
void *data),
769
+
void *data)
770
+
{
771
+
const void *blob = initial_boot_params;
772
+
int node;
773
+
774
+
fdt_for_each_subnode(node, blob, parent) {
775
+
const char *pathp;
776
+
int rc;
777
+
778
+
pathp = fdt_get_name(blob, node, NULL);
779
+
if (*pathp == '/')
780
+
pathp = kbasename(pathp);
781
+
rc = it(node, pathp, data);
782
+
if (rc)
783
+
return rc;
784
+
}
785
+
return 0;
786
+
}
787
+
788
+
/**
759
789
* of_get_flat_dt_subnode_by_name - get the subnode by given name
760
790
*
761
791
* @node: the parent node
···
842
812
int __init of_flat_dt_match(unsigned long node, const char *const *compat)
843
813
{
844
814
return of_fdt_match(initial_boot_params, node, compat);
815
+
}
816
+
817
+
/**
818
+
* of_get_flat_dt_prop - Given a node in the flat blob, return the phandle
819
+
*/
820
+
uint32_t __init of_get_flat_dt_phandle(unsigned long node)
821
+
{
822
+
return fdt_get_phandle(initial_boot_params, node);
845
823
}
846
824
847
825
struct fdt_scan_status {
+5
drivers/soc/fsl/qbman/qman.c
+5
drivers/soc/fsl/qbman/qman.c
···
1344
1344
if (!qm_mc_result_timeout(&p->p, &mcr)) {
1345
1345
spin_unlock(&p->cgr_lock);
1346
1346
dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1347
+
qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1347
1348
return;
1348
1349
}
1349
1350
/* mask out the ones I'm not interested in */
···
1359
1358
if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1360
1359
cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1361
1360
spin_unlock(&p->cgr_lock);
1361
+
qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1362
1362
}
1363
1363
1364
1364
static void qm_mr_process_task(struct work_struct *work)
···
1419
1417
}
1420
1418
1421
1419
qm_mr_cci_consume(&p->p, num);
1420
+
qman_p_irqsource_add(p, QM_PIRQ_MRI);
1422
1421
preempt_enable();
1423
1422
}
1424
1423
1425
1424
static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1426
1425
{
1427
1426
if (is & QM_PIRQ_CSCI) {
1427
+
qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
1428
1428
queue_work_on(smp_processor_id(), qm_portal_wq,
1429
1429
&p->congestion_work);
1430
1430
}
···
1438
1434
}
1439
1435
1440
1436
if (is & QM_PIRQ_MRI) {
1437
+
qman_p_irqsource_remove(p, QM_PIRQ_MRI);
1441
1438
queue_work_on(smp_processor_id(), qm_portal_wq,
1442
1439
&p->mr_work);
1443
1440
}
+20
-5
drivers/soc/fsl/qe/qe.c
+20
-5
drivers/soc/fsl/qe/qe.c
···
66
66
67
67
static phys_addr_t qebase = -1;
68
68
69
-
phys_addr_t get_qe_base(void)
69
+
static phys_addr_t get_qe_base(void)
70
70
{
71
71
struct device_node *qe;
72
72
int ret;
···
89
89
90
90
return qebase;
91
91
}
92
-
93
-
EXPORT_SYMBOL(get_qe_base);
94
92
95
93
void qe_reset(void)
96
94
{
···
161
163
*/
162
164
static unsigned int brg_clk = 0;
163
165
166
+
#define CLK_GRAN (1000)
167
+
#define CLK_GRAN_LIMIT (5)
168
+
164
169
unsigned int qe_get_brg_clk(void)
165
170
{
166
171
struct device_node *qe;
167
172
int size;
168
173
const u32 *prop;
174
+
unsigned int mod;
169
175
170
176
if (brg_clk)
171
177
return brg_clk;
···
187
185
188
186
of_node_put(qe);
189
187
188
+
/* round this if near to a multiple of CLK_GRAN */
189
+
mod = brg_clk % CLK_GRAN;
190
+
if (mod) {
191
+
if (mod < CLK_GRAN_LIMIT)
192
+
brg_clk -= mod;
193
+
else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
194
+
brg_clk += CLK_GRAN - mod;
195
+
}
196
+
190
197
return brg_clk;
191
198
}
192
199
EXPORT_SYMBOL(qe_get_brg_clk);
200
+
201
+
#define PVR_VER_836x 0x8083
202
+
#define PVR_VER_832x 0x8084
193
203
194
204
/* Program the BRG to the given sampling rate and multiplier
195
205
*
···
229
215
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
230
216
that the BRG divisor must be even if you're not using divide-by-16
231
217
mode. */
232
-
if (!div16 && (divisor & 1) && (divisor > 3))
233
-
divisor++;
218
+
if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
219
+
if (!div16 && (divisor & 1) && (divisor > 3))
220
+
divisor++;
234
221
235
222
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
236
223
QE_BRGC_ENABLE | div16;
+2
drivers/soc/fsl/qe/qe_tdm.c
+2
drivers/soc/fsl/qe/qe_tdm.c
+6
include/linux/of_fdt.h
+6
include/linux/of_fdt.h
···
54
54
extern int of_scan_flat_dt(int (*it)(unsigned long node, const char *uname,
55
55
int depth, void *data),
56
56
void *data);
57
+
extern int of_scan_flat_dt_subnodes(unsigned long node,
58
+
int (*it)(unsigned long node,
59
+
const char *uname,
60
+
void *data),
61
+
void *data);
57
62
extern int of_get_flat_dt_subnode_by_name(unsigned long node,
58
63
const char *uname);
59
64
extern const void *of_get_flat_dt_prop(unsigned long node, const char *name,
···
67
62
extern int of_flat_dt_match(unsigned long node, const char *const *matches);
68
63
extern unsigned long of_get_flat_dt_root(void);
69
64
extern int of_get_flat_dt_size(void);
65
+
extern uint32_t of_get_flat_dt_phandle(unsigned long node);
70
66
71
67
extern int early_init_dt_scan_chosen(unsigned long node, const char *uname,
72
68
int depth, void *data);
-19
include/soc/fsl/qe/immap_qe.h
-19
include/soc/fsl/qe/immap_qe.h
···
464
464
} __attribute__ ((packed));
465
465
466
466
extern struct qe_immap __iomem *qe_immr;
467
-
extern phys_addr_t get_qe_base(void);
468
-
469
-
/*
470
-
* Returns the offset within the QE address space of the given pointer.
471
-
*
472
-
* Note that the QE does not support 36-bit physical addresses, so if
473
-
* get_qe_base() returns a number above 4GB, the caller will probably fail.
474
-
*/
475
-
static inline phys_addr_t immrbar_virt_to_phys(void *address)
476
-
{
477
-
void *q = (void *)qe_immr;
478
-
479
-
/* Is it a MURAM address? */
480
-
if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
481
-
return get_qe_base() + (address - q);
482
-
483
-
/* It's an address returned by kmalloc */
484
-
return virt_to_phys(address);
485
-
}
486
467
487
468
#endif /* __KERNEL__ */
488
469
#endif /* _ASM_POWERPC_IMMAP_QE_H */
+1
include/soc/fsl/qe/qe.h
+1
include/soc/fsl/qe/qe.h
···
243
243
#define qe_muram_free cpm_muram_free
244
244
#define qe_muram_addr cpm_muram_addr
245
245
#define qe_muram_offset cpm_muram_offset
246
+
#define qe_muram_dma cpm_muram_dma
246
247
247
248
#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
248
249
#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))