Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
Read PHY_VDR_0_CONFIG to check if there is any change in the register and
decide based on that if P2P sequence to change the data rate of LT PHY
are required or not. This scenario only happens if the requested mode
uses 1.62Gbps with DP mode since LT PHY defaults to this mode if
any other mode is requested we need to follow the whole sequence.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
+123
-25
+1
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+1
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
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int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
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void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
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bool intel_cx0_is_hdmi_frl(u32 clock);
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+
u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
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int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
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void intel_cx0_pll_power_save_wa(struct intel_display *display);
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void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
+121
-23
drivers/gpu/drm/i915/display/intel_lt_phy.c
+121
-23
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
6
6
#include <drm/drm_print.h>
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8
8
#include "i915_reg.h"
9
+
#include "i915_utils.h"
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#include "intel_cx0_phy.h"
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#include "intel_cx0_phy_regs.h"
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#include "intel_de.h"
···
15
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#include "intel_hdmi.h"
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#include "intel_lt_phy.h"
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#include "intel_lt_phy_regs.h"
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+
#include "intel_psr.h"
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#include "intel_tc.h"
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#define INTEL_LT_PHY_LANE0 BIT(0)
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#define INTEL_LT_PHY_LANE1 BIT(1)
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#define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
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INTEL_LT_PHY_LANE0)
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#define MODE_DP 3
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static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
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{
···
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return intel_tc_port_max_lane_count(dig_port) > 2
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? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0;
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}
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+
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static u8 intel_lt_phy_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr)
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{
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return intel_cx0_read(encoder, lane_mask, addr);
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}
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static void
···
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XELPDP_SSC_ENABLE_PLLB, val);
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}
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+
static u32 intel_lt_phy_get_dp_clock(u8 rate)
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{
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switch (rate) {
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case 0:
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return 162000;
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case 1:
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return 270000;
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case 2:
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return 540000;
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case 3:
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return 810000;
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case 4:
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return 216000;
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case 5:
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return 243000;
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+
case 6:
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return 324000;
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case 7:
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return 432000;
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case 8:
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return 1000000;
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case 9:
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return 1350000;
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case 10:
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return 2000000;
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case 11:
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return 675000;
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default:
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MISSING_CASE(rate);
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return 0;
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}
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}
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+
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static bool
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intel_lt_phy_config_changed(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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u8 val, rate;
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u32 clock;
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+
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val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
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LT_PHY_VDR_0_CONFIG);
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rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, val);
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+
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/*
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* The only time we do not reconfigure the PLL is when we are
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* using 1.62 Gbps clock since PHY PLL defaults to that
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* otherwise we always need to reconfigure it.
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*/
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if (intel_crtc_has_dp_encoder(crtc_state)) {
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clock = intel_lt_phy_get_dp_clock(rate);
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if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock)
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return false;
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}
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+
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return true;
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}
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+
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static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *encoder)
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+
{
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struct intel_display *display = to_intel_display(encoder);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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intel_wakeref_t wakeref;
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+
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intel_psr_pause(intel_dp);
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wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
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+
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return wakeref;
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}
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+
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static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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+
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intel_psr_resume(intel_dp);
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intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
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}
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void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct intel_display *display = to_intel_display(encoder);
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struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
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bool lane_reversal = dig_port->lane_reversal;
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u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
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intel_wakeref_t wakeref = 0;
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wakeref = intel_lt_phy_transaction_begin(encoder);
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/* 1. Enable MacCLK at default 162 MHz frequency. */
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intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
···
261
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* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type,
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* encoded rate and encoded mode.
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*/
264
-
/*
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* 5. Program the PHY internal PLL registers over PHY message bus for the desired
266
-
* frequency and protocol type
267
-
*/
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-
/* 6. Use the P2P transaction flow */
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-
/*
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* 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
271
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* bus for Owned PHY Lanes.
272
-
*/
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/*
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* 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR register
275
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* at offset 0xC00 for Owned PHY Lanes.
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-
*/
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/* 6.3. Clear P2P transaction Ready bit. */
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/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
279
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/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
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/*
281
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* 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency Change.
282
-
* We handle this step in bxt_set_cdclk()
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-
*/
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/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
285
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/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
286
-
/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
173
+
if (intel_lt_phy_config_changed(encoder, crtc_state)) {
174
+
/*
175
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* 5. Program the PHY internal PLL registers over PHY message bus for the desired
176
+
* frequency and protocol type
177
+
*/
178
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/* 6. Use the P2P transaction flow */
179
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/*
180
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* 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message
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* bus for Owned PHY Lanes.
182
+
*/
183
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/*
184
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* 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR
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* register at offset 0xC00 for Owned PHY Lanes*.
186
+
*/
187
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/* 6.3. Clear P2P transaction Ready bit. */
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/* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */
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/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
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/*
191
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* 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
192
+
* Change. We handle this step in bxt_set_cdclk().
193
+
*/
194
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/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
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/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
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/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
197
+
} else {
198
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intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);
199
+
}
200
+
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/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */
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/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
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/*
···
302
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* We handle this step in bxt_set_cdclk()
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207
*/
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/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
209
+
210
+
intel_lt_phy_transaction_end(encoder, wakeref);
305
211
}