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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'thead-dt-for-v6.13-p2' of https://github.com/pdp7/linux into soc/dt
T-HEAD Devicetrees for v6.13, part 2
Add gmac, mdio, and phy nodes to enable the gigabit Ethernet ports on
the TH1520 SoC-based BeagleV Ahead and Sipeed Lichee Pi 4a boards.
The dwmac-thead driver and dt binding have been accepted by netdev and
are in linux-next as well as the dts patch in this pull request. I have
tested next-20241108 on the Ahead and LPi4a boards, and Ethernet works
correctly.
Signed-off-by: Drew Fustini <drew@pdp7.com>
* tag 'thead-dt-for-v6.13-p2' of https://github.com/pdp7/linux:
riscv: dts: thead: Add TH1520 ethernet nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+260
+91
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+91
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
···
15
15
compatible = "beagle,beaglev-ahead", "thead,th1520";
16
16
17
17
aliases {
18
+
ethernet0 = &gmac0;
18
19
gpio0 = &gpio0;
19
20
gpio1 = &gpio1;
20
21
gpio2 = &gpio2;
···
99
98
status = "okay";
100
99
};
101
100
101
+
&gmac0 {
102
+
pinctrl-names = "default";
103
+
pinctrl-0 = <&gmac0_pins>;
104
+
phy-handle = <&phy0>;
105
+
phy-mode = "rgmii-id";
106
+
status = "okay";
107
+
};
108
+
109
+
&mdio0 {
110
+
phy0: ethernet-phy@1 {
111
+
reg = <1>;
112
+
interrupt-parent = <&gpio3>;
113
+
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
114
+
reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
115
+
reset-delay-us = <10000>;
116
+
reset-post-delay-us = <50000>;
117
+
};
118
+
};
119
+
102
120
&padctrl_aosys {
103
121
led_pins: led-0 {
104
122
led-pins {
···
136
116
};
137
117
138
118
&padctrl0_apsys {
119
+
gmac0_pins: gmac0-0 {
120
+
tx-pins {
121
+
pins = "GMAC0_TX_CLK",
122
+
"GMAC0_TXEN",
123
+
"GMAC0_TXD0",
124
+
"GMAC0_TXD1",
125
+
"GMAC0_TXD2",
126
+
"GMAC0_TXD3";
127
+
function = "gmac0";
128
+
bias-disable;
129
+
drive-strength = <25>;
130
+
input-disable;
131
+
input-schmitt-disable;
132
+
slew-rate = <0>;
133
+
};
134
+
135
+
rx-pins {
136
+
pins = "GMAC0_RX_CLK",
137
+
"GMAC0_RXDV",
138
+
"GMAC0_RXD0",
139
+
"GMAC0_RXD1",
140
+
"GMAC0_RXD2",
141
+
"GMAC0_RXD3";
142
+
function = "gmac0";
143
+
bias-disable;
144
+
drive-strength = <1>;
145
+
input-enable;
146
+
input-schmitt-disable;
147
+
slew-rate = <0>;
148
+
};
149
+
150
+
mdc-pins {
151
+
pins = "GMAC0_MDC";
152
+
function = "gmac0";
153
+
bias-disable;
154
+
drive-strength = <13>;
155
+
input-disable;
156
+
input-schmitt-disable;
157
+
slew-rate = <0>;
158
+
};
159
+
160
+
mdio-pins {
161
+
pins = "GMAC0_MDIO";
162
+
function = "gmac0";
163
+
bias-disable;
164
+
drive-strength = <13>;
165
+
input-enable;
166
+
input-schmitt-enable;
167
+
slew-rate = <0>;
168
+
};
169
+
170
+
phy-reset-pins {
171
+
pins = "GMAC0_COL"; /* GPIO3_21 */
172
+
bias-disable;
173
+
drive-strength = <3>;
174
+
input-disable;
175
+
input-schmitt-disable;
176
+
slew-rate = <0>;
177
+
};
178
+
179
+
phy-interrupt-pins {
180
+
pins = "GMAC0_CRS"; /* GPIO3_22 */
181
+
function = "gpio";
182
+
bias-pull-up;
183
+
drive-strength = <1>;
184
+
input-enable;
185
+
input-schmitt-enable;
186
+
slew-rate = <0>;
187
+
};
188
+
};
189
+
139
190
uart0_pins: uart0-0 {
140
191
tx-pins {
141
192
pins = "UART0_TXD";
+119
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+119
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
···
11
11
model = "Sipeed Lichee Module 4A";
12
12
compatible = "sipeed,lichee-module-4a", "thead,th1520";
13
13
14
+
aliases {
15
+
ethernet0 = &gmac0;
16
+
ethernet1 = &gmac1;
17
+
};
18
+
14
19
memory@0 {
15
20
device_type = "memory";
16
21
reg = <0x0 0x00000000 0x2 0x00000000>;
···
50
45
status = "okay";
51
46
};
52
47
48
+
&gmac0 {
49
+
pinctrl-names = "default";
50
+
pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
51
+
phy-handle = <&phy0>;
52
+
phy-mode = "rgmii-id";
53
+
status = "okay";
54
+
};
55
+
56
+
&gmac1 {
57
+
pinctrl-names = "default";
58
+
pinctrl-0 = <&gmac1_pins>;
59
+
phy-handle = <&phy1>;
60
+
phy-mode = "rgmii-id";
61
+
status = "okay";
62
+
};
63
+
53
64
&gpio0 {
54
65
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
55
66
"", "", "", "", "", "", "", "", "", "",
···
97
76
gpio-line-names = "", "",
98
77
"GPIO09",
99
78
"GPIO10";
79
+
};
80
+
81
+
&mdio0 {
82
+
phy0: ethernet-phy@1 {
83
+
reg = <1>;
84
+
};
85
+
86
+
phy1: ethernet-phy@2 {
87
+
reg = <2>;
88
+
};
89
+
};
90
+
91
+
&padctrl0_apsys {
92
+
gmac0_pins: gmac0-0 {
93
+
tx-pins {
94
+
pins = "GMAC0_TX_CLK",
95
+
"GMAC0_TXEN",
96
+
"GMAC0_TXD0",
97
+
"GMAC0_TXD1",
98
+
"GMAC0_TXD2",
99
+
"GMAC0_TXD3";
100
+
function = "gmac0";
101
+
bias-disable;
102
+
drive-strength = <25>;
103
+
input-disable;
104
+
input-schmitt-disable;
105
+
slew-rate = <0>;
106
+
};
107
+
108
+
rx-pins {
109
+
pins = "GMAC0_RX_CLK",
110
+
"GMAC0_RXDV",
111
+
"GMAC0_RXD0",
112
+
"GMAC0_RXD1",
113
+
"GMAC0_RXD2",
114
+
"GMAC0_RXD3";
115
+
function = "gmac0";
116
+
bias-disable;
117
+
drive-strength = <1>;
118
+
input-enable;
119
+
input-schmitt-disable;
120
+
slew-rate = <0>;
121
+
};
122
+
};
123
+
124
+
gmac1_pins: gmac1-0 {
125
+
tx-pins {
126
+
pins = "GPIO2_18", /* GMAC1_TX_CLK */
127
+
"GPIO2_20", /* GMAC1_TXEN */
128
+
"GPIO2_21", /* GMAC1_TXD0 */
129
+
"GPIO2_22", /* GMAC1_TXD1 */
130
+
"GPIO2_23", /* GMAC1_TXD2 */
131
+
"GPIO2_24"; /* GMAC1_TXD3 */
132
+
function = "gmac1";
133
+
bias-disable;
134
+
drive-strength = <25>;
135
+
input-disable;
136
+
input-schmitt-disable;
137
+
slew-rate = <0>;
138
+
};
139
+
140
+
rx-pins {
141
+
pins = "GPIO2_19", /* GMAC1_RX_CLK */
142
+
"GPIO2_25", /* GMAC1_RXDV */
143
+
"GPIO2_30", /* GMAC1_RXD0 */
144
+
"GPIO2_31", /* GMAC1_RXD1 */
145
+
"GPIO3_0", /* GMAC1_RXD2 */
146
+
"GPIO3_1"; /* GMAC1_RXD3 */
147
+
function = "gmac1";
148
+
bias-disable;
149
+
drive-strength = <1>;
150
+
input-enable;
151
+
input-schmitt-disable;
152
+
slew-rate = <0>;
153
+
};
154
+
};
155
+
156
+
mdio0_pins: mdio0-0 {
157
+
mdc-pins {
158
+
pins = "GMAC0_MDC";
159
+
function = "gmac0";
160
+
bias-disable;
161
+
drive-strength = <13>;
162
+
input-disable;
163
+
input-schmitt-disable;
164
+
slew-rate = <0>;
165
+
};
166
+
167
+
mdio-pins {
168
+
pins = "GMAC0_MDIO";
169
+
function = "gmac0";
170
+
bias-disable;
171
+
drive-strength = <13>;
172
+
input-enable;
173
+
input-schmitt-enable;
174
+
slew-rate = <0>;
175
+
};
176
+
};
100
177
};
101
178
102
179
&sdio0 {
+50
arch/riscv/boot/dts/thead/th1520.dtsi
+50
arch/riscv/boot/dts/thead/th1520.dtsi
···
223
223
#clock-cells = <0>;
224
224
};
225
225
226
+
stmmac_axi_config: stmmac-axi-config {
227
+
snps,wr_osr_lmt = <15>;
228
+
snps,rd_osr_lmt = <15>;
229
+
snps,blen = <0 0 64 32 0 0 0>;
230
+
};
231
+
226
232
soc {
227
233
compatible = "simple-bus";
228
234
interrupt-parent = <&plic>;
···
278
272
reg-shift = <2>;
279
273
reg-io-width = <4>;
280
274
status = "disabled";
275
+
};
276
+
277
+
gmac1: ethernet@ffe7060000 {
278
+
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
279
+
reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
280
+
reg-names = "dwmac", "apb";
281
+
interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
282
+
interrupt-names = "macirq";
283
+
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
284
+
clock-names = "stmmaceth", "pclk";
285
+
snps,pbl = <32>;
286
+
snps,fixed-burst;
287
+
snps,multicast-filter-bins = <64>;
288
+
snps,perfect-filter-entries = <32>;
289
+
snps,axi-config = <&stmmac_axi_config>;
290
+
status = "disabled";
291
+
292
+
mdio1: mdio {
293
+
compatible = "snps,dwmac-mdio";
294
+
#address-cells = <1>;
295
+
#size-cells = <0>;
296
+
};
297
+
};
298
+
299
+
gmac0: ethernet@ffe7070000 {
300
+
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
301
+
reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
302
+
reg-names = "dwmac", "apb";
303
+
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
304
+
interrupt-names = "macirq";
305
+
clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
306
+
clock-names = "stmmaceth", "pclk";
307
+
snps,pbl = <32>;
308
+
snps,fixed-burst;
309
+
snps,multicast-filter-bins = <64>;
310
+
snps,perfect-filter-entries = <32>;
311
+
snps,axi-config = <&stmmac_axi_config>;
312
+
status = "disabled";
313
+
314
+
mdio0: mdio {
315
+
compatible = "snps,dwmac-mdio";
316
+
#address-cells = <1>;
317
+
#size-cells = <0>;
318
+
};
281
319
};
282
320
283
321
emmc: mmc@ffe7080000 {