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pinctrl: realtek: add support for slew rate, input voltage and high VIL

Add support for configuring slew rate, input voltage level and high VIL
mode. This involves updating the pin configuration parsing logic to handle
PIN_CONFIG_SLEW_RATE, PIN_CONFIG_INPUT_VOLTAGE_UV and the new custom
property "realtek,high-vil-microvolt".

Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Tzuyi Chang <tychang@realtek.com>
Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Tzuyi Chang and committed by
Linus Walleij dcc93344 f6ea7004

+68 -1
+65 -1
drivers/pinctrl/realtek/pinctrl-rtd.c
··· 37 37 #define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1) 38 38 #define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2) 39 39 #define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3) 40 + #define RTD_HIGH_VIL (PIN_CONFIG_END + 4) 40 41 41 42 static const struct pinconf_generic_params rtd_custom_bindings[] = { 42 43 {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, 43 44 {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, 44 45 {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, 46 + {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0}, 45 47 }; 46 48 47 49 static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) ··· 290 288 u16 strength; 291 289 u32 val; 292 290 u32 mask; 293 - u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; 291 + u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off, 292 + input_volt_off, sr_off, hvil_off; 294 293 const char *name = data->info->pins[pinnr].name; 295 294 int ret = 0; 296 295 ··· 410 407 set_val = arg; 411 408 mask = BIT(pow_off); 412 409 val = set_val ? mask : 0; 410 + break; 411 + 412 + case PIN_CONFIG_SLEW_RATE: 413 + if (config_desc->slew_rate_offset == NA) { 414 + dev_err(data->dev, "Slew rate setting unsupported for pin: %s\n", name); 415 + return -ENOTSUPP; 416 + } 417 + 418 + switch (arg) { 419 + case 1: 420 + set_val = 0; 421 + break; 422 + case 10: 423 + set_val = 1; 424 + break; 425 + case 20: 426 + set_val = 2; 427 + break; 428 + case 30: 429 + set_val = 3; 430 + break; 431 + default: 432 + return -EINVAL; 433 + } 434 + 435 + sr_off = config_desc->base_bit + config_desc->slew_rate_offset; 436 + reg_off = config_desc->reg_offset; 437 + mask = 0x3 << sr_off; 438 + val = arg << sr_off; 439 + break; 440 + 441 + case PIN_CONFIG_INPUT_VOLTAGE_UV: 442 + if (config_desc->input_volt_offset == NA) { 443 + dev_err(data->dev, "Input voltage level setting unsupported for pin:%s\n", 444 + name); 445 + return -ENOTSUPP; 446 + } 447 + 448 + if (arg == 3300000) 449 + set_val = 1; 450 + else if (arg == 1800000) 451 + set_val = 0; 452 + else 453 + return -EINVAL; 454 + 455 + input_volt_off = config_desc->base_bit + config_desc->input_volt_offset; 456 + reg_off = config_desc->reg_offset; 457 + 458 + mask = BIT(input_volt_off); 459 + val = set_val ? BIT(input_volt_off) : 0; 460 + break; 461 + 462 + case RTD_HIGH_VIL: 463 + if (config_desc->hvil_offset == NA) { 464 + dev_err(data->dev, "High vil setting unsupported for pin:%s\n", name); 465 + return -ENOTSUPP; 466 + } 467 + hvil_off = config_desc->base_bit + config_desc->hvil_offset; 468 + reg_off = config_desc->reg_offset; 469 + mask = BIT(hvil_off); 470 + val = 1; 413 471 break; 414 472 415 473 case RTD_DRIVE_STRENGH_P:
+3
drivers/pinctrl/realtek/pinctrl-rtd.h
··· 34 34 unsigned int smt_offset; 35 35 unsigned int power_offset; 36 36 unsigned int curr_type; 37 + unsigned int input_volt_offset; 38 + unsigned int slew_rate_offset; 39 + unsigned int hvil_offset; 37 40 }; 38 41 39 42 struct rtd_pin_sconfig_desc {