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Merge tag 'mmc-v4.20-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson:
"MMC host:

- sdhci-pci: Fixup card detect lookup

- sdhci-pci: Workaround GLK firmware bug for tuning"

* tag 'mmc-v4.20-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-pci: Workaround GLK firmware failing to restore the tuning value
mmc: sdhci-pci: Try "cd" for card-detect lookup before using NULL

+83 -3
+83 -3
drivers/mmc/host/sdhci-pci-core.c
··· 12 12 * - JMicron (hardware and technical support) 13 13 */ 14 14 15 + #include <linux/bitfield.h> 15 16 #include <linux/string.h> 16 17 #include <linux/delay.h> 17 18 #include <linux/highmem.h> ··· 463 462 u32 dsm_fns; 464 463 int drv_strength; 465 464 bool d3_retune; 465 + bool rpm_retune_ok; 466 + u32 glk_rx_ctrl1; 467 + u32 glk_tun_val; 466 468 }; 467 469 468 470 static const guid_t intel_dsm_guid = ··· 795 791 return ret; 796 792 } 797 793 794 + #ifdef CONFIG_PM 795 + #define GLK_RX_CTRL1 0x834 796 + #define GLK_TUN_VAL 0x840 797 + #define GLK_PATH_PLL GENMASK(13, 8) 798 + #define GLK_DLY GENMASK(6, 0) 799 + /* Workaround firmware failing to restore the tuning value */ 800 + static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 801 + { 802 + struct sdhci_pci_slot *slot = chip->slots[0]; 803 + struct intel_host *intel_host = sdhci_pci_priv(slot); 804 + struct sdhci_host *host = slot->host; 805 + u32 glk_rx_ctrl1; 806 + u32 glk_tun_val; 807 + u32 dly; 808 + 809 + if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 810 + return; 811 + 812 + glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 813 + glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 814 + 815 + if (susp) { 816 + intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 817 + intel_host->glk_tun_val = glk_tun_val; 818 + return; 819 + } 820 + 821 + if (!intel_host->glk_tun_val) 822 + return; 823 + 824 + if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 825 + intel_host->rpm_retune_ok = true; 826 + return; 827 + } 828 + 829 + dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 830 + (intel_host->glk_tun_val << 1)); 831 + if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 832 + return; 833 + 834 + glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 835 + sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 836 + 837 + intel_host->rpm_retune_ok = true; 838 + chip->rpm_retune = true; 839 + mmc_retune_needed(host->mmc); 840 + pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 841 + } 842 + 843 + static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 844 + { 845 + if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 846 + !chip->rpm_retune) 847 + glk_rpm_retune_wa(chip, susp); 848 + } 849 + 850 + static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 851 + { 852 + glk_rpm_retune_chk(chip, true); 853 + 854 + return sdhci_cqhci_runtime_suspend(chip); 855 + } 856 + 857 + static int glk_runtime_resume(struct sdhci_pci_chip *chip) 858 + { 859 + glk_rpm_retune_chk(chip, false); 860 + 861 + return sdhci_cqhci_runtime_resume(chip); 862 + } 863 + #endif 864 + 798 865 #ifdef CONFIG_ACPI 799 866 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 800 867 { ··· 954 879 .resume = sdhci_cqhci_resume, 955 880 #endif 956 881 #ifdef CONFIG_PM 957 - .runtime_suspend = sdhci_cqhci_runtime_suspend, 958 - .runtime_resume = sdhci_cqhci_runtime_resume, 882 + .runtime_suspend = glk_runtime_suspend, 883 + .runtime_resume = glk_runtime_resume, 959 884 #endif 960 885 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 961 886 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | ··· 1837 1762 device_init_wakeup(&pdev->dev, true); 1838 1763 1839 1764 if (slot->cd_idx >= 0) { 1840 - ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, 1765 + ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1841 1766 slot->cd_override_level, 0, NULL); 1767 + if (ret && ret != -EPROBE_DEFER) 1768 + ret = mmc_gpiod_request_cd(host->mmc, NULL, 1769 + slot->cd_idx, 1770 + slot->cd_override_level, 1771 + 0, NULL); 1842 1772 if (ret == -EPROBE_DEFER) 1843 1773 goto remove; 1844 1774