tjh.dev / kernel
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drm/amdgpu: Add xcc specific functions for gfxhub

GFXHUB 1.2 supports multiple XCC instances. Add XCC specific functions
to handle XCC instances separately.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher dd1a02e2 44b5cf2e

+127 -77
+4
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1263 1263 1264 1264 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1265 1265 1266 + #define for_each_inst(i, inst_mask) \ 1267 + for (i = ffs(inst_mask) - 1; inst_mask; \ 1268 + inst_mask &= ~(1U << i), i = ffs(inst_mask) - 1) 1269 + 1266 1270 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1267 1271 1268 1272 /* Common functions */
+123 -77
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
··· 38 38 return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24; 39 39 } 40 40 41 - static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev, 42 - uint32_t vmid, 43 - uint64_t page_table_base) 41 + static void gfxhub_v1_2_xcc_setup_vm_pt_regs(struct amdgpu_device *adev, 42 + uint32_t vmid, 43 + uint64_t page_table_base, 44 + uint32_t xcc_mask) 44 45 { 45 46 struct amdgpu_vmhub *hub; 46 - int i, num_xcc; 47 + int i; 47 48 48 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 49 - for (i = 0; i < num_xcc; i++) { 49 + for_each_inst(i, xcc_mask) { 50 50 hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; 51 51 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), 52 52 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, ··· 57 57 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 58 58 hub->ctx_addr_distance * vmid, 59 59 upper_32_bits(page_table_base)); 60 - 61 60 } 62 61 } 63 62 64 - static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev) 63 + static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev, 64 + uint32_t vmid, 65 + uint64_t page_table_base) 66 + { 67 + uint32_t xcc_mask; 68 + 69 + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 70 + gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); 71 + } 72 + 73 + static void gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev, 74 + uint32_t xcc_mask) 65 75 { 66 76 uint64_t pt_base; 67 - int i, num_xcc; 77 + int i; 68 78 69 79 if (adev->gmc.pdb0_bo) 70 80 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 71 81 else 72 82 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 73 83 74 - gfxhub_v1_2_setup_vm_pt_regs(adev, 0, pt_base); 84 + gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); 75 85 76 86 /* If use GART for FB translation, vmid0 page table covers both 77 87 * vram and system memory (gart) 78 88 */ 79 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 80 - for (i = 0; i < num_xcc; i++) { 89 + for_each_inst(i, xcc_mask) { 81 90 if (adev->gmc.pdb0_bo) { 82 91 WREG32_SOC15(GC, GET_INST(GC, i), 83 92 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, ··· 119 110 } 120 111 } 121 112 122 - static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev) 113 + static void 114 + gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev, 115 + uint32_t xcc_mask) 123 116 { 124 117 uint64_t value; 125 118 uint32_t tmp; 126 - int i, num_xcc; 119 + int i; 127 120 128 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 129 - for (i = 0; i < num_xcc; i++) { 121 + for_each_inst(i, xcc_mask) { 130 122 /* Program the AGP BAR */ 131 123 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0); 132 124 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); ··· 188 178 } 189 179 } 190 180 191 - static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev) 181 + static void gfxhub_v1_2_xcc_init_tlb_regs(struct amdgpu_device *adev, 182 + uint32_t xcc_mask) 192 183 { 193 184 uint32_t tmp; 194 - int i, num_xcc; 185 + int i; 195 186 196 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 197 - for (i = 0; i < num_xcc; i++) { 187 + for_each_inst(i, xcc_mask) { 198 188 /* Setup TLB control */ 199 189 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL); 200 190 ··· 214 204 } 215 205 } 216 206 217 - static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 207 + static void gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev, 208 + uint32_t xcc_mask) 218 209 { 219 210 uint32_t tmp; 220 - int i, num_xcc; 211 + int i; 221 212 222 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 223 - for (i = 0; i < num_xcc; i++) { 213 + for_each_inst(i, xcc_mask) { 224 214 /* Setup L2 cache */ 225 215 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL); 226 216 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); ··· 262 252 } 263 253 } 264 254 265 - static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev) 255 + static void gfxhub_v1_2_xcc_enable_system_domain(struct amdgpu_device *adev, 256 + uint32_t xcc_mask) 266 257 { 267 258 uint32_t tmp; 268 - int i, num_xcc; 259 + int i; 269 260 270 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 271 - for (i = 0; i < num_xcc; i++) { 261 + for_each_inst(i, xcc_mask) { 272 262 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL); 273 263 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 274 264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, ··· 281 271 } 282 272 } 283 273 284 - static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev) 274 + static void 275 + gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev, 276 + uint32_t xcc_mask) 285 277 { 286 - int i, num_xcc; 278 + int i; 287 279 288 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 289 - for (i = 0; i < num_xcc; i++) { 280 + for_each_inst(i, xcc_mask) { 290 281 WREG32_SOC15(GC, GET_INST(GC, i), 291 282 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 292 283 0XFFFFFFFF); ··· 309 298 } 310 299 } 311 300 312 - static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) 301 + static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev, 302 + uint32_t xcc_mask) 313 303 { 314 304 struct amdgpu_vmhub *hub; 315 305 unsigned num_level, block_size; 316 306 uint32_t tmp; 317 - int i, j, num_xcc; 307 + int i, j; 318 308 319 309 num_level = adev->vm_manager.num_level; 320 310 block_size = adev->vm_manager.block_size; ··· 324 312 else 325 313 block_size -= 9; 326 314 327 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 328 - for (j = 0; j < num_xcc; j++) { 315 + for_each_inst(j, xcc_mask) { 329 316 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 330 317 for (i = 0; i <= 14; i++) { 331 318 tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i); ··· 379 368 } 380 369 } 381 370 382 - static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev) 371 + static void gfxhub_v1_2_xcc_program_invalidation(struct amdgpu_device *adev, 372 + uint32_t xcc_mask) 383 373 { 384 374 struct amdgpu_vmhub *hub; 385 - unsigned i, j, num_xcc; 375 + unsigned int i, j; 386 376 387 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 388 - for (j = 0; j < num_xcc; j++) { 377 + for_each_inst(j, xcc_mask) { 389 378 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 390 379 391 380 for (i = 0 ; i < 18; ++i) { ··· 397 386 } 398 387 } 399 388 400 - static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev) 389 + static int gfxhub_v1_2_xcc_gart_enable(struct amdgpu_device *adev, 390 + uint32_t xcc_mask) 401 391 { 402 - int i, num_xcc; 392 + uint32_t tmp_mask; 393 + int i; 403 394 404 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 405 - for (i = 0; i < num_xcc; i++) { 406 - if (amdgpu_sriov_vf(adev)) { 407 - /* 408 - * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 409 - * VF copy registers so vbios post doesn't program them, for 410 - * SRIOV driver need to program them 411 - */ 395 + tmp_mask = xcc_mask; 396 + /* 397 + * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, because they are 398 + * VF copy registers so vbios post doesn't program them, for 399 + * SRIOV driver need to program them 400 + */ 401 + if (amdgpu_sriov_vf(adev)) { 402 + for_each_inst(i, tmp_mask) { 403 + i = ffs(tmp_mask) - 1; 412 404 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 413 405 adev->gmc.vram_start >> 24); 414 406 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, ··· 420 406 } 421 407 422 408 /* GART Enable. */ 423 - gfxhub_v1_2_init_gart_aperture_regs(adev); 424 - gfxhub_v1_2_init_system_aperture_regs(adev); 425 - gfxhub_v1_2_init_tlb_regs(adev); 409 + gfxhub_v1_2_xcc_init_gart_aperture_regs(adev, xcc_mask); 410 + gfxhub_v1_2_xcc_init_system_aperture_regs(adev, xcc_mask); 411 + gfxhub_v1_2_xcc_init_tlb_regs(adev, xcc_mask); 426 412 if (!amdgpu_sriov_vf(adev)) 427 - gfxhub_v1_2_init_cache_regs(adev); 413 + gfxhub_v1_2_xcc_init_cache_regs(adev, xcc_mask); 428 414 429 - gfxhub_v1_2_enable_system_domain(adev); 415 + gfxhub_v1_2_xcc_enable_system_domain(adev, xcc_mask); 430 416 if (!amdgpu_sriov_vf(adev)) 431 - gfxhub_v1_2_disable_identity_aperture(adev); 432 - gfxhub_v1_2_setup_vmid_config(adev); 433 - gfxhub_v1_2_program_invalidation(adev); 417 + gfxhub_v1_2_xcc_disable_identity_aperture(adev, xcc_mask); 418 + gfxhub_v1_2_xcc_setup_vmid_config(adev, xcc_mask); 419 + gfxhub_v1_2_xcc_program_invalidation(adev, xcc_mask); 434 420 435 421 return 0; 436 422 } 437 423 438 - static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) 424 + static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev) 425 + { 426 + uint32_t xcc_mask; 427 + 428 + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 429 + return gfxhub_v1_2_xcc_gart_enable(adev, xcc_mask); 430 + } 431 + 432 + static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev, 433 + uint32_t xcc_mask) 439 434 { 440 435 struct amdgpu_vmhub *hub; 441 436 u32 tmp; 442 - u32 i, j, num_xcc; 437 + u32 i, j; 443 438 444 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 445 - for (j = 0; j < num_xcc; j++) { 439 + for_each_inst(j, xcc_mask) { 446 440 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 447 441 /* Disable all tables */ 448 442 for (i = 0; i < 16; i++) ··· 474 452 } 475 453 } 476 454 477 - /** 478 - * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling 479 - * 480 - * @adev: amdgpu_device pointer 481 - * @value: true redirects VM faults to the default page 482 - */ 483 - static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, 484 - bool value) 455 + static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) 456 + { 457 + uint32_t xcc_mask; 458 + 459 + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 460 + gfxhub_v1_2_xcc_gart_disable(adev, xcc_mask); 461 + } 462 + 463 + static void gfxhub_v1_2_xcc_set_fault_enable_default(struct amdgpu_device *adev, 464 + bool value, 465 + uint32_t xcc_mask) 485 466 { 486 467 u32 tmp; 487 - int i, num_xcc; 468 + int i; 488 469 489 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 490 - for (i = 0; i < num_xcc; i++) { 470 + for_each_inst(i, xcc_mask) { 491 471 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); 492 472 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 493 473 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); ··· 525 501 } 526 502 } 527 503 528 - static void gfxhub_v1_2_init(struct amdgpu_device *adev) 504 + /** 505 + * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling 506 + * 507 + * @adev: amdgpu_device pointer 508 + * @value: true redirects VM faults to the default page 509 + */ 510 + static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, 511 + bool value) 512 + { 513 + uint32_t xcc_mask; 514 + 515 + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 516 + gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, xcc_mask); 517 + } 518 + 519 + static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) 529 520 { 530 521 struct amdgpu_vmhub *hub; 531 - int i, num_xcc; 522 + int i; 532 523 533 - num_xcc = NUM_XCC(adev->gfx.xcc_mask); 534 - for (i = 0; i < num_xcc; i++) { 524 + for_each_inst(i, xcc_mask) { 535 525 hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; 536 526 537 527 hub->ctx0_ptb_addr_lo32 = ··· 579 541 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 580 542 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 581 543 } 544 + } 545 + 546 + static void gfxhub_v1_2_init(struct amdgpu_device *adev) 547 + { 548 + uint32_t xcc_mask; 549 + 550 + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 551 + gfxhub_v1_2_xcc_init(adev, xcc_mask); 582 552 } 583 553 584 554 static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev)