Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/i915/dp_mst: Update the total link slot count early

A follow up change will check a selected bpp's BW requirement in
intel_dp_mtp_tu_compute_config(), however that requires the total link
slot count to be up-to-date. The latter in turn depends on the channel
encoding and hence the link rate used, so it can be set after the
link rate used is selected.

This also allows simplifying mst_stream_update_slots(), do that as well,
moving the function definition before its use.

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250509180340.554867-5-imre.deak@intel.com

+11 -25
+11 -25
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 241 241 num_joined_pipes); 242 242 } 243 243 244 + static void mst_stream_update_slots(const struct intel_crtc_state *crtc_state, 245 + struct drm_dp_mst_topology_state *topology_state) 246 + { 247 + u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? 248 + DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; 249 + 250 + drm_dp_mst_update_slots(topology_state, link_coding_cap); 251 + } 252 + 244 253 int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, 245 254 struct intel_crtc_state *crtc_state, 246 255 struct drm_connector_state *conn_state, ··· 285 276 286 277 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, 287 278 crtc_state->lane_count); 279 + 280 + mst_stream_update_slots(crtc_state, mst_state); 288 281 } 289 282 290 283 if (dsc) { ··· 502 491 fxp_q4_from_int(1), true); 503 492 } 504 493 505 - static int mst_stream_update_slots(struct intel_dp *intel_dp, 506 - struct intel_crtc_state *crtc_state, 507 - struct drm_connector_state *conn_state) 508 - { 509 - struct intel_display *display = to_intel_display(intel_dp); 510 - struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr; 511 - struct drm_dp_mst_topology_state *topology_state; 512 - u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? 513 - DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; 514 - 515 - topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); 516 - if (IS_ERR(topology_state)) { 517 - drm_dbg_kms(display->drm, "slot update failed\n"); 518 - return PTR_ERR(topology_state); 519 - } 520 - 521 - drm_dp_mst_update_slots(topology_state, link_coding_cap); 522 - 523 - return 0; 524 - } 525 - 526 494 static int mode_hblank_period_ns(const struct drm_display_mode *mode) 527 495 { 528 496 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay, ··· 704 714 pipe_config->dp_m_n.tu); 705 715 } 706 716 707 - if (ret) 708 - return ret; 709 - 710 - ret = mst_stream_update_slots(intel_dp, pipe_config, conn_state); 711 717 if (ret) 712 718 return ret; 713 719