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drm/amdgpu: gate VM CPU HDP flush on reset lock

During GPU reset, the application could still run CPU page table updates. Each commit called
amdgpu_device_flush_hdp(), which on SR-IOV sends work through the KIQ ring.
That can advance sync_seq while the GPU is being reset,
leaving fence writeback out of sync and causing amdgpu_fence_emit_polling()
to time out on later KIQ use.

Fix:
amdgpu_vm_cpu_commit():
Reset will flush HDP anyway, the HDP flush in amdgpu_vm_cpu_commit() can be skipped
when a reset is ongoging.
Take reset_domain->sem with down_read_trylock() before amdgpu_device_flush_hdp().
If the reset path holds the write lock, skip the HDP flush so no HDP-related HW
access (including KIQ) runs during reset; state is re-established after reset.

Signed-off-by: Chenglei Xie <Chenglei.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

authored by

Chenglei Xie and committed by
Alex Deucher ddda81c4 574b3b14

+11 -1
+11 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
··· 21 21 */ 22 22 23 23 #include "amdgpu_vm.h" 24 + #include "amdgpu.h" 25 + #include "amdgpu_reset.h" 24 26 #include "amdgpu_object.h" 25 27 #include "amdgpu_trace.h" 26 28 ··· 110 108 static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p, 111 109 struct dma_fence **fence) 112 110 { 111 + struct amdgpu_device *adev = p->adev; 112 + 113 113 if (p->needs_flush) 114 114 atomic64_inc(&p->vm->tlb_seq); 115 115 116 116 mb(); 117 - amdgpu_device_flush_hdp(p->adev, NULL); 117 + /* A reset flushed the HDP anyway, so that here can be skipped when a reset is ongoing */ 118 + if (!down_read_trylock(&adev->reset_domain->sem)) 119 + return 0; 120 + 121 + amdgpu_device_flush_hdp(adev, NULL); 122 + up_read(&adev->reset_domain->sem); 123 + 118 124 return 0; 119 125 } 120 126