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Merge tag 'mvebu-dt64-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/late2
mvebu dt64 for 7.1 (part 1)
- Armada 37xx/3720 device tree fixes:
- Reorder USB PHYs, standardize names, drop undocumented
properties, fix schema alignment
- Add Marvell 7k COMe board bindings and uDPU ethernet aliases
- Cleanup: drop unused .dtsi files
* tag 'mvebu-dt64-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node
arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names
arm64: dts: marvell: armada-37xx: drop 'marvell,usb-misc-reg' from USB host nodes
arm64: dts: marvell: armada-37xx: drop redundant status property
arm64: dts: marvell: armada-37xx: align 'phy-names' of EHCI node with DT schema
dt-bindings: arm64: add Marvell 7k COMe boards
arm64: dts: marvell: armada-3720: drop 'marvell,xenon-emmc' properties
arm64: dts: marvell: uDPU: add ethernet aliases
arm/arm64: dts: marvell: Drop unused .dtsi
arm64: dts: a7k: use phy handle
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+10
-274
-148
arch/arm/boot/dts/marvell/armada-380.dtsi
-148
arch/arm/boot/dts/marvell/armada-380.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Device Tree Include file for Marvell Armada 380 SoC.
4
-
*
5
-
* Copyright (C) 2014 Marvell
6
-
*
7
-
* Lior Amsalem <alior@marvell.com>
8
-
* Gregory CLEMENT <gregory.clement@free-electrons.com>
9
-
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10
-
*/
11
-
12
-
#include "armada-38x.dtsi"
13
-
14
-
/ {
15
-
model = "Marvell Armada 380 family SoC";
16
-
compatible = "marvell,armada380";
17
-
18
-
cpus {
19
-
#address-cells = <1>;
20
-
#size-cells = <0>;
21
-
enable-method = "marvell,armada-380-smp";
22
-
23
-
cpu@0 {
24
-
device_type = "cpu";
25
-
compatible = "arm,cortex-a9";
26
-
reg = <0>;
27
-
};
28
-
};
29
-
30
-
soc {
31
-
internal-regs {
32
-
pinctrl@18000 {
33
-
compatible = "marvell,mv88f6810-pinctrl";
34
-
};
35
-
};
36
-
37
-
pcie {
38
-
compatible = "marvell,armada-370-pcie";
39
-
status = "disabled";
40
-
device_type = "pci";
41
-
42
-
#address-cells = <3>;
43
-
#size-cells = <2>;
44
-
45
-
msi-parent = <&mpic>;
46
-
bus-range = <0x00 0xff>;
47
-
48
-
ranges =
49
-
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50
-
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51
-
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52
-
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53
-
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54
-
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
55
-
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56
-
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
57
-
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58
-
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
59
-
60
-
/* x1 port */
61
-
pcie@1,0 {
62
-
device_type = "pci";
63
-
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
64
-
reg = <0x0800 0 0 0 0>;
65
-
#address-cells = <3>;
66
-
#size-cells = <2>;
67
-
interrupt-names = "intx";
68
-
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
69
-
#interrupt-cells = <1>;
70
-
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71
-
0x81000000 0 0 0x81000000 0x1 0 1 0>;
72
-
bus-range = <0x00 0xff>;
73
-
interrupt-map-mask = <0 0 0 7>;
74
-
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
75
-
<0 0 0 2 &pcie1_intc 1>,
76
-
<0 0 0 3 &pcie1_intc 2>,
77
-
<0 0 0 4 &pcie1_intc 3>;
78
-
marvell,pcie-port = <0>;
79
-
marvell,pcie-lane = <0>;
80
-
clocks = <&gateclk 8>;
81
-
status = "disabled";
82
-
83
-
pcie1_intc: interrupt-controller {
84
-
interrupt-controller;
85
-
#interrupt-cells = <1>;
86
-
};
87
-
};
88
-
89
-
/* x1 port */
90
-
pcie@2,0 {
91
-
device_type = "pci";
92
-
assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
93
-
reg = <0x1000 0 0 0 0>;
94
-
#address-cells = <3>;
95
-
#size-cells = <2>;
96
-
interrupt-names = "intx";
97
-
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
98
-
#interrupt-cells = <1>;
99
-
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100
-
0x81000000 0 0 0x81000000 0x2 0 1 0>;
101
-
bus-range = <0x00 0xff>;
102
-
interrupt-map-mask = <0 0 0 7>;
103
-
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
104
-
<0 0 0 2 &pcie2_intc 1>,
105
-
<0 0 0 3 &pcie2_intc 2>,
106
-
<0 0 0 4 &pcie2_intc 3>;
107
-
marvell,pcie-port = <1>;
108
-
marvell,pcie-lane = <0>;
109
-
clocks = <&gateclk 5>;
110
-
status = "disabled";
111
-
112
-
pcie2_intc: interrupt-controller {
113
-
interrupt-controller;
114
-
#interrupt-cells = <1>;
115
-
};
116
-
};
117
-
118
-
/* x1 port */
119
-
pcie@3,0 {
120
-
device_type = "pci";
121
-
assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
122
-
reg = <0x1800 0 0 0 0>;
123
-
#address-cells = <3>;
124
-
#size-cells = <2>;
125
-
interrupt-names = "intx";
126
-
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
127
-
#interrupt-cells = <1>;
128
-
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
129
-
0x81000000 0 0 0x81000000 0x3 0 1 0>;
130
-
bus-range = <0x00 0xff>;
131
-
interrupt-map-mask = <0 0 0 7>;
132
-
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
133
-
<0 0 0 2 &pcie3_intc 1>,
134
-
<0 0 0 3 &pcie3_intc 2>,
135
-
<0 0 0 4 &pcie3_intc 3>;
136
-
marvell,pcie-port = <2>;
137
-
marvell,pcie-lane = <0>;
138
-
clocks = <&gateclk 6>;
139
-
status = "disabled";
140
-
141
-
pcie3_intc: interrupt-controller {
142
-
interrupt-controller;
143
-
#interrupt-cells = <1>;
144
-
};
145
-
};
146
-
};
147
-
};
148
-
};
-1
arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
-1
arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+6
-1
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
+6
-1
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dtsi
···
15
15
#include "armada-372x.dtsi"
16
16
17
17
/ {
18
+
aliases {
19
+
ethernet0 = ð0;
20
+
ethernet1 = ð1;
21
+
};
22
+
18
23
chosen {
19
24
stdout-path = "serial0:115200n8";
20
25
};
···
161
156
&usb3 {
162
157
status = "okay";
163
158
phys = <&usb2_utmi_otg_phy>;
164
-
phy-names = "usb2-utmi-otg-phy";
159
+
phy-names = "usb2-phy";
165
160
};
166
161
167
162
&uart0 {
+3
-6
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+3
-6
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
···
369
369
compatible = "marvell,armada3700-xhci",
370
370
"generic-xhci";
371
371
reg = <0x58000 0x4000>;
372
-
marvell,usb-misc-reg = <&usb32_syscon>;
373
372
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
374
373
clocks = <&sb_periph_clk 12>;
375
-
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
376
-
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
374
+
phys = <&usb2_utmi_otg_phy>, <&comphy0 0>;
375
+
phy-names = "usb2-phy", "usb3-phy";
377
376
status = "disabled";
378
377
};
379
378
···
392
393
usb2: usb@5e000 {
393
394
compatible = "marvell,armada-3700-ehci";
394
395
reg = <0x5e000 0x1000>;
395
-
marvell,usb-misc-reg = <&usb2_syscon>;
396
396
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397
397
phys = <&usb2_utmi_host_phy>;
398
-
phy-names = "usb2-utmi-host-phy";
398
+
phy-names = "usb";
399
399
status = "disabled";
400
400
};
401
401
···
532
534
armada-3700-rwtm {
533
535
compatible = "marvell,armada-3700-rwtm-firmware";
534
536
mboxes = <&rwtm 0>;
535
-
status = "okay";
536
537
};
537
538
};
538
539
};
+1
-1
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
+1
-1
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
-20
arch/arm64/boot/dts/marvell/armada-8020.dtsi
-20
arch/arm64/boot/dts/marvell/armada-8020.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Copyright (C) 2016 Marvell Technology Group Ltd.
4
-
*
5
-
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
6
-
* two CP110.
7
-
*/
8
-
9
-
#include "armada-ap806-dual.dtsi"
10
-
#include "armada-80x0.dtsi"
11
-
12
-
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
13
-
* in CP master is not connected (by package) to the oscillator. So
14
-
* disable it. However, the RTC clock in CP slave is connected to the
15
-
* oscillator so this one is let enabled.
16
-
*/
17
-
18
-
&cp0_rtc {
19
-
status = "disabled";
20
-
};
-96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
-96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
-
/*
3
-
* Copyright (C) 2023 Marvell International Ltd.
4
-
*
5
-
* Device tree for the CN9130-DB Com Express CPU module board.
6
-
*/
7
-
8
-
#include "cn9130-db.dtsi"
9
-
10
-
/ {
11
-
model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
12
-
compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
13
-
"marvell,armada-ap807-quad", "marvell,armada-ap807";
14
-
15
-
};
16
-
17
-
&ap0_reg_sd_vccq {
18
-
regulator-max-microvolt = <1800000>;
19
-
states = <1800000 0x1 1800000 0x0>;
20
-
/delete-property/ gpios;
21
-
};
22
-
23
-
&cp0_reg_usb3_vbus0 {
24
-
/delete-property/ gpio;
25
-
};
26
-
27
-
&cp0_reg_usb3_vbus1 {
28
-
/delete-property/ gpio;
29
-
};
30
-
31
-
&cp0_reg_sd_vcc {
32
-
status = "disabled";
33
-
};
34
-
35
-
&cp0_reg_sd_vccq {
36
-
status = "disabled";
37
-
};
38
-
39
-
&cp0_sdhci0 {
40
-
status = "disabled";
41
-
};
42
-
43
-
&cp0_eth0 {
44
-
status = "disabled";
45
-
};
46
-
47
-
&cp0_eth1 {
48
-
status = "okay";
49
-
phy = <&phy0>;
50
-
phy-mode = "rgmii-id";
51
-
};
52
-
53
-
&cp0_eth2 {
54
-
status = "disabled";
55
-
};
56
-
57
-
&cp0_mdio {
58
-
status = "okay";
59
-
pinctrl-0 = <&cp0_ge_mdio_pins>;
60
-
phy0: ethernet-phy@0 {
61
-
status = "okay";
62
-
};
63
-
};
64
-
65
-
&cp0_syscon0 {
66
-
cp0_pinctrl: pinctrl {
67
-
compatible = "marvell,cp115-standalone-pinctrl";
68
-
69
-
cp0_ge_mdio_pins: ge-mdio-pins {
70
-
marvell,pins = "mpp40", "mpp41";
71
-
marvell,function = "ge";
72
-
};
73
-
};
74
-
};
75
-
76
-
&cp0_sdhci0 {
77
-
status = "disabled";
78
-
};
79
-
80
-
&cp0_spi1 {
81
-
status = "okay";
82
-
};
83
-
84
-
&cp0_usb3_0 {
85
-
status = "okay";
86
-
usb-phy = <&cp0_usb3_0_phy0>;
87
-
phy-names = "usb";
88
-
/delete-property/ phys;
89
-
};
90
-
91
-
&cp0_usb3_1 {
92
-
status = "okay";
93
-
usb-phy = <&cp0_usb3_0_phy1>;
94
-
phy-names = "usb";
95
-
/delete-property/ phys;
96
-
};