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drm/amd/powerplay: enable deep sleep by default for vega10

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
df057e02 4022e4f2

+61 -5
+61 -5
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 129 129 data->registry_data.ulv_support = 130 130 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 131 131 132 + data->registry_data.sclk_deep_sleep_support = 133 + hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 134 + 132 135 data->registry_data.disable_water_mark = 0; 133 136 134 137 data->registry_data.fan_control_support = 1; ··· 355 352 data->smu_features[GNLD_DS_GFXCLK].supported = true; 356 353 data->smu_features[GNLD_DS_SOCCLK].supported = true; 357 354 data->smu_features[GNLD_DS_LCLK].supported = true; 355 + data->smu_features[GNLD_DS_DCEFCLK].supported = true; 358 356 } 359 357 360 358 if (data->registry_data.enable_pkg_pwr_tracking_feature) ··· 2612 2608 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2613 2609 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2614 2610 "Attempt to Enable DS_GFXCLK Feature Failed!", 2615 - return -1); 2611 + return -EINVAL); 2616 2612 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 2617 2613 } 2618 2614 2619 2615 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2620 2616 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2621 2617 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2622 - "Attempt to Enable DS_GFXCLK Feature Failed!", 2623 - return -1); 2618 + "Attempt to Enable DS_SOCCLK Feature Failed!", 2619 + return -EINVAL); 2624 2620 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 2625 2621 } 2626 2622 2627 2623 if (data->smu_features[GNLD_DS_LCLK].supported) { 2628 2624 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2629 2625 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2630 - "Attempt to Enable DS_GFXCLK Feature Failed!", 2631 - return -1); 2626 + "Attempt to Enable DS_LCLK Feature Failed!", 2627 + return -EINVAL); 2632 2628 data->smu_features[GNLD_DS_LCLK].enabled = true; 2629 + } 2630 + 2631 + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2632 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2633 + true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2634 + "Attempt to Enable DS_DCEFCLK Feature Failed!", 2635 + return -EINVAL); 2636 + data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 2637 + } 2638 + 2639 + return 0; 2640 + } 2641 + 2642 + static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2643 + { 2644 + struct vega10_hwmgr *data = 2645 + (struct vega10_hwmgr *)(hwmgr->backend); 2646 + 2647 + if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2648 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2649 + false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2650 + "Attempt to disable DS_GFXCLK Feature Failed!", 2651 + return -EINVAL); 2652 + data->smu_features[GNLD_DS_GFXCLK].enabled = false; 2653 + } 2654 + 2655 + if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2656 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2657 + false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2658 + "Attempt to disable DS_ Feature Failed!", 2659 + return -EINVAL); 2660 + data->smu_features[GNLD_DS_SOCCLK].enabled = false; 2661 + } 2662 + 2663 + if (data->smu_features[GNLD_DS_LCLK].supported) { 2664 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2665 + false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2666 + "Attempt to disable DS_LCLK Feature Failed!", 2667 + return -EINVAL); 2668 + data->smu_features[GNLD_DS_LCLK].enabled = false; 2669 + } 2670 + 2671 + if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2672 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2673 + false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2674 + "Attempt to disable DS_DCEFCLK Feature Failed!", 2675 + return -EINVAL); 2676 + data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 2633 2677 } 2634 2678 2635 2679 return 0; ··· 4602 4550 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 4603 4551 PP_ASSERT_WITH_CODE((tmp_result == 0), 4604 4552 "Failed to stop DPM!", result = tmp_result); 4553 + 4554 + tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); 4555 + PP_ASSERT_WITH_CODE((tmp_result == 0), 4556 + "Failed to disable deep sleep!", result = tmp_result); 4605 4557 4606 4558 tmp_result = vega10_disable_ulv(hwmgr); 4607 4559 PP_ASSERT_WITH_CODE((tmp_result == 0),