tjh.dev / kernel
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"A bumper crop of arm64 fixes for -rc3.

The largest change is fixing our parsing of the 'rodata=full' command
line option, which kstrtobool() started treating as 'rodata=false'.
The fix actually makes the parsing of that option much less fragile
and updates the documentation at the same time.

We still have a boot issue pending when KASLR is disabled at compile
time, but there's a fresh fix on the list which I'll send next week if
it holds up to testing.

Summary:

- Fix workaround for Cortex-A76 erratum #1286807

- Add workaround for AMU erratum #2457168 on Cortex-A510

- Drop reference to removed CONFIG_ARCH_RANDOM #define

- Fix parsing of the "rodata=full" cmdline option

- Fix a bunch of issues in the SME register state switching and sigframe code

- Fix incorrect extraction of the CTR_EL0.CWG register field

- Fix ACPI cache topology probing when the PPTT is not present

- Trivial comment and whitespace fixes"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/sme: Don't flush SVE register state when handling SME traps
arm64/sme: Don't flush SVE register state when allocating SME storage
arm64/signal: Flush FPSIMD register state when disabling streaming mode
arm64/signal: Raise limit on stack frames
arm64/cache: Fix cache_type_cwg() for register generation
arm64/sysreg: Guard SYS_FIELD_ macros for asm
arm64/sysreg: Directly include bitfield.h
arm64: cacheinfo: Fix incorrect assignment of signed error value to unsigned fw_level
arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
arm64: fix rodata=full
arm64: Fix comment typo
docs/arm64: elf_hwcaps: unify newlines in HWCAP lists
arm64: adjust KASLR relocation after ARCH_RANDOM removal
arm64: Fix match_list for erratum 1286807 on Arm Cortex-A76

Linus Torvalds e022620b 012bd7e8

+136 -66
+2
Documentation/admin-guide/kernel-parameters.txt
··· 5331 5331 rodata= [KNL] 5332 5332 on Mark read-only kernel memory as read-only (default). 5333 5333 off Leave read-only kernel memory writable for debugging. 5334 + full Mark read-only kernel memory and aliases as read-only 5335 + [arm64] 5334 5336 5335 5337 rockchip.usb_uart 5336 5338 Enable the uart passthrough on the designated usb port
-10
Documentation/arm64/elf_hwcaps.rst
··· 242 242 by Documentation/arm64/memory-tagging-extension.rst. 243 243 244 244 HWCAP2_SME 245 - 246 245 Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described 247 246 by Documentation/arm64/sme.rst. 248 247 249 248 HWCAP2_SME_I16I64 250 - 251 249 Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111. 252 250 253 251 HWCAP2_SME_F64F64 254 - 255 252 Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1. 256 253 257 254 HWCAP2_SME_I8I32 258 - 259 255 Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111. 260 256 261 257 HWCAP2_SME_F16F32 262 - 263 258 Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1. 264 259 265 260 HWCAP2_SME_B16F32 266 - 267 261 Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1. 268 262 269 263 HWCAP2_SME_F32F32 270 - 271 264 Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1. 272 265 273 266 HWCAP2_SME_FA64 274 - 275 267 Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1. 276 268 277 269 HWCAP2_WFXT 278 - 279 270 Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010. 280 271 281 272 HWCAP2_EBF16 282 - 283 273 Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010. 284 274 285 275 4. Unused AT_HWCAP bits
+2
Documentation/arm64/silicon-errata.rst
··· 52 52 | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | 53 53 +----------------+-----------------+-----------------+-----------------------------+ 54 54 +----------------+-----------------+-----------------+-----------------------------+ 55 + | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | 56 + +----------------+-----------------+-----------------+-----------------------------+ 55 57 | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | 56 58 +----------------+-----------------+-----------------+-----------------------------+ 57 59 | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
+17
arch/arm64/Kconfig
··· 917 917 918 918 If unsure, say Y. 919 919 920 + config ARM64_ERRATUM_2457168 921 + bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 922 + depends on ARM64_AMU_EXTN 923 + default y 924 + help 925 + This option adds the workaround for ARM Cortex-A510 erratum 2457168. 926 + 927 + The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 928 + as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 929 + incorrectly giving a significantly higher output value. 930 + 931 + Work around this problem by returning 0 when reading the affected counter in 932 + key locations that results in disabling all users of this counter. This effect 933 + is the same to firmware disabling affected counters. 934 + 935 + If unsure, say Y. 936 + 920 937 config CAVIUM_ERRATUM_22375 921 938 bool "Cavium erratum 22375, 24313" 922 939 default y
+1 -1
arch/arm64/include/asm/cache.h
··· 71 71 72 72 static inline u32 cache_type_cwg(void) 73 73 { 74 - return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK; 74 + return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype()); 75 75 } 76 76 77 77 #define __read_mostly __section(".data..read_mostly")
+2 -2
arch/arm64/include/asm/fpsimd.h
··· 153 153 154 154 #ifdef CONFIG_ARM64_SVE 155 155 156 - extern void sve_alloc(struct task_struct *task); 156 + extern void sve_alloc(struct task_struct *task, bool flush); 157 157 extern void fpsimd_release_task(struct task_struct *task); 158 158 extern void fpsimd_sync_to_sve(struct task_struct *task); 159 159 extern void fpsimd_force_sync_to_sve(struct task_struct *task); ··· 256 256 257 257 #else /* ! CONFIG_ARM64_SVE */ 258 258 259 - static inline void sve_alloc(struct task_struct *task) { } 259 + static inline void sve_alloc(struct task_struct *task, bool flush) { } 260 260 static inline void fpsimd_release_task(struct task_struct *task) { } 261 261 static inline void sve_sync_to_fpsimd(struct task_struct *task) { } 262 262 static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { }
+17
arch/arm64/include/asm/setup.h
··· 3 3 #ifndef __ARM64_ASM_SETUP_H 4 4 #define __ARM64_ASM_SETUP_H 5 5 6 + #include <linux/string.h> 7 + 6 8 #include <uapi/asm/setup.h> 7 9 8 10 void *get_early_fdt_ptr(void); ··· 15 13 */ 16 14 extern phys_addr_t __fdt_pointer __initdata; 17 15 extern u64 __cacheline_aligned boot_args[4]; 16 + 17 + static inline bool arch_parse_debug_rodata(char *arg) 18 + { 19 + extern bool rodata_enabled; 20 + extern bool rodata_full; 21 + 22 + if (arg && !strcmp(arg, "full")) { 23 + rodata_enabled = true; 24 + rodata_full = true; 25 + return true; 26 + } 27 + 28 + return false; 29 + } 30 + #define arch_parse_debug_rodata arch_parse_debug_rodata 18 31 19 32 #endif
+3 -2
arch/arm64/include/asm/sysreg.h
··· 1116 1116 1117 1117 #else 1118 1118 1119 + #include <linux/bitfield.h> 1119 1120 #include <linux/build_bug.h> 1120 1121 #include <linux/types.h> 1121 1122 #include <asm/alternative.h> ··· 1210 1209 par; \ 1211 1210 }) 1212 1211 1213 - #endif 1214 - 1215 1212 #define SYS_FIELD_GET(reg, field, val) \ 1216 1213 FIELD_GET(reg##_##field##_MASK, val) 1217 1214 ··· 1218 1219 1219 1220 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 1220 1221 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val) 1222 + 1223 + #endif 1221 1224 1222 1225 #endif /* __ASM_SYSREG_H */
+5 -1
arch/arm64/kernel/cacheinfo.c
··· 45 45 46 46 int init_cache_level(unsigned int cpu) 47 47 { 48 - unsigned int ctype, level, leaves, fw_level; 48 + unsigned int ctype, level, leaves; 49 + int fw_level; 49 50 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 50 51 51 52 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { ··· 63 62 fw_level = of_find_last_cache_level(cpu); 64 63 else 65 64 fw_level = acpi_find_last_cache_level(cpu); 65 + 66 + if (fw_level < 0) 67 + return fw_level; 66 68 67 69 if (level < fw_level) { 68 70 /*
+12
arch/arm64/kernel/cpu_errata.c
··· 208 208 #ifdef CONFIG_ARM64_ERRATUM_1286807 209 209 { 210 210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 211 + }, 212 + { 211 213 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 212 214 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 213 215 }, ··· 654 652 655 653 /* Cortex-A510 r0p0 - r0p2 */ 656 654 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 655 + }, 656 + #endif 657 + #ifdef CONFIG_ARM64_ERRATUM_2457168 658 + { 659 + .desc = "ARM erratum 2457168", 660 + .capability = ARM64_WORKAROUND_2457168, 661 + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 662 + 663 + /* Cortex-A510 r0p0-r1p1 */ 664 + CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) 657 665 }, 658 666 #endif 659 667 #ifdef CONFIG_ARM64_ERRATUM_2038923
+4 -1
arch/arm64/kernel/cpufeature.c
··· 1870 1870 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1871 1871 smp_processor_id()); 1872 1872 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1873 - update_freq_counters_refs(); 1873 + 1874 + /* 0 reference values signal broken/disabled counters */ 1875 + if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1876 + update_freq_counters_refs(); 1874 1877 } 1875 1878 } 1876 1879
+1 -1
arch/arm64/kernel/entry.S
··· 502 502 SYM_CODE_START(vectors) 503 503 kernel_ventry 1, t, 64, sync // Synchronous EL1t 504 504 kernel_ventry 1, t, 64, irq // IRQ EL1t 505 - kernel_ventry 1, t, 64, fiq // FIQ EL1h 505 + kernel_ventry 1, t, 64, fiq // FIQ EL1t 506 506 kernel_ventry 1, t, 64, error // Error EL1t 507 507 508 508 kernel_ventry 1, h, 64, sync // Synchronous EL1h
+6 -15
arch/arm64/kernel/fpsimd.c
··· 715 715 * do_sve_acc() case, there is no ABI requirement to hide stale data 716 716 * written previously be task. 717 717 */ 718 - void sve_alloc(struct task_struct *task) 718 + void sve_alloc(struct task_struct *task, bool flush) 719 719 { 720 720 if (task->thread.sve_state) { 721 - memset(task->thread.sve_state, 0, sve_state_size(task)); 721 + if (flush) 722 + memset(task->thread.sve_state, 0, 723 + sve_state_size(task)); 722 724 return; 723 725 } 724 726 ··· 1390 1388 return; 1391 1389 } 1392 1390 1393 - sve_alloc(current); 1391 + sve_alloc(current, true); 1394 1392 if (!current->thread.sve_state) { 1395 1393 force_sig(SIGKILL); 1396 1394 return; ··· 1441 1439 return; 1442 1440 } 1443 1441 1444 - sve_alloc(current); 1442 + sve_alloc(current, false); 1445 1443 sme_alloc(current); 1446 1444 if (!current->thread.sve_state || !current->thread.za_state) { 1447 1445 force_sig(SIGKILL); ··· 1461 1459 1462 1460 fpsimd_bind_task_to_cpu(); 1463 1461 } 1464 - 1465 - /* 1466 - * If SVE was not already active initialise the SVE registers, 1467 - * any non-shared state between the streaming and regular SVE 1468 - * registers is architecturally guaranteed to be zeroed when 1469 - * we enter streaming mode. We do not need to initialize ZA 1470 - * since ZA must be disabled at this point and enabling ZA is 1471 - * architecturally defined to zero ZA. 1472 - */ 1473 - if (system_supports_sve() && !test_thread_flag(TIF_SVE)) 1474 - sve_init_regs(); 1475 1462 1476 1463 put_cpu_fpsimd_context(); 1477 1464 }
+3 -5
arch/arm64/kernel/pi/kaslr_early.c
··· 94 94 95 95 seed = get_kaslr_seed(fdt); 96 96 if (!seed) { 97 - #ifdef CONFIG_ARCH_RANDOM 98 - if (!__early_cpu_has_rndr() || 99 - !__arm64_rndr((unsigned long *)&seed)) 100 - #endif 101 - return 0; 97 + if (!__early_cpu_has_rndr() || 98 + !__arm64_rndr((unsigned long *)&seed)) 99 + return 0; 102 100 } 103 101 104 102 /*
+3 -3
arch/arm64/kernel/ptrace.c
··· 882 882 * state and ensure there's storage. 883 883 */ 884 884 if (target->thread.svcr != old_svcr) 885 - sve_alloc(target); 885 + sve_alloc(target, true); 886 886 } 887 887 888 888 /* Registers: FPSIMD-only case */ ··· 912 912 goto out; 913 913 } 914 914 915 - sve_alloc(target); 915 + sve_alloc(target, true); 916 916 if (!target->thread.sve_state) { 917 917 ret = -ENOMEM; 918 918 clear_tsk_thread_flag(target, TIF_SVE); ··· 1082 1082 1083 1083 /* Ensure there is some SVE storage for streaming mode */ 1084 1084 if (!target->thread.sve_state) { 1085 - sve_alloc(target); 1085 + sve_alloc(target, false); 1086 1086 if (!target->thread.sve_state) { 1087 1087 clear_thread_flag(TIF_SME); 1088 1088 ret = -ENOMEM;
+12 -2
arch/arm64/kernel/signal.c
··· 91 91 * not taken into account. This limit is not a guarantee and is 92 92 * NOT ABI. 93 93 */ 94 - #define SIGFRAME_MAXSZ SZ_64K 94 + #define SIGFRAME_MAXSZ SZ_256K 95 95 96 96 static int __sigframe_alloc(struct rt_sigframe_user_layout *user, 97 97 unsigned long *offset, size_t size, bool extend) ··· 310 310 fpsimd_flush_task_state(current); 311 311 /* From now, fpsimd_thread_switch() won't touch thread.sve_state */ 312 312 313 - sve_alloc(current); 313 + sve_alloc(current, true); 314 314 if (!current->thread.sve_state) { 315 315 clear_thread_flag(TIF_SVE); 316 316 return -ENOMEM; ··· 926 926 927 927 /* Signal handlers are invoked with ZA and streaming mode disabled */ 928 928 if (system_supports_sme()) { 929 + /* 930 + * If we were in streaming mode the saved register 931 + * state was SVE but we will exit SM and use the 932 + * FPSIMD register state - flush the saved FPSIMD 933 + * register state in case it gets loaded. 934 + */ 935 + if (current->thread.svcr & SVCR_SM_MASK) 936 + memset(&current->thread.uw.fpsimd_state, 0, 937 + sizeof(current->thread.uw.fpsimd_state)); 938 + 929 939 current->thread.svcr &= ~(SVCR_ZA_MASK | 930 940 SVCR_SM_MASK); 931 941 sme_smstop();
+30 -2
arch/arm64/kernel/topology.c
··· 296 296 297 297 static void cpu_read_corecnt(void *val) 298 298 { 299 + /* 300 + * A value of 0 can be returned if the current CPU does not support AMUs 301 + * or if the counter is disabled for this CPU. A return value of 0 at 302 + * counter read is properly handled as an error case by the users of the 303 + * counter. 304 + */ 299 305 *(u64 *)val = read_corecnt(); 300 306 } 301 307 302 308 static void cpu_read_constcnt(void *val) 303 309 { 304 - *(u64 *)val = read_constcnt(); 310 + /* 311 + * Return 0 if the current CPU is affected by erratum 2457168. A value 312 + * of 0 is also returned if the current CPU does not support AMUs or if 313 + * the counter is disabled. A return value of 0 at counter read is 314 + * properly handled as an error case by the users of the counter. 315 + */ 316 + *(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ? 317 + 0UL : read_constcnt(); 305 318 } 306 319 307 320 static inline ··· 341 328 */ 342 329 bool cpc_ffh_supported(void) 343 330 { 344 - return freq_counters_valid(get_cpu_with_amu_feat()); 331 + int cpu = get_cpu_with_amu_feat(); 332 + 333 + /* 334 + * FFH is considered supported if there is at least one present CPU that 335 + * supports AMUs. Using FFH to read core and reference counters for CPUs 336 + * that do not support AMUs, have counters disabled or that are affected 337 + * by errata, will result in a return value of 0. 338 + * 339 + * This is done to allow any enabled and valid counters to be read 340 + * through FFH, knowing that potentially returning 0 as counter value is 341 + * properly handled by the users of these counters. 342 + */ 343 + if ((cpu >= nr_cpu_ids) || !cpumask_test_cpu(cpu, cpu_present_mask)) 344 + return false; 345 + 346 + return true; 345 347 } 346 348 347 349 int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
-18
arch/arm64/mm/mmu.c
··· 642 642 vm_area_add_early(vma); 643 643 } 644 644 645 - static int __init parse_rodata(char *arg) 646 - { 647 - int ret = strtobool(arg, &rodata_enabled); 648 - if (!ret) { 649 - rodata_full = false; 650 - return 0; 651 - } 652 - 653 - /* permit 'full' in addition to boolean options */ 654 - if (strcmp(arg, "full")) 655 - return -EINVAL; 656 - 657 - rodata_enabled = true; 658 - rodata_full = true; 659 - return 0; 660 - } 661 - early_param("rodata", parse_rodata); 662 - 663 645 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 664 646 static int __init map_entry_trampoline(void) 665 647 {
+1
arch/arm64/tools/cpucaps
··· 67 67 WORKAROUND_2038923 68 68 WORKAROUND_2064142 69 69 WORKAROUND_2077057 70 + WORKAROUND_2457168 70 71 WORKAROUND_TRBE_OVERWRITE_FILL_MODE 71 72 WORKAROUND_TSB_FLUSH_FAILURE 72 73 WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
+15 -3
init/main.c
··· 1446 1446 1447 1447 #if defined(CONFIG_STRICT_KERNEL_RWX) || defined(CONFIG_STRICT_MODULE_RWX) 1448 1448 bool rodata_enabled __ro_after_init = true; 1449 + 1450 + #ifndef arch_parse_debug_rodata 1451 + static inline bool arch_parse_debug_rodata(char *str) { return false; } 1452 + #endif 1453 + 1449 1454 static int __init set_debug_rodata(char *str) 1450 1455 { 1451 - if (strtobool(str, &rodata_enabled)) 1456 + if (arch_parse_debug_rodata(str)) 1457 + return 0; 1458 + 1459 + if (str && !strcmp(str, "on")) 1460 + rodata_enabled = true; 1461 + else if (str && !strcmp(str, "off")) 1462 + rodata_enabled = false; 1463 + else 1452 1464 pr_warn("Invalid option string for rodata: '%s'\n", str); 1453 - return 1; 1465 + return 0; 1454 1466 } 1455 - __setup("rodata=", set_debug_rodata); 1467 + early_param("rodata", set_debug_rodata); 1456 1468 #endif 1457 1469 1458 1470 #ifdef CONFIG_STRICT_KERNEL_RWX