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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Merge tag 'mtd/fixes-for-4.17-rc5' of git://git.infradead.org/linux-mtd
Pull mtd fixes from Boris Brezillon:
- make nand_soft_waitrdy() wait tWB before polling the status REG
- fix BCH write in the the Marvell NAND controller driver
- fix wrong picosec to msec conversion in the Marvell NAND controller
driver
- fix DMA handling in the TI OneNAND controllre driver
* tag 'mtd/fixes-for-4.17-rc5' of git://git.infradead.org/linux-mtd:
mtd: rawnand: Make sure we wait tWB before polling the STATUS reg
mtd: rawnand: marvell: fix command xtype in BCH write hook
mtd: rawnand: marvell: pass ms delay to wait_op
mtd: onenand: omap2: Disable DMA for HIGHMEM buffers
+52
-70
+38
-67
drivers/mtd/nand/onenand/omap2.c
+38
-67
drivers/mtd/nand/onenand/omap2.c
···
375
375
{
376
376
struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
377
377
struct onenand_chip *this = mtd->priv;
378
-
dma_addr_t dma_src, dma_dst;
379
-
int bram_offset;
378
+
struct device *dev = &c->pdev->dev;
380
379
void *buf = (void *)buffer;
380
+
dma_addr_t dma_src, dma_dst;
381
+
int bram_offset, err;
381
382
size_t xtra;
382
-
int ret;
383
383
384
384
bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
385
-
if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
385
+
/*
386
+
* If the buffer address is not DMA-able, len is not long enough to make
387
+
* DMA transfers profitable or panic_write() may be in an interrupt
388
+
* context fallback to PIO mode.
389
+
*/
390
+
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
391
+
count < 384 || in_interrupt() || oops_in_progress )
386
392
goto out_copy;
387
-
388
-
/* panic_write() may be in an interrupt context */
389
-
if (in_interrupt() || oops_in_progress)
390
-
goto out_copy;
391
-
392
-
if (buf >= high_memory) {
393
-
struct page *p1;
394
-
395
-
if (((size_t)buf & PAGE_MASK) !=
396
-
((size_t)(buf + count - 1) & PAGE_MASK))
397
-
goto out_copy;
398
-
p1 = vmalloc_to_page(buf);
399
-
if (!p1)
400
-
goto out_copy;
401
-
buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
402
-
}
403
393
404
394
xtra = count & 3;
405
395
if (xtra) {
···
397
407
memcpy(buf + count, this->base + bram_offset + count, xtra);
398
408
}
399
409
410
+
dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
400
411
dma_src = c->phys_base + bram_offset;
401
-
dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
402
-
if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
403
-
dev_err(&c->pdev->dev,
404
-
"Couldn't DMA map a %d byte buffer\n",
405
-
count);
412
+
413
+
if (dma_mapping_error(dev, dma_dst)) {
414
+
dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
406
415
goto out_copy;
407
416
}
408
417
409
-
ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
410
-
dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
418
+
err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
419
+
dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
420
+
if (!err)
421
+
return 0;
411
422
412
-
if (ret) {
413
-
dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
414
-
goto out_copy;
415
-
}
416
-
417
-
return 0;
423
+
dev_err(dev, "timeout waiting for DMA\n");
418
424
419
425
out_copy:
420
426
memcpy(buf, this->base + bram_offset, count);
···
423
437
{
424
438
struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
425
439
struct onenand_chip *this = mtd->priv;
426
-
dma_addr_t dma_src, dma_dst;
427
-
int bram_offset;
440
+
struct device *dev = &c->pdev->dev;
428
441
void *buf = (void *)buffer;
429
-
int ret;
442
+
dma_addr_t dma_src, dma_dst;
443
+
int bram_offset, err;
430
444
431
445
bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
432
-
if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
446
+
/*
447
+
* If the buffer address is not DMA-able, len is not long enough to make
448
+
* DMA transfers profitable or panic_write() may be in an interrupt
449
+
* context fallback to PIO mode.
450
+
*/
451
+
if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
452
+
count < 384 || in_interrupt() || oops_in_progress )
433
453
goto out_copy;
434
454
435
-
/* panic_write() may be in an interrupt context */
436
-
if (in_interrupt() || oops_in_progress)
437
-
goto out_copy;
438
-
439
-
if (buf >= high_memory) {
440
-
struct page *p1;
441
-
442
-
if (((size_t)buf & PAGE_MASK) !=
443
-
((size_t)(buf + count - 1) & PAGE_MASK))
444
-
goto out_copy;
445
-
p1 = vmalloc_to_page(buf);
446
-
if (!p1)
447
-
goto out_copy;
448
-
buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
449
-
}
450
-
451
-
dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
455
+
dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
452
456
dma_dst = c->phys_base + bram_offset;
453
-
if (dma_mapping_error(&c->pdev->dev, dma_src)) {
454
-
dev_err(&c->pdev->dev,
455
-
"Couldn't DMA map a %d byte buffer\n",
456
-
count);
457
-
return -1;
458
-
}
459
-
460
-
ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
461
-
dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
462
-
463
-
if (ret) {
464
-
dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
457
+
if (dma_mapping_error(dev, dma_src)) {
458
+
dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
465
459
goto out_copy;
466
460
}
467
461
468
-
return 0;
462
+
err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
463
+
dma_unmap_page(dev, dma_src, count, DMA_TO_DEVICE);
464
+
if (!err)
465
+
return 0;
466
+
467
+
dev_err(dev, "timeout waiting for DMA\n");
469
468
470
469
out_copy:
471
470
memcpy(this->base + bram_offset, buf, count);
+9
-3
drivers/mtd/nand/raw/marvell_nand.c
+9
-3
drivers/mtd/nand/raw/marvell_nand.c
···
1074
1074
return ret;
1075
1075
1076
1076
ret = marvell_nfc_wait_op(chip,
1077
-
chip->data_interface.timings.sdr.tPROG_max);
1077
+
PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1078
1078
return ret;
1079
1079
}
1080
1080
···
1408
1408
struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1409
1409
struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1410
1410
const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1411
+
u32 xtype;
1411
1412
int ret;
1412
1413
struct marvell_nfc_op nfc_op = {
1413
1414
.ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
···
1424
1423
* last naked write.
1425
1424
*/
1426
1425
if (chunk == 0) {
1427
-
nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) |
1426
+
if (lt->nchunks == 1)
1427
+
xtype = XTYPE_MONOLITHIC_RW;
1428
+
else
1429
+
xtype = XTYPE_WRITE_DISPATCH;
1430
+
1431
+
nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
1428
1432
NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1429
1433
NDCB0_CMD1(NAND_CMD_SEQIN);
1430
1434
nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
···
1500
1494
}
1501
1495
1502
1496
ret = marvell_nfc_wait_op(chip,
1503
-
chip->data_interface.timings.sdr.tPROG_max);
1497
+
PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1504
1498
1505
1499
marvell_nfc_disable_hw_ecc(chip);
1506
1500
+5
drivers/mtd/nand/raw/nand_base.c
+5
drivers/mtd/nand/raw/nand_base.c
···
706
706
*/
707
707
int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
708
708
{
709
+
const struct nand_sdr_timings *timings;
709
710
u8 status = 0;
710
711
int ret;
711
712
712
713
if (!chip->exec_op)
713
714
return -ENOTSUPP;
715
+
716
+
/* Wait tWB before polling the STATUS reg. */
717
+
timings = nand_get_sdr_timings(&chip->data_interface);
718
+
ndelay(PSEC_TO_NSEC(timings->tWB_max));
714
719
715
720
ret = nand_status_op(chip, NULL);
716
721
if (ret)