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drm/msm/dsi_phy_28nm: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series. The change to use clamp_t() was
done manually.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/667872/
Link: https://lore.kernel.org/r/20250810-drm-msm-phy-clk-round-rate-v2-4-0fd1f7979c83@redhat.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Brian Masney and committed by
Dmitry Baryshkov e04baa0b 267c0a2d

+10 -11
+10 -11
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
··· 533 533 pll_28nm->phy->pll_on = false; 534 534 } 535 535 536 - static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, 537 - unsigned long rate, unsigned long *parent_rate) 536 + static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, 537 + struct clk_rate_request *req) 538 538 { 539 539 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); 540 540 541 - if (rate < pll_28nm->phy->cfg->min_pll_rate) 542 - return pll_28nm->phy->cfg->min_pll_rate; 543 - else if (rate > pll_28nm->phy->cfg->max_pll_rate) 544 - return pll_28nm->phy->cfg->max_pll_rate; 545 - else 546 - return rate; 541 + req->rate = clamp_t(unsigned long, req->rate, 542 + pll_28nm->phy->cfg->min_pll_rate, 543 + pll_28nm->phy->cfg->max_pll_rate); 544 + 545 + return 0; 547 546 } 548 547 549 548 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_hpm = { 550 - .round_rate = dsi_pll_28nm_clk_round_rate, 549 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 551 550 .set_rate = dsi_pll_28nm_clk_set_rate, 552 551 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 553 552 .prepare = dsi_pll_28nm_vco_prepare_hpm, ··· 555 556 }; 556 557 557 558 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { 558 - .round_rate = dsi_pll_28nm_clk_round_rate, 559 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 559 560 .set_rate = dsi_pll_28nm_clk_set_rate, 560 561 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 561 562 .prepare = dsi_pll_28nm_vco_prepare_lp, ··· 564 565 }; 565 566 566 567 static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { 567 - .round_rate = dsi_pll_28nm_clk_round_rate, 568 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 568 569 .set_rate = dsi_pll_28nm_clk_set_rate, 569 570 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 570 571 .prepare = dsi_pll_28nm_vco_prepare_8226,