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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: renesas: r9a07g043: Add GbEthernet clock/reset
Add ETH{0,1} clock/reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
e11f804a
f201eb84
+10
+10
drivers/clk/renesas/r9a07g043-cpg.c
+10
drivers/clk/renesas/r9a07g043-cpg.c
···
111
111
0x52c, 0),
112
112
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
113
113
0x52c, 1),
114
+
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
115
+
0x57c, 0),
116
+
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
117
+
0x57c, 0),
118
+
DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
119
+
0x57c, 1),
120
+
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
121
+
0x57c, 1),
114
122
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
115
123
0x584, 0),
116
124
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
···
143
135
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
144
136
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
145
137
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
138
+
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
139
+
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
146
140
DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
147
141
DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
148
142
DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),