tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: renesas: r9a07g043: Add ethernet clock sources

Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven f201eb84 6c185664

+13
+13
drivers/clk/renesas/r9a07g043-cpg.c
··· 32 32 CLK_PLL3_DIV2_4, 33 33 CLK_PLL3_DIV2_4_2, 34 34 CLK_PLL5, 35 + CLK_PLL5_500, 36 + CLK_PLL5_250, 35 37 CLK_PLL6, 38 + CLK_PLL6_250, 36 39 CLK_P1_DIV2, 37 40 38 41 /* Module Clocks */ ··· 60 57 {0, 0}, 61 58 }; 62 59 60 + /* Mux clock tables */ 61 + static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 62 + 63 63 static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 64 64 /* External Clock Inputs */ 65 65 DEF_INPUT("extal", CLK_EXTAL), ··· 79 73 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 80 74 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 81 75 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 76 + DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), 77 + DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), 82 78 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 79 + DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 83 80 84 81 /* Core output clk */ 85 82 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, ··· 94 85 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 95 86 DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, 96 87 DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 88 + DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 89 + DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 90 + DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, 91 + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), 97 92 }; 98 93 99 94 static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {