tjh.dev / kernel
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crypto: octeontx2 - increase CPT HW instruction queue length

LDWB is getting incorrectly used in HW when
CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
320 free entries. So, increase HW instruction queue size by 320 and give
320 entries less for SW/NIX RX as a SW workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Srujana Challa and committed by
Herbert Xu e236ab0d 9eef6e97

+15 -4
+15 -4
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
··· 26 26 */ 27 27 #define OTX2_CPT_INST_QLEN_MSGS ((OTX2_CPT_SIZE_DIV40 - 1) * 40) 28 28 29 + /* 30 + * LDWB is getting incorrectly used when IQB_LDWB = 1 and CPT instruction 31 + * queue has less than 320 free entries. So, increase HW instruction queue 32 + * size by 320 and give 320 entries less for SW/NIX RX as a workaround. 33 + */ 34 + #define OTX2_CPT_INST_QLEN_EXTRA_BYTES (320 * OTX2_CPT_INST_SIZE) 35 + #define OTX2_CPT_EXTRA_SIZE_DIV40 (320/40) 36 + 29 37 /* CPT instruction queue length in bytes */ 30 - #define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \ 31 - OTX2_CPT_INST_SIZE) 38 + #define OTX2_CPT_INST_QLEN_BYTES \ 39 + ((OTX2_CPT_SIZE_DIV40 * 40 * OTX2_CPT_INST_SIZE) + \ 40 + OTX2_CPT_INST_QLEN_EXTRA_BYTES) 32 41 33 42 /* CPT instruction group queue length in bytes */ 34 - #define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16) 43 + #define OTX2_CPT_INST_GRP_QLEN_BYTES \ 44 + ((OTX2_CPT_SIZE_DIV40 + OTX2_CPT_EXTRA_SIZE_DIV40) * 16) 35 45 36 46 /* CPT FC length in bytes */ 37 47 #define OTX2_CPT_Q_FC_LEN 128 ··· 189 179 { 190 180 union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 }; 191 181 192 - lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40; 182 + lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 + 183 + OTX2_CPT_EXTRA_SIZE_DIV40; 193 184 otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot, 194 185 OTX2_CPT_LF_Q_SIZE, lf_q_size.u); 195 186 }