Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add/update skylake events/metrics
Update events from v58 to v59.
Update TMA metrics from v4.7 to v4.8.
Bring in the event updates v59:
https://github.com/intel/perfmon/commit/5d36f1835b02f056031a06e777e4bf54a5964930
The TMA 4.8 information was added in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736
Add counter information. The most recent RFC patch set using this
information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
Adds the event SW_PREFETCH_ACCESS.ANY.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-32-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
e2641db8
caccae3c
+756
-91
+1
-1
tools/perf/pmu-events/arch/x86/mapfile.csv
+1
-1
tools/perf/pmu-events/arch/x86/mapfile.csv
···
29
29
GenuineIntel-6-8F,v1.23,sapphirerapids,core
30
30
GenuineIntel-6-AF,v1.04,sierraforest,core
31
31
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
32
-
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core
32
+
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
33
33
GenuineIntel-6-55-[01234],v1.33,skylakex,core
34
34
GenuineIntel-6-86,v1.22,snowridgex,core
35
35
GenuineIntel-6-8[CD],v1.15,tigerlake,core
+250
tools/perf/pmu-events/arch/x86/skylake/cache.json
+250
tools/perf/pmu-events/arch/x86/skylake/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "L1D data line replacements",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x51",
5
6
"EventName": "L1D.REPLACEMENT",
6
7
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0x48",
14
14
"EventName": "L1D_PEND_MISS.FB_FULL",
15
15
"PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
···
19
17
},
20
18
{
21
19
"BriefDescription": "L1D miss outstandings duration in cycles",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0x48",
23
22
"EventName": "L1D_PEND_MISS.PENDING",
24
23
"PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
···
28
25
},
29
26
{
30
27
"BriefDescription": "Cycles with L1D load Misses outstanding.",
28
+
"Counter": "0,1,2,3",
31
29
"CounterMask": "1",
32
30
"EventCode": "0x48",
33
31
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
···
39
35
{
40
36
"AnyThread": "1",
41
37
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
38
+
"Counter": "0,1,2,3",
42
39
"CounterMask": "1",
43
40
"EventCode": "0x48",
44
41
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
···
48
43
},
49
44
{
50
45
"BriefDescription": "L2 cache lines filling L2",
46
+
"Counter": "0,1,2,3",
51
47
"EventCode": "0xF1",
52
48
"EventName": "L2_LINES_IN.ALL",
53
49
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
···
57
51
},
58
52
{
59
53
"BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
54
+
"Counter": "0,1,2,3",
60
55
"EventCode": "0xF2",
61
56
"EventName": "L2_LINES_OUT.NON_SILENT",
62
57
"SampleAfterValue": "200003",
···
65
58
},
66
59
{
67
60
"BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
61
+
"Counter": "0,1,2,3",
68
62
"EventCode": "0xF2",
69
63
"EventName": "L2_LINES_OUT.SILENT",
70
64
"SampleAfterValue": "200003",
···
73
65
},
74
66
{
75
67
"BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
68
+
"Counter": "0,1,2,3",
76
69
"EventCode": "0xF2",
77
70
"EventName": "L2_LINES_OUT.USELESS_HWPF",
78
71
"SampleAfterValue": "200003",
···
81
72
},
82
73
{
83
74
"BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
75
+
"Counter": "0,1,2,3",
84
76
"Deprecated": "1",
85
77
"EventCode": "0xF2",
86
78
"EventName": "L2_LINES_OUT.USELESS_PREF",
···
90
80
},
91
81
{
92
82
"BriefDescription": "L2 code requests",
83
+
"Counter": "0,1,2,3",
93
84
"EventCode": "0x24",
94
85
"EventName": "L2_RQSTS.ALL_CODE_RD",
95
86
"PublicDescription": "Counts the total number of L2 code requests.",
···
99
88
},
100
89
{
101
90
"BriefDescription": "Demand Data Read requests",
91
+
"Counter": "0,1,2,3",
102
92
"EventCode": "0x24",
103
93
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
104
94
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
···
108
96
},
109
97
{
110
98
"BriefDescription": "Demand requests that miss L2 cache",
99
+
"Counter": "0,1,2,3",
111
100
"EventCode": "0x24",
112
101
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
113
102
"PublicDescription": "Demand requests that miss L2 cache.",
···
117
104
},
118
105
{
119
106
"BriefDescription": "Demand requests to L2 cache",
107
+
"Counter": "0,1,2,3",
120
108
"EventCode": "0x24",
121
109
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
122
110
"PublicDescription": "Demand requests to L2 cache.",
···
126
112
},
127
113
{
128
114
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
115
+
"Counter": "0,1,2,3",
129
116
"EventCode": "0x24",
130
117
"EventName": "L2_RQSTS.ALL_PF",
131
118
"PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
···
135
120
},
136
121
{
137
122
"BriefDescription": "RFO requests to L2 cache",
123
+
"Counter": "0,1,2,3",
138
124
"EventCode": "0x24",
139
125
"EventName": "L2_RQSTS.ALL_RFO",
140
126
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
···
144
128
},
145
129
{
146
130
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
131
+
"Counter": "0,1,2,3",
147
132
"EventCode": "0x24",
148
133
"EventName": "L2_RQSTS.CODE_RD_HIT",
149
134
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
···
153
136
},
154
137
{
155
138
"BriefDescription": "L2 cache misses when fetching instructions",
139
+
"Counter": "0,1,2,3",
156
140
"EventCode": "0x24",
157
141
"EventName": "L2_RQSTS.CODE_RD_MISS",
158
142
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
···
162
144
},
163
145
{
164
146
"BriefDescription": "Demand Data Read requests that hit L2 cache",
147
+
"Counter": "0,1,2,3",
165
148
"EventCode": "0x24",
166
149
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
167
150
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
···
171
152
},
172
153
{
173
154
"BriefDescription": "Demand Data Read miss L2, no rejects",
155
+
"Counter": "0,1,2,3",
174
156
"EventCode": "0x24",
175
157
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
176
158
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
···
180
160
},
181
161
{
182
162
"BriefDescription": "All requests that miss L2 cache",
163
+
"Counter": "0,1,2,3",
183
164
"EventCode": "0x24",
184
165
"EventName": "L2_RQSTS.MISS",
185
166
"PublicDescription": "All requests that miss L2 cache.",
···
189
168
},
190
169
{
191
170
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
171
+
"Counter": "0,1,2,3",
192
172
"EventCode": "0x24",
193
173
"EventName": "L2_RQSTS.PF_HIT",
194
174
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
···
198
176
},
199
177
{
200
178
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
179
+
"Counter": "0,1,2,3",
201
180
"EventCode": "0x24",
202
181
"EventName": "L2_RQSTS.PF_MISS",
203
182
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
···
207
184
},
208
185
{
209
186
"BriefDescription": "All L2 requests",
187
+
"Counter": "0,1,2,3",
210
188
"EventCode": "0x24",
211
189
"EventName": "L2_RQSTS.REFERENCES",
212
190
"PublicDescription": "All L2 requests.",
···
216
192
},
217
193
{
218
194
"BriefDescription": "RFO requests that hit L2 cache",
195
+
"Counter": "0,1,2,3",
219
196
"EventCode": "0x24",
220
197
"EventName": "L2_RQSTS.RFO_HIT",
221
198
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
···
225
200
},
226
201
{
227
202
"BriefDescription": "RFO requests that miss L2 cache",
203
+
"Counter": "0,1,2,3",
228
204
"EventCode": "0x24",
229
205
"EventName": "L2_RQSTS.RFO_MISS",
230
206
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
···
234
208
},
235
209
{
236
210
"BriefDescription": "L2 writebacks that access L2 cache",
211
+
"Counter": "0,1,2,3",
237
212
"EventCode": "0xF0",
238
213
"EventName": "L2_TRANS.L2_WB",
239
214
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
···
243
216
},
244
217
{
245
218
"BriefDescription": "Core-originated cacheable demand requests missed L3",
219
+
"Counter": "0,1,2,3",
246
220
"Errata": "SKL057",
247
221
"EventCode": "0x2E",
248
222
"EventName": "LONGEST_LAT_CACHE.MISS",
···
253
225
},
254
226
{
255
227
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
228
+
"Counter": "0,1,2,3",
256
229
"Errata": "SKL057",
257
230
"EventCode": "0x2E",
258
231
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
···
263
234
},
264
235
{
265
236
"BriefDescription": "Retired load instructions.",
237
+
"Counter": "0,1,2,3",
266
238
"Data_LA": "1",
267
239
"EventCode": "0xD0",
268
240
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
···
274
244
},
275
245
{
276
246
"BriefDescription": "Retired store instructions.",
247
+
"Counter": "0,1,2,3",
277
248
"Data_LA": "1",
278
249
"EventCode": "0xD0",
279
250
"EventName": "MEM_INST_RETIRED.ALL_STORES",
···
285
254
},
286
255
{
287
256
"BriefDescription": "All retired memory instructions.",
257
+
"Counter": "0,1,2,3",
288
258
"Data_LA": "1",
289
259
"EventCode": "0xD0",
290
260
"EventName": "MEM_INST_RETIRED.ANY",
···
296
264
},
297
265
{
298
266
"BriefDescription": "Retired load instructions with locked access.",
267
+
"Counter": "0,1,2,3",
299
268
"Data_LA": "1",
300
269
"EventCode": "0xD0",
301
270
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
···
306
273
},
307
274
{
308
275
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
276
+
"Counter": "0,1,2,3",
309
277
"Data_LA": "1",
310
278
"EventCode": "0xD0",
311
279
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
···
317
283
},
318
284
{
319
285
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
286
+
"Counter": "0,1,2,3",
320
287
"Data_LA": "1",
321
288
"EventCode": "0xD0",
322
289
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
···
328
293
},
329
294
{
330
295
"BriefDescription": "Retired load instructions that miss the STLB.",
296
+
"Counter": "0,1,2,3",
331
297
"Data_LA": "1",
332
298
"EventCode": "0xD0",
333
299
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
···
339
303
},
340
304
{
341
305
"BriefDescription": "Retired store instructions that miss the STLB.",
306
+
"Counter": "0,1,2,3",
342
307
"Data_LA": "1",
343
308
"EventCode": "0xD0",
344
309
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
···
350
313
},
351
314
{
352
315
"BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
316
+
"Counter": "0,1,2,3",
353
317
"Data_LA": "1",
354
318
"EventCode": "0xD2",
355
319
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
···
361
323
},
362
324
{
363
325
"BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
326
+
"Counter": "0,1,2,3",
364
327
"Data_LA": "1",
365
328
"EventCode": "0xD2",
366
329
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
···
372
333
},
373
334
{
374
335
"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
336
+
"Counter": "0,1,2,3",
375
337
"Data_LA": "1",
376
338
"EventCode": "0xD2",
377
339
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
···
382
342
},
383
343
{
384
344
"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
345
+
"Counter": "0,1,2,3",
385
346
"Data_LA": "1",
386
347
"EventCode": "0xD2",
387
348
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
···
393
352
},
394
353
{
395
354
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
355
+
"Counter": "0,1,2,3",
396
356
"Data_LA": "1",
397
357
"EventCode": "0xD4",
398
358
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
···
403
361
},
404
362
{
405
363
"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
364
+
"Counter": "0,1,2,3",
406
365
"Data_LA": "1",
407
366
"EventCode": "0xD1",
408
367
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
···
414
371
},
415
372
{
416
373
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
374
+
"Counter": "0,1,2,3",
417
375
"Data_LA": "1",
418
376
"EventCode": "0xD1",
419
377
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
···
425
381
},
426
382
{
427
383
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
384
+
"Counter": "0,1,2,3",
428
385
"Data_LA": "1",
429
386
"EventCode": "0xD1",
430
387
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
···
436
391
},
437
392
{
438
393
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
394
+
"Counter": "0,1,2,3",
439
395
"Data_LA": "1",
440
396
"EventCode": "0xD1",
441
397
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
···
447
401
},
448
402
{
449
403
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
404
+
"Counter": "0,1,2,3",
450
405
"Data_LA": "1",
451
406
"EventCode": "0xD1",
452
407
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
···
458
411
},
459
412
{
460
413
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
414
+
"Counter": "0,1,2,3",
461
415
"Data_LA": "1",
462
416
"EventCode": "0xD1",
463
417
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
···
469
421
},
470
422
{
471
423
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
424
+
"Counter": "0,1,2,3",
472
425
"Data_LA": "1",
473
426
"EventCode": "0xD1",
474
427
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
···
480
431
},
481
432
{
482
433
"BriefDescription": "Demand and prefetch data reads",
434
+
"Counter": "0,1,2,3",
483
435
"EventCode": "0xB0",
484
436
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
485
437
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
···
489
439
},
490
440
{
491
441
"BriefDescription": "Any memory transaction that reached the SQ.",
442
+
"Counter": "0,1,2,3",
492
443
"EventCode": "0xB0",
493
444
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
494
445
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
···
498
447
},
499
448
{
500
449
"BriefDescription": "Cacheable and non-cacheable code read requests",
450
+
"Counter": "0,1,2,3",
501
451
"EventCode": "0xB0",
502
452
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
503
453
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
···
507
455
},
508
456
{
509
457
"BriefDescription": "Demand Data Read requests sent to uncore",
458
+
"Counter": "0,1,2,3",
510
459
"EventCode": "0xB0",
511
460
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
512
461
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
···
516
463
},
517
464
{
518
465
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
466
+
"Counter": "0,1,2,3",
519
467
"EventCode": "0xB0",
520
468
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
521
469
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
···
525
471
},
526
472
{
527
473
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
474
+
"Counter": "0,1,2,3",
528
475
"EventCode": "0xB2",
529
476
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
530
477
"PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
···
534
479
},
535
480
{
536
481
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
482
+
"Counter": "0,1,2,3",
537
483
"EventCode": "0x60",
538
484
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
539
485
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
···
543
487
},
544
488
{
545
489
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
490
+
"Counter": "0,1,2,3",
546
491
"CounterMask": "1",
547
492
"EventCode": "0x60",
548
493
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
···
553
496
},
554
497
{
555
498
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
499
+
"Counter": "0,1,2,3",
556
500
"CounterMask": "1",
557
501
"EventCode": "0x60",
558
502
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
···
563
505
},
564
506
{
565
507
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
508
+
"Counter": "0,1,2,3",
566
509
"CounterMask": "1",
567
510
"EventCode": "0x60",
568
511
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
···
573
514
},
574
515
{
575
516
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
517
+
"Counter": "0,1,2,3",
576
518
"CounterMask": "1",
577
519
"EventCode": "0x60",
578
520
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
···
583
523
},
584
524
{
585
525
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
526
+
"Counter": "0,1,2,3",
586
527
"EventCode": "0x60",
587
528
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
588
529
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
···
592
531
},
593
532
{
594
533
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
534
+
"Counter": "0,1,2,3",
595
535
"EventCode": "0x60",
596
536
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
597
537
"PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
···
601
539
},
602
540
{
603
541
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
542
+
"Counter": "0,1,2,3",
604
543
"CounterMask": "6",
605
544
"EventCode": "0x60",
606
545
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
···
610
547
},
611
548
{
612
549
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
550
+
"Counter": "0,1,2,3",
613
551
"EventCode": "0x60",
614
552
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
615
553
"PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
···
619
555
},
620
556
{
621
557
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
558
+
"Counter": "0,1,2,3",
622
559
"EventCode": "0xB7, 0xBB",
623
560
"EventName": "OFFCORE_RESPONSE",
624
561
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
···
628
563
},
629
564
{
630
565
"BriefDescription": "Counts all demand code reads have any response type.",
566
+
"Counter": "0,1,2,3",
631
567
"EventCode": "0xB7, 0xBB",
632
568
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
633
569
"MSRIndex": "0x1a6,0x1a7",
···
638
572
},
639
573
{
640
574
"BriefDescription": "Counts all demand code reads",
575
+
"Counter": "0,1,2,3",
641
576
"EventCode": "0xB7, 0xBB",
642
577
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
643
578
"MSRIndex": "0x1a6,0x1a7",
···
648
581
},
649
582
{
650
583
"BriefDescription": "Counts all demand code reads",
584
+
"Counter": "0,1,2,3",
651
585
"EventCode": "0xB7, 0xBB",
652
586
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
653
587
"MSRIndex": "0x1a6,0x1a7",
···
658
590
},
659
591
{
660
592
"BriefDescription": "Counts all demand code reads",
593
+
"Counter": "0,1,2,3",
661
594
"EventCode": "0xB7, 0xBB",
662
595
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
663
596
"MSRIndex": "0x1a6,0x1a7",
···
668
599
},
669
600
{
670
601
"BriefDescription": "Counts all demand code reads",
602
+
"Counter": "0,1,2,3",
671
603
"EventCode": "0xB7, 0xBB",
672
604
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
673
605
"MSRIndex": "0x1a6,0x1a7",
···
678
608
},
679
609
{
680
610
"BriefDescription": "Counts all demand code reads",
611
+
"Counter": "0,1,2,3",
681
612
"EventCode": "0xB7, 0xBB",
682
613
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
683
614
"MSRIndex": "0x1a6,0x1a7",
···
688
617
},
689
618
{
690
619
"BriefDescription": "Counts all demand code reads",
620
+
"Counter": "0,1,2,3",
691
621
"EventCode": "0xB7, 0xBB",
692
622
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
693
623
"MSRIndex": "0x1a6,0x1a7",
···
698
626
},
699
627
{
700
628
"BriefDescription": "Counts all demand code reads",
629
+
"Counter": "0,1,2,3",
701
630
"EventCode": "0xB7, 0xBB",
702
631
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT",
703
632
"MSRIndex": "0x1a6,0x1a7",
···
708
635
},
709
636
{
710
637
"BriefDescription": "Counts all demand code reads",
638
+
"Counter": "0,1,2,3",
711
639
"EventCode": "0xB7, 0xBB",
712
640
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
713
641
"MSRIndex": "0x1a6,0x1a7",
···
718
644
},
719
645
{
720
646
"BriefDescription": "Counts all demand code reads",
647
+
"Counter": "0,1,2,3",
721
648
"EventCode": "0xB7, 0xBB",
722
649
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM",
723
650
"MSRIndex": "0x1a6,0x1a7",
···
728
653
},
729
654
{
730
655
"BriefDescription": "Counts all demand code reads",
656
+
"Counter": "0,1,2,3",
731
657
"EventCode": "0xB7, 0xBB",
732
658
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
733
659
"MSRIndex": "0x1a6,0x1a7",
···
738
662
},
739
663
{
740
664
"BriefDescription": "Counts all demand code reads",
665
+
"Counter": "0,1,2,3",
741
666
"EventCode": "0xB7, 0xBB",
742
667
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
743
668
"MSRIndex": "0x1a6,0x1a7",
···
748
671
},
749
672
{
750
673
"BriefDescription": "Counts all demand code reads",
674
+
"Counter": "0,1,2,3",
751
675
"EventCode": "0xB7, 0xBB",
752
676
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
753
677
"MSRIndex": "0x1a6,0x1a7",
···
758
680
},
759
681
{
760
682
"BriefDescription": "Counts all demand code reads",
683
+
"Counter": "0,1,2,3",
761
684
"EventCode": "0xB7, 0xBB",
762
685
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
763
686
"MSRIndex": "0x1a6,0x1a7",
···
768
689
},
769
690
{
770
691
"BriefDescription": "Counts all demand code reads",
692
+
"Counter": "0,1,2,3",
771
693
"EventCode": "0xB7, 0xBB",
772
694
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT",
773
695
"MSRIndex": "0x1a6,0x1a7",
···
778
698
},
779
699
{
780
700
"BriefDescription": "Counts all demand code reads",
701
+
"Counter": "0,1,2,3",
781
702
"EventCode": "0xB7, 0xBB",
782
703
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
783
704
"MSRIndex": "0x1a6,0x1a7",
···
788
707
},
789
708
{
790
709
"BriefDescription": "Counts all demand code reads",
710
+
"Counter": "0,1,2,3",
791
711
"EventCode": "0xB7, 0xBB",
792
712
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM",
793
713
"MSRIndex": "0x1a6,0x1a7",
···
798
716
},
799
717
{
800
718
"BriefDescription": "Counts all demand code reads",
719
+
"Counter": "0,1,2,3",
801
720
"EventCode": "0xB7, 0xBB",
802
721
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
803
722
"MSRIndex": "0x1a6,0x1a7",
···
808
725
},
809
726
{
810
727
"BriefDescription": "Counts all demand code reads",
728
+
"Counter": "0,1,2,3",
811
729
"EventCode": "0xB7, 0xBB",
812
730
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
813
731
"MSRIndex": "0x1a6,0x1a7",
···
818
734
},
819
735
{
820
736
"BriefDescription": "Counts all demand code reads",
737
+
"Counter": "0,1,2,3",
821
738
"EventCode": "0xB7, 0xBB",
822
739
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
823
740
"MSRIndex": "0x1a6,0x1a7",
···
828
743
},
829
744
{
830
745
"BriefDescription": "Counts all demand code reads",
746
+
"Counter": "0,1,2,3",
831
747
"EventCode": "0xB7, 0xBB",
832
748
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
833
749
"MSRIndex": "0x1a6,0x1a7",
···
838
752
},
839
753
{
840
754
"BriefDescription": "Counts all demand code reads",
755
+
"Counter": "0,1,2,3",
841
756
"EventCode": "0xB7, 0xBB",
842
757
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT",
843
758
"MSRIndex": "0x1a6,0x1a7",
···
848
761
},
849
762
{
850
763
"BriefDescription": "Counts all demand code reads",
764
+
"Counter": "0,1,2,3",
851
765
"EventCode": "0xB7, 0xBB",
852
766
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
853
767
"MSRIndex": "0x1a6,0x1a7",
···
858
770
},
859
771
{
860
772
"BriefDescription": "Counts all demand code reads",
773
+
"Counter": "0,1,2,3",
861
774
"EventCode": "0xB7, 0xBB",
862
775
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM",
863
776
"MSRIndex": "0x1a6,0x1a7",
···
868
779
},
869
780
{
870
781
"BriefDescription": "Counts all demand code reads",
782
+
"Counter": "0,1,2,3",
871
783
"EventCode": "0xB7, 0xBB",
872
784
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
873
785
"MSRIndex": "0x1a6,0x1a7",
···
878
788
},
879
789
{
880
790
"BriefDescription": "Counts all demand code reads",
791
+
"Counter": "0,1,2,3",
881
792
"EventCode": "0xB7, 0xBB",
882
793
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
883
794
"MSRIndex": "0x1a6,0x1a7",
···
888
797
},
889
798
{
890
799
"BriefDescription": "Counts all demand code reads",
800
+
"Counter": "0,1,2,3",
891
801
"EventCode": "0xB7, 0xBB",
892
802
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
893
803
"MSRIndex": "0x1a6,0x1a7",
···
898
806
},
899
807
{
900
808
"BriefDescription": "Counts all demand code reads",
809
+
"Counter": "0,1,2,3",
901
810
"EventCode": "0xB7, 0xBB",
902
811
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
903
812
"MSRIndex": "0x1a6,0x1a7",
···
908
815
},
909
816
{
910
817
"BriefDescription": "Counts all demand code reads",
818
+
"Counter": "0,1,2,3",
911
819
"EventCode": "0xB7, 0xBB",
912
820
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT",
913
821
"MSRIndex": "0x1a6,0x1a7",
···
918
824
},
919
825
{
920
826
"BriefDescription": "Counts all demand code reads",
827
+
"Counter": "0,1,2,3",
921
828
"EventCode": "0xB7, 0xBB",
922
829
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
923
830
"MSRIndex": "0x1a6,0x1a7",
···
928
833
},
929
834
{
930
835
"BriefDescription": "Counts all demand code reads",
836
+
"Counter": "0,1,2,3",
931
837
"EventCode": "0xB7, 0xBB",
932
838
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
933
839
"MSRIndex": "0x1a6,0x1a7",
···
938
842
},
939
843
{
940
844
"BriefDescription": "Counts all demand code reads",
845
+
"Counter": "0,1,2,3",
941
846
"EventCode": "0xB7, 0xBB",
942
847
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
943
848
"MSRIndex": "0x1a6,0x1a7",
···
948
851
},
949
852
{
950
853
"BriefDescription": "Counts all demand code reads",
854
+
"Counter": "0,1,2,3",
951
855
"EventCode": "0xB7, 0xBB",
952
856
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
953
857
"MSRIndex": "0x1a6,0x1a7",
···
958
860
},
959
861
{
960
862
"BriefDescription": "Counts all demand code reads",
863
+
"Counter": "0,1,2,3",
961
864
"EventCode": "0xB7, 0xBB",
962
865
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
963
866
"MSRIndex": "0x1a6,0x1a7",
···
968
869
},
969
870
{
970
871
"BriefDescription": "Counts all demand code reads",
872
+
"Counter": "0,1,2,3",
971
873
"EventCode": "0xB7, 0xBB",
972
874
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
973
875
"MSRIndex": "0x1a6,0x1a7",
···
978
878
},
979
879
{
980
880
"BriefDescription": "Counts all demand code reads",
881
+
"Counter": "0,1,2,3",
981
882
"EventCode": "0xB7, 0xBB",
982
883
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT",
983
884
"MSRIndex": "0x1a6,0x1a7",
···
988
887
},
989
888
{
990
889
"BriefDescription": "Counts all demand code reads",
890
+
"Counter": "0,1,2,3",
991
891
"EventCode": "0xB7, 0xBB",
992
892
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
993
893
"MSRIndex": "0x1a6,0x1a7",
···
998
896
},
999
897
{
1000
898
"BriefDescription": "Counts all demand code reads",
899
+
"Counter": "0,1,2,3",
1001
900
"EventCode": "0xB7, 0xBB",
1002
901
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM",
1003
902
"MSRIndex": "0x1a6,0x1a7",
···
1008
905
},
1009
906
{
1010
907
"BriefDescription": "Counts all demand code reads",
908
+
"Counter": "0,1,2,3",
1011
909
"EventCode": "0xB7, 0xBB",
1012
910
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1013
911
"MSRIndex": "0x1a6,0x1a7",
···
1018
914
},
1019
915
{
1020
916
"BriefDescription": "Counts all demand code reads",
917
+
"Counter": "0,1,2,3",
1021
918
"EventCode": "0xB7, 0xBB",
1022
919
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
1023
920
"MSRIndex": "0x1a6,0x1a7",
···
1028
923
},
1029
924
{
1030
925
"BriefDescription": "Counts all demand code reads",
926
+
"Counter": "0,1,2,3",
1031
927
"EventCode": "0xB7, 0xBB",
1032
928
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
1033
929
"MSRIndex": "0x1a6,0x1a7",
···
1038
932
},
1039
933
{
1040
934
"BriefDescription": "Counts all demand code reads",
935
+
"Counter": "0,1,2,3",
1041
936
"EventCode": "0xB7, 0xBB",
1042
937
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1043
938
"MSRIndex": "0x1a6,0x1a7",
···
1048
941
},
1049
942
{
1050
943
"BriefDescription": "Counts all demand code reads",
944
+
"Counter": "0,1,2,3",
1051
945
"EventCode": "0xB7, 0xBB",
1052
946
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT",
1053
947
"MSRIndex": "0x1a6,0x1a7",
···
1058
950
},
1059
951
{
1060
952
"BriefDescription": "Counts demand data reads have any response type.",
953
+
"Counter": "0,1,2,3",
1061
954
"EventCode": "0xB7, 0xBB",
1062
955
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
1063
956
"MSRIndex": "0x1a6,0x1a7",
···
1068
959
},
1069
960
{
1070
961
"BriefDescription": "Counts demand data reads",
962
+
"Counter": "0,1,2,3",
1071
963
"EventCode": "0xB7, 0xBB",
1072
964
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
1073
965
"MSRIndex": "0x1a6,0x1a7",
···
1078
968
},
1079
969
{
1080
970
"BriefDescription": "Counts demand data reads",
971
+
"Counter": "0,1,2,3",
1081
972
"EventCode": "0xB7, 0xBB",
1082
973
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
1083
974
"MSRIndex": "0x1a6,0x1a7",
···
1088
977
},
1089
978
{
1090
979
"BriefDescription": "Counts demand data reads",
980
+
"Counter": "0,1,2,3",
1091
981
"EventCode": "0xB7, 0xBB",
1092
982
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
1093
983
"MSRIndex": "0x1a6,0x1a7",
···
1098
986
},
1099
987
{
1100
988
"BriefDescription": "Counts demand data reads",
989
+
"Counter": "0,1,2,3",
1101
990
"EventCode": "0xB7, 0xBB",
1102
991
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
1103
992
"MSRIndex": "0x1a6,0x1a7",
···
1108
995
},
1109
996
{
1110
997
"BriefDescription": "Counts demand data reads",
998
+
"Counter": "0,1,2,3",
1111
999
"EventCode": "0xB7, 0xBB",
1112
1000
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
1113
1001
"MSRIndex": "0x1a6,0x1a7",
···
1118
1004
},
1119
1005
{
1120
1006
"BriefDescription": "Counts demand data reads",
1007
+
"Counter": "0,1,2,3",
1121
1008
"EventCode": "0xB7, 0xBB",
1122
1009
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
1123
1010
"MSRIndex": "0x1a6,0x1a7",
···
1128
1013
},
1129
1014
{
1130
1015
"BriefDescription": "Counts demand data reads",
1016
+
"Counter": "0,1,2,3",
1131
1017
"EventCode": "0xB7, 0xBB",
1132
1018
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT",
1133
1019
"MSRIndex": "0x1a6,0x1a7",
···
1138
1022
},
1139
1023
{
1140
1024
"BriefDescription": "Counts demand data reads",
1025
+
"Counter": "0,1,2,3",
1141
1026
"EventCode": "0xB7, 0xBB",
1142
1027
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
1143
1028
"MSRIndex": "0x1a6,0x1a7",
···
1148
1031
},
1149
1032
{
1150
1033
"BriefDescription": "Counts demand data reads",
1034
+
"Counter": "0,1,2,3",
1151
1035
"EventCode": "0xB7, 0xBB",
1152
1036
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM",
1153
1037
"MSRIndex": "0x1a6,0x1a7",
···
1158
1040
},
1159
1041
{
1160
1042
"BriefDescription": "Counts demand data reads",
1043
+
"Counter": "0,1,2,3",
1161
1044
"EventCode": "0xB7, 0xBB",
1162
1045
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD",
1163
1046
"MSRIndex": "0x1a6,0x1a7",
···
1168
1049
},
1169
1050
{
1170
1051
"BriefDescription": "Counts demand data reads",
1052
+
"Counter": "0,1,2,3",
1171
1053
"EventCode": "0xB7, 0xBB",
1172
1054
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
1173
1055
"MSRIndex": "0x1a6,0x1a7",
···
1178
1058
},
1179
1059
{
1180
1060
"BriefDescription": "Counts demand data reads",
1061
+
"Counter": "0,1,2,3",
1181
1062
"EventCode": "0xB7, 0xBB",
1182
1063
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
1183
1064
"MSRIndex": "0x1a6,0x1a7",
···
1188
1067
},
1189
1068
{
1190
1069
"BriefDescription": "Counts demand data reads",
1070
+
"Counter": "0,1,2,3",
1191
1071
"EventCode": "0xB7, 0xBB",
1192
1072
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED",
1193
1073
"MSRIndex": "0x1a6,0x1a7",
···
1198
1076
},
1199
1077
{
1200
1078
"BriefDescription": "Counts demand data reads",
1079
+
"Counter": "0,1,2,3",
1201
1080
"EventCode": "0xB7, 0xBB",
1202
1081
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT",
1203
1082
"MSRIndex": "0x1a6,0x1a7",
···
1208
1085
},
1209
1086
{
1210
1087
"BriefDescription": "Counts demand data reads",
1088
+
"Counter": "0,1,2,3",
1211
1089
"EventCode": "0xB7, 0xBB",
1212
1090
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
1213
1091
"MSRIndex": "0x1a6,0x1a7",
···
1218
1094
},
1219
1095
{
1220
1096
"BriefDescription": "Counts demand data reads",
1097
+
"Counter": "0,1,2,3",
1221
1098
"EventCode": "0xB7, 0xBB",
1222
1099
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM",
1223
1100
"MSRIndex": "0x1a6,0x1a7",
···
1228
1103
},
1229
1104
{
1230
1105
"BriefDescription": "Counts demand data reads",
1106
+
"Counter": "0,1,2,3",
1231
1107
"EventCode": "0xB7, 0xBB",
1232
1108
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD",
1233
1109
"MSRIndex": "0x1a6,0x1a7",
···
1238
1112
},
1239
1113
{
1240
1114
"BriefDescription": "Counts demand data reads",
1115
+
"Counter": "0,1,2,3",
1241
1116
"EventCode": "0xB7, 0xBB",
1242
1117
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
1243
1118
"MSRIndex": "0x1a6,0x1a7",
···
1248
1121
},
1249
1122
{
1250
1123
"BriefDescription": "Counts demand data reads",
1124
+
"Counter": "0,1,2,3",
1251
1125
"EventCode": "0xB7, 0xBB",
1252
1126
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
1253
1127
"MSRIndex": "0x1a6,0x1a7",
···
1258
1130
},
1259
1131
{
1260
1132
"BriefDescription": "Counts demand data reads",
1133
+
"Counter": "0,1,2,3",
1261
1134
"EventCode": "0xB7, 0xBB",
1262
1135
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED",
1263
1136
"MSRIndex": "0x1a6,0x1a7",
···
1268
1139
},
1269
1140
{
1270
1141
"BriefDescription": "Counts demand data reads",
1142
+
"Counter": "0,1,2,3",
1271
1143
"EventCode": "0xB7, 0xBB",
1272
1144
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT",
1273
1145
"MSRIndex": "0x1a6,0x1a7",
···
1278
1148
},
1279
1149
{
1280
1150
"BriefDescription": "Counts demand data reads",
1151
+
"Counter": "0,1,2,3",
1281
1152
"EventCode": "0xB7, 0xBB",
1282
1153
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
1283
1154
"MSRIndex": "0x1a6,0x1a7",
···
1288
1157
},
1289
1158
{
1290
1159
"BriefDescription": "Counts demand data reads",
1160
+
"Counter": "0,1,2,3",
1291
1161
"EventCode": "0xB7, 0xBB",
1292
1162
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM",
1293
1163
"MSRIndex": "0x1a6,0x1a7",
···
1298
1166
},
1299
1167
{
1300
1168
"BriefDescription": "Counts demand data reads",
1169
+
"Counter": "0,1,2,3",
1301
1170
"EventCode": "0xB7, 0xBB",
1302
1171
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD",
1303
1172
"MSRIndex": "0x1a6,0x1a7",
···
1308
1175
},
1309
1176
{
1310
1177
"BriefDescription": "Counts demand data reads",
1178
+
"Counter": "0,1,2,3",
1311
1179
"EventCode": "0xB7, 0xBB",
1312
1180
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
1313
1181
"MSRIndex": "0x1a6,0x1a7",
···
1318
1184
},
1319
1185
{
1320
1186
"BriefDescription": "Counts demand data reads",
1187
+
"Counter": "0,1,2,3",
1321
1188
"EventCode": "0xB7, 0xBB",
1322
1189
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
1323
1190
"MSRIndex": "0x1a6,0x1a7",
···
1328
1193
},
1329
1194
{
1330
1195
"BriefDescription": "Counts demand data reads",
1196
+
"Counter": "0,1,2,3",
1331
1197
"EventCode": "0xB7, 0xBB",
1332
1198
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED",
1333
1199
"MSRIndex": "0x1a6,0x1a7",
···
1338
1202
},
1339
1203
{
1340
1204
"BriefDescription": "Counts demand data reads",
1205
+
"Counter": "0,1,2,3",
1341
1206
"EventCode": "0xB7, 0xBB",
1342
1207
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT",
1343
1208
"MSRIndex": "0x1a6,0x1a7",
···
1348
1211
},
1349
1212
{
1350
1213
"BriefDescription": "Counts demand data reads",
1214
+
"Counter": "0,1,2,3",
1351
1215
"EventCode": "0xB7, 0xBB",
1352
1216
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
1353
1217
"MSRIndex": "0x1a6,0x1a7",
···
1358
1220
},
1359
1221
{
1360
1222
"BriefDescription": "Counts demand data reads",
1223
+
"Counter": "0,1,2,3",
1361
1224
"EventCode": "0xB7, 0xBB",
1362
1225
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
1363
1226
"MSRIndex": "0x1a6,0x1a7",
···
1368
1229
},
1369
1230
{
1370
1231
"BriefDescription": "Counts demand data reads",
1232
+
"Counter": "0,1,2,3",
1371
1233
"EventCode": "0xB7, 0xBB",
1372
1234
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
1373
1235
"MSRIndex": "0x1a6,0x1a7",
···
1378
1238
},
1379
1239
{
1380
1240
"BriefDescription": "Counts demand data reads",
1241
+
"Counter": "0,1,2,3",
1381
1242
"EventCode": "0xB7, 0xBB",
1382
1243
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
1383
1244
"MSRIndex": "0x1a6,0x1a7",
···
1388
1247
},
1389
1248
{
1390
1249
"BriefDescription": "Counts demand data reads",
1250
+
"Counter": "0,1,2,3",
1391
1251
"EventCode": "0xB7, 0xBB",
1392
1252
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
1393
1253
"MSRIndex": "0x1a6,0x1a7",
···
1398
1256
},
1399
1257
{
1400
1258
"BriefDescription": "Counts demand data reads",
1259
+
"Counter": "0,1,2,3",
1401
1260
"EventCode": "0xB7, 0xBB",
1402
1261
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
1403
1262
"MSRIndex": "0x1a6,0x1a7",
···
1408
1265
},
1409
1266
{
1410
1267
"BriefDescription": "Counts demand data reads",
1268
+
"Counter": "0,1,2,3",
1411
1269
"EventCode": "0xB7, 0xBB",
1412
1270
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT",
1413
1271
"MSRIndex": "0x1a6,0x1a7",
···
1418
1274
},
1419
1275
{
1420
1276
"BriefDescription": "Counts demand data reads",
1277
+
"Counter": "0,1,2,3",
1421
1278
"EventCode": "0xB7, 0xBB",
1422
1279
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
1423
1280
"MSRIndex": "0x1a6,0x1a7",
···
1428
1283
},
1429
1284
{
1430
1285
"BriefDescription": "Counts demand data reads",
1286
+
"Counter": "0,1,2,3",
1431
1287
"EventCode": "0xB7, 0xBB",
1432
1288
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
1433
1289
"MSRIndex": "0x1a6,0x1a7",
···
1438
1292
},
1439
1293
{
1440
1294
"BriefDescription": "Counts demand data reads",
1295
+
"Counter": "0,1,2,3",
1441
1296
"EventCode": "0xB7, 0xBB",
1442
1297
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1443
1298
"MSRIndex": "0x1a6,0x1a7",
···
1448
1301
},
1449
1302
{
1450
1303
"BriefDescription": "Counts demand data reads",
1304
+
"Counter": "0,1,2,3",
1451
1305
"EventCode": "0xB7, 0xBB",
1452
1306
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
1453
1307
"MSRIndex": "0x1a6,0x1a7",
···
1458
1310
},
1459
1311
{
1460
1312
"BriefDescription": "Counts demand data reads",
1313
+
"Counter": "0,1,2,3",
1461
1314
"EventCode": "0xB7, 0xBB",
1462
1315
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
1463
1316
"MSRIndex": "0x1a6,0x1a7",
···
1468
1319
},
1469
1320
{
1470
1321
"BriefDescription": "Counts demand data reads",
1322
+
"Counter": "0,1,2,3",
1471
1323
"EventCode": "0xB7, 0xBB",
1472
1324
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1473
1325
"MSRIndex": "0x1a6,0x1a7",
···
1478
1328
},
1479
1329
{
1480
1330
"BriefDescription": "Counts demand data reads",
1331
+
"Counter": "0,1,2,3",
1481
1332
"EventCode": "0xB7, 0xBB",
1482
1333
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT",
1483
1334
"MSRIndex": "0x1a6,0x1a7",
···
1488
1337
},
1489
1338
{
1490
1339
"BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
1340
+
"Counter": "0,1,2,3",
1491
1341
"EventCode": "0xB7, 0xBB",
1492
1342
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
1493
1343
"MSRIndex": "0x1a6,0x1a7",
···
1498
1346
},
1499
1347
{
1500
1348
"BriefDescription": "Counts all demand data writes (RFOs)",
1349
+
"Counter": "0,1,2,3",
1501
1350
"EventCode": "0xB7, 0xBB",
1502
1351
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
1503
1352
"MSRIndex": "0x1a6,0x1a7",
···
1508
1355
},
1509
1356
{
1510
1357
"BriefDescription": "Counts all demand data writes (RFOs)",
1358
+
"Counter": "0,1,2,3",
1511
1359
"EventCode": "0xB7, 0xBB",
1512
1360
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
1513
1361
"MSRIndex": "0x1a6,0x1a7",
···
1518
1364
},
1519
1365
{
1520
1366
"BriefDescription": "Counts all demand data writes (RFOs)",
1367
+
"Counter": "0,1,2,3",
1521
1368
"EventCode": "0xB7, 0xBB",
1522
1369
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
1523
1370
"MSRIndex": "0x1a6,0x1a7",
···
1528
1373
},
1529
1374
{
1530
1375
"BriefDescription": "Counts all demand data writes (RFOs)",
1376
+
"Counter": "0,1,2,3",
1531
1377
"EventCode": "0xB7, 0xBB",
1532
1378
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
1533
1379
"MSRIndex": "0x1a6,0x1a7",
···
1538
1382
},
1539
1383
{
1540
1384
"BriefDescription": "Counts all demand data writes (RFOs)",
1385
+
"Counter": "0,1,2,3",
1541
1386
"EventCode": "0xB7, 0xBB",
1542
1387
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
1543
1388
"MSRIndex": "0x1a6,0x1a7",
···
1548
1391
},
1549
1392
{
1550
1393
"BriefDescription": "Counts all demand data writes (RFOs)",
1394
+
"Counter": "0,1,2,3",
1551
1395
"EventCode": "0xB7, 0xBB",
1552
1396
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
1553
1397
"MSRIndex": "0x1a6,0x1a7",
···
1558
1400
},
1559
1401
{
1560
1402
"BriefDescription": "Counts all demand data writes (RFOs)",
1403
+
"Counter": "0,1,2,3",
1561
1404
"EventCode": "0xB7, 0xBB",
1562
1405
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT",
1563
1406
"MSRIndex": "0x1a6,0x1a7",
···
1568
1409
},
1569
1410
{
1570
1411
"BriefDescription": "Counts all demand data writes (RFOs)",
1412
+
"Counter": "0,1,2,3",
1571
1413
"EventCode": "0xB7, 0xBB",
1572
1414
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
1573
1415
"MSRIndex": "0x1a6,0x1a7",
···
1578
1418
},
1579
1419
{
1580
1420
"BriefDescription": "Counts all demand data writes (RFOs)",
1421
+
"Counter": "0,1,2,3",
1581
1422
"EventCode": "0xB7, 0xBB",
1582
1423
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM",
1583
1424
"MSRIndex": "0x1a6,0x1a7",
···
1588
1427
},
1589
1428
{
1590
1429
"BriefDescription": "Counts all demand data writes (RFOs)",
1430
+
"Counter": "0,1,2,3",
1591
1431
"EventCode": "0xB7, 0xBB",
1592
1432
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD",
1593
1433
"MSRIndex": "0x1a6,0x1a7",
···
1598
1436
},
1599
1437
{
1600
1438
"BriefDescription": "Counts all demand data writes (RFOs)",
1439
+
"Counter": "0,1,2,3",
1601
1440
"EventCode": "0xB7, 0xBB",
1602
1441
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
1603
1442
"MSRIndex": "0x1a6,0x1a7",
···
1608
1445
},
1609
1446
{
1610
1447
"BriefDescription": "Counts all demand data writes (RFOs)",
1448
+
"Counter": "0,1,2,3",
1611
1449
"EventCode": "0xB7, 0xBB",
1612
1450
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
1613
1451
"MSRIndex": "0x1a6,0x1a7",
···
1618
1454
},
1619
1455
{
1620
1456
"BriefDescription": "Counts all demand data writes (RFOs)",
1457
+
"Counter": "0,1,2,3",
1621
1458
"EventCode": "0xB7, 0xBB",
1622
1459
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED",
1623
1460
"MSRIndex": "0x1a6,0x1a7",
···
1628
1463
},
1629
1464
{
1630
1465
"BriefDescription": "Counts all demand data writes (RFOs)",
1466
+
"Counter": "0,1,2,3",
1631
1467
"EventCode": "0xB7, 0xBB",
1632
1468
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT",
1633
1469
"MSRIndex": "0x1a6,0x1a7",
···
1638
1472
},
1639
1473
{
1640
1474
"BriefDescription": "Counts all demand data writes (RFOs)",
1475
+
"Counter": "0,1,2,3",
1641
1476
"EventCode": "0xB7, 0xBB",
1642
1477
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
1643
1478
"MSRIndex": "0x1a6,0x1a7",
···
1648
1481
},
1649
1482
{
1650
1483
"BriefDescription": "Counts all demand data writes (RFOs)",
1484
+
"Counter": "0,1,2,3",
1651
1485
"EventCode": "0xB7, 0xBB",
1652
1486
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM",
1653
1487
"MSRIndex": "0x1a6,0x1a7",
···
1658
1490
},
1659
1491
{
1660
1492
"BriefDescription": "Counts all demand data writes (RFOs)",
1493
+
"Counter": "0,1,2,3",
1661
1494
"EventCode": "0xB7, 0xBB",
1662
1495
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD",
1663
1496
"MSRIndex": "0x1a6,0x1a7",
···
1668
1499
},
1669
1500
{
1670
1501
"BriefDescription": "Counts all demand data writes (RFOs)",
1502
+
"Counter": "0,1,2,3",
1671
1503
"EventCode": "0xB7, 0xBB",
1672
1504
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
1673
1505
"MSRIndex": "0x1a6,0x1a7",
···
1678
1508
},
1679
1509
{
1680
1510
"BriefDescription": "Counts all demand data writes (RFOs)",
1511
+
"Counter": "0,1,2,3",
1681
1512
"EventCode": "0xB7, 0xBB",
1682
1513
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
1683
1514
"MSRIndex": "0x1a6,0x1a7",
···
1688
1517
},
1689
1518
{
1690
1519
"BriefDescription": "Counts all demand data writes (RFOs)",
1520
+
"Counter": "0,1,2,3",
1691
1521
"EventCode": "0xB7, 0xBB",
1692
1522
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED",
1693
1523
"MSRIndex": "0x1a6,0x1a7",
···
1698
1526
},
1699
1527
{
1700
1528
"BriefDescription": "Counts all demand data writes (RFOs)",
1529
+
"Counter": "0,1,2,3",
1701
1530
"EventCode": "0xB7, 0xBB",
1702
1531
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT",
1703
1532
"MSRIndex": "0x1a6,0x1a7",
···
1708
1535
},
1709
1536
{
1710
1537
"BriefDescription": "Counts all demand data writes (RFOs)",
1538
+
"Counter": "0,1,2,3",
1711
1539
"EventCode": "0xB7, 0xBB",
1712
1540
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
1713
1541
"MSRIndex": "0x1a6,0x1a7",
···
1718
1544
},
1719
1545
{
1720
1546
"BriefDescription": "Counts all demand data writes (RFOs)",
1547
+
"Counter": "0,1,2,3",
1721
1548
"EventCode": "0xB7, 0xBB",
1722
1549
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM",
1723
1550
"MSRIndex": "0x1a6,0x1a7",
···
1728
1553
},
1729
1554
{
1730
1555
"BriefDescription": "Counts all demand data writes (RFOs)",
1556
+
"Counter": "0,1,2,3",
1731
1557
"EventCode": "0xB7, 0xBB",
1732
1558
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD",
1733
1559
"MSRIndex": "0x1a6,0x1a7",
···
1738
1562
},
1739
1563
{
1740
1564
"BriefDescription": "Counts all demand data writes (RFOs)",
1565
+
"Counter": "0,1,2,3",
1741
1566
"EventCode": "0xB7, 0xBB",
1742
1567
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
1743
1568
"MSRIndex": "0x1a6,0x1a7",
···
1748
1571
},
1749
1572
{
1750
1573
"BriefDescription": "Counts all demand data writes (RFOs)",
1574
+
"Counter": "0,1,2,3",
1751
1575
"EventCode": "0xB7, 0xBB",
1752
1576
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
1753
1577
"MSRIndex": "0x1a6,0x1a7",
···
1758
1580
},
1759
1581
{
1760
1582
"BriefDescription": "Counts all demand data writes (RFOs)",
1583
+
"Counter": "0,1,2,3",
1761
1584
"EventCode": "0xB7, 0xBB",
1762
1585
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED",
1763
1586
"MSRIndex": "0x1a6,0x1a7",
···
1768
1589
},
1769
1590
{
1770
1591
"BriefDescription": "Counts all demand data writes (RFOs)",
1592
+
"Counter": "0,1,2,3",
1771
1593
"EventCode": "0xB7, 0xBB",
1772
1594
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT",
1773
1595
"MSRIndex": "0x1a6,0x1a7",
···
1778
1598
},
1779
1599
{
1780
1600
"BriefDescription": "Counts all demand data writes (RFOs)",
1601
+
"Counter": "0,1,2,3",
1781
1602
"EventCode": "0xB7, 0xBB",
1782
1603
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP",
1783
1604
"MSRIndex": "0x1a6,0x1a7",
···
1788
1607
},
1789
1608
{
1790
1609
"BriefDescription": "Counts all demand data writes (RFOs)",
1610
+
"Counter": "0,1,2,3",
1791
1611
"EventCode": "0xB7, 0xBB",
1792
1612
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM",
1793
1613
"MSRIndex": "0x1a6,0x1a7",
···
1798
1616
},
1799
1617
{
1800
1618
"BriefDescription": "Counts all demand data writes (RFOs)",
1619
+
"Counter": "0,1,2,3",
1801
1620
"EventCode": "0xB7, 0xBB",
1802
1621
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
1803
1622
"MSRIndex": "0x1a6,0x1a7",
···
1808
1625
},
1809
1626
{
1810
1627
"BriefDescription": "Counts all demand data writes (RFOs)",
1628
+
"Counter": "0,1,2,3",
1811
1629
"EventCode": "0xB7, 0xBB",
1812
1630
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS",
1813
1631
"MSRIndex": "0x1a6,0x1a7",
···
1818
1634
},
1819
1635
{
1820
1636
"BriefDescription": "Counts all demand data writes (RFOs)",
1637
+
"Counter": "0,1,2,3",
1821
1638
"EventCode": "0xB7, 0xBB",
1822
1639
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE",
1823
1640
"MSRIndex": "0x1a6,0x1a7",
···
1828
1643
},
1829
1644
{
1830
1645
"BriefDescription": "Counts all demand data writes (RFOs)",
1646
+
"Counter": "0,1,2,3",
1831
1647
"EventCode": "0xB7, 0xBB",
1832
1648
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
1833
1649
"MSRIndex": "0x1a6,0x1a7",
···
1838
1652
},
1839
1653
{
1840
1654
"BriefDescription": "Counts all demand data writes (RFOs)",
1655
+
"Counter": "0,1,2,3",
1841
1656
"EventCode": "0xB7, 0xBB",
1842
1657
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT",
1843
1658
"MSRIndex": "0x1a6,0x1a7",
···
1848
1661
},
1849
1662
{
1850
1663
"BriefDescription": "Counts all demand data writes (RFOs)",
1664
+
"Counter": "0,1,2,3",
1851
1665
"EventCode": "0xB7, 0xBB",
1852
1666
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
1853
1667
"MSRIndex": "0x1a6,0x1a7",
···
1858
1670
},
1859
1671
{
1860
1672
"BriefDescription": "Counts all demand data writes (RFOs)",
1673
+
"Counter": "0,1,2,3",
1861
1674
"EventCode": "0xB7, 0xBB",
1862
1675
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM",
1863
1676
"MSRIndex": "0x1a6,0x1a7",
···
1868
1679
},
1869
1680
{
1870
1681
"BriefDescription": "Counts all demand data writes (RFOs)",
1682
+
"Counter": "0,1,2,3",
1871
1683
"EventCode": "0xB7, 0xBB",
1872
1684
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
1873
1685
"MSRIndex": "0x1a6,0x1a7",
···
1878
1688
},
1879
1689
{
1880
1690
"BriefDescription": "Counts all demand data writes (RFOs)",
1691
+
"Counter": "0,1,2,3",
1881
1692
"EventCode": "0xB7, 0xBB",
1882
1693
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
1883
1694
"MSRIndex": "0x1a6,0x1a7",
···
1888
1697
},
1889
1698
{
1890
1699
"BriefDescription": "Counts all demand data writes (RFOs)",
1700
+
"Counter": "0,1,2,3",
1891
1701
"EventCode": "0xB7, 0xBB",
1892
1702
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
1893
1703
"MSRIndex": "0x1a6,0x1a7",
···
1898
1706
},
1899
1707
{
1900
1708
"BriefDescription": "Counts all demand data writes (RFOs)",
1709
+
"Counter": "0,1,2,3",
1901
1710
"EventCode": "0xB7, 0xBB",
1902
1711
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
1903
1712
"MSRIndex": "0x1a6,0x1a7",
···
1908
1715
},
1909
1716
{
1910
1717
"BriefDescription": "Counts all demand data writes (RFOs)",
1718
+
"Counter": "0,1,2,3",
1911
1719
"EventCode": "0xB7, 0xBB",
1912
1720
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT",
1913
1721
"MSRIndex": "0x1a6,0x1a7",
···
1918
1724
},
1919
1725
{
1920
1726
"BriefDescription": "Counts any other requests have any response type.",
1727
+
"Counter": "0,1,2,3",
1921
1728
"EventCode": "0xB7, 0xBB",
1922
1729
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
1923
1730
"MSRIndex": "0x1a6,0x1a7",
···
1928
1733
},
1929
1734
{
1930
1735
"BriefDescription": "Counts any other requests",
1736
+
"Counter": "0,1,2,3",
1931
1737
"EventCode": "0xB7, 0xBB",
1932
1738
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
1933
1739
"MSRIndex": "0x1a6,0x1a7",
···
1938
1742
},
1939
1743
{
1940
1744
"BriefDescription": "Counts any other requests",
1745
+
"Counter": "0,1,2,3",
1941
1746
"EventCode": "0xB7, 0xBB",
1942
1747
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM",
1943
1748
"MSRIndex": "0x1a6,0x1a7",
···
1948
1751
},
1949
1752
{
1950
1753
"BriefDescription": "Counts any other requests",
1754
+
"Counter": "0,1,2,3",
1951
1755
"EventCode": "0xB7, 0xBB",
1952
1756
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
1953
1757
"MSRIndex": "0x1a6,0x1a7",
···
1958
1760
},
1959
1761
{
1960
1762
"BriefDescription": "Counts any other requests",
1763
+
"Counter": "0,1,2,3",
1961
1764
"EventCode": "0xB7, 0xBB",
1962
1765
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
1963
1766
"MSRIndex": "0x1a6,0x1a7",
···
1968
1769
},
1969
1770
{
1970
1771
"BriefDescription": "Counts any other requests",
1772
+
"Counter": "0,1,2,3",
1971
1773
"EventCode": "0xB7, 0xBB",
1972
1774
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
1973
1775
"MSRIndex": "0x1a6,0x1a7",
···
1978
1778
},
1979
1779
{
1980
1780
"BriefDescription": "Counts any other requests",
1781
+
"Counter": "0,1,2,3",
1981
1782
"EventCode": "0xB7, 0xBB",
1982
1783
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
1983
1784
"MSRIndex": "0x1a6,0x1a7",
···
1988
1787
},
1989
1788
{
1990
1789
"BriefDescription": "Counts any other requests",
1790
+
"Counter": "0,1,2,3",
1991
1791
"EventCode": "0xB7, 0xBB",
1992
1792
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT",
1993
1793
"MSRIndex": "0x1a6,0x1a7",
···
1998
1796
},
1999
1797
{
2000
1798
"BriefDescription": "Counts any other requests",
1799
+
"Counter": "0,1,2,3",
2001
1800
"EventCode": "0xB7, 0xBB",
2002
1801
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
2003
1802
"MSRIndex": "0x1a6,0x1a7",
···
2008
1805
},
2009
1806
{
2010
1807
"BriefDescription": "Counts any other requests",
1808
+
"Counter": "0,1,2,3",
2011
1809
"EventCode": "0xB7, 0xBB",
2012
1810
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM",
2013
1811
"MSRIndex": "0x1a6,0x1a7",
···
2018
1814
},
2019
1815
{
2020
1816
"BriefDescription": "Counts any other requests",
1817
+
"Counter": "0,1,2,3",
2021
1818
"EventCode": "0xB7, 0xBB",
2022
1819
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD",
2023
1820
"MSRIndex": "0x1a6,0x1a7",
···
2028
1823
},
2029
1824
{
2030
1825
"BriefDescription": "Counts any other requests",
1826
+
"Counter": "0,1,2,3",
2031
1827
"EventCode": "0xB7, 0xBB",
2032
1828
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
2033
1829
"MSRIndex": "0x1a6,0x1a7",
···
2038
1832
},
2039
1833
{
2040
1834
"BriefDescription": "Counts any other requests",
1835
+
"Counter": "0,1,2,3",
2041
1836
"EventCode": "0xB7, 0xBB",
2042
1837
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
2043
1838
"MSRIndex": "0x1a6,0x1a7",
···
2048
1841
},
2049
1842
{
2050
1843
"BriefDescription": "Counts any other requests",
1844
+
"Counter": "0,1,2,3",
2051
1845
"EventCode": "0xB7, 0xBB",
2052
1846
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED",
2053
1847
"MSRIndex": "0x1a6,0x1a7",
···
2058
1850
},
2059
1851
{
2060
1852
"BriefDescription": "Counts any other requests",
1853
+
"Counter": "0,1,2,3",
2061
1854
"EventCode": "0xB7, 0xBB",
2062
1855
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT",
2063
1856
"MSRIndex": "0x1a6,0x1a7",
···
2068
1859
},
2069
1860
{
2070
1861
"BriefDescription": "Counts any other requests",
1862
+
"Counter": "0,1,2,3",
2071
1863
"EventCode": "0xB7, 0xBB",
2072
1864
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
2073
1865
"MSRIndex": "0x1a6,0x1a7",
···
2078
1868
},
2079
1869
{
2080
1870
"BriefDescription": "Counts any other requests",
1871
+
"Counter": "0,1,2,3",
2081
1872
"EventCode": "0xB7, 0xBB",
2082
1873
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM",
2083
1874
"MSRIndex": "0x1a6,0x1a7",
···
2088
1877
},
2089
1878
{
2090
1879
"BriefDescription": "Counts any other requests",
1880
+
"Counter": "0,1,2,3",
2091
1881
"EventCode": "0xB7, 0xBB",
2092
1882
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD",
2093
1883
"MSRIndex": "0x1a6,0x1a7",
···
2098
1886
},
2099
1887
{
2100
1888
"BriefDescription": "Counts any other requests",
1889
+
"Counter": "0,1,2,3",
2101
1890
"EventCode": "0xB7, 0xBB",
2102
1891
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
2103
1892
"MSRIndex": "0x1a6,0x1a7",
···
2108
1895
},
2109
1896
{
2110
1897
"BriefDescription": "Counts any other requests",
1898
+
"Counter": "0,1,2,3",
2111
1899
"EventCode": "0xB7, 0xBB",
2112
1900
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
2113
1901
"MSRIndex": "0x1a6,0x1a7",
···
2118
1904
},
2119
1905
{
2120
1906
"BriefDescription": "Counts any other requests",
1907
+
"Counter": "0,1,2,3",
2121
1908
"EventCode": "0xB7, 0xBB",
2122
1909
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED",
2123
1910
"MSRIndex": "0x1a6,0x1a7",
···
2128
1913
},
2129
1914
{
2130
1915
"BriefDescription": "Counts any other requests",
1916
+
"Counter": "0,1,2,3",
2131
1917
"EventCode": "0xB7, 0xBB",
2132
1918
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT",
2133
1919
"MSRIndex": "0x1a6,0x1a7",
···
2138
1922
},
2139
1923
{
2140
1924
"BriefDescription": "Counts any other requests",
1925
+
"Counter": "0,1,2,3",
2141
1926
"EventCode": "0xB7, 0xBB",
2142
1927
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
2143
1928
"MSRIndex": "0x1a6,0x1a7",
···
2148
1931
},
2149
1932
{
2150
1933
"BriefDescription": "Counts any other requests",
1934
+
"Counter": "0,1,2,3",
2151
1935
"EventCode": "0xB7, 0xBB",
2152
1936
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM",
2153
1937
"MSRIndex": "0x1a6,0x1a7",
···
2158
1940
},
2159
1941
{
2160
1942
"BriefDescription": "Counts any other requests",
1943
+
"Counter": "0,1,2,3",
2161
1944
"EventCode": "0xB7, 0xBB",
2162
1945
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD",
2163
1946
"MSRIndex": "0x1a6,0x1a7",
···
2168
1949
},
2169
1950
{
2170
1951
"BriefDescription": "Counts any other requests",
1952
+
"Counter": "0,1,2,3",
2171
1953
"EventCode": "0xB7, 0xBB",
2172
1954
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
2173
1955
"MSRIndex": "0x1a6,0x1a7",
···
2178
1958
},
2179
1959
{
2180
1960
"BriefDescription": "Counts any other requests",
1961
+
"Counter": "0,1,2,3",
2181
1962
"EventCode": "0xB7, 0xBB",
2182
1963
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
2183
1964
"MSRIndex": "0x1a6,0x1a7",
···
2188
1967
},
2189
1968
{
2190
1969
"BriefDescription": "Counts any other requests",
1970
+
"Counter": "0,1,2,3",
2191
1971
"EventCode": "0xB7, 0xBB",
2192
1972
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED",
2193
1973
"MSRIndex": "0x1a6,0x1a7",
···
2198
1976
},
2199
1977
{
2200
1978
"BriefDescription": "Counts any other requests",
1979
+
"Counter": "0,1,2,3",
2201
1980
"EventCode": "0xB7, 0xBB",
2202
1981
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT",
2203
1982
"MSRIndex": "0x1a6,0x1a7",
···
2208
1985
},
2209
1986
{
2210
1987
"BriefDescription": "Counts any other requests",
1988
+
"Counter": "0,1,2,3",
2211
1989
"EventCode": "0xB7, 0xBB",
2212
1990
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP",
2213
1991
"MSRIndex": "0x1a6,0x1a7",
···
2218
1994
},
2219
1995
{
2220
1996
"BriefDescription": "Counts any other requests",
1997
+
"Counter": "0,1,2,3",
2221
1998
"EventCode": "0xB7, 0xBB",
2222
1999
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM",
2223
2000
"MSRIndex": "0x1a6,0x1a7",
···
2228
2003
},
2229
2004
{
2230
2005
"BriefDescription": "Counts any other requests",
2006
+
"Counter": "0,1,2,3",
2231
2007
"EventCode": "0xB7, 0xBB",
2232
2008
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
2233
2009
"MSRIndex": "0x1a6,0x1a7",
···
2238
2012
},
2239
2013
{
2240
2014
"BriefDescription": "Counts any other requests",
2015
+
"Counter": "0,1,2,3",
2241
2016
"EventCode": "0xB7, 0xBB",
2242
2017
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS",
2243
2018
"MSRIndex": "0x1a6,0x1a7",
···
2248
2021
},
2249
2022
{
2250
2023
"BriefDescription": "Counts any other requests",
2024
+
"Counter": "0,1,2,3",
2251
2025
"EventCode": "0xB7, 0xBB",
2252
2026
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE",
2253
2027
"MSRIndex": "0x1a6,0x1a7",
···
2258
2030
},
2259
2031
{
2260
2032
"BriefDescription": "Counts any other requests",
2033
+
"Counter": "0,1,2,3",
2261
2034
"EventCode": "0xB7, 0xBB",
2262
2035
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
2263
2036
"MSRIndex": "0x1a6,0x1a7",
···
2268
2039
},
2269
2040
{
2270
2041
"BriefDescription": "Counts any other requests",
2042
+
"Counter": "0,1,2,3",
2271
2043
"EventCode": "0xB7, 0xBB",
2272
2044
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT",
2273
2045
"MSRIndex": "0x1a6,0x1a7",
···
2278
2048
},
2279
2049
{
2280
2050
"BriefDescription": "Counts any other requests",
2051
+
"Counter": "0,1,2,3",
2281
2052
"EventCode": "0xB7, 0xBB",
2282
2053
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
2283
2054
"MSRIndex": "0x1a6,0x1a7",
···
2288
2057
},
2289
2058
{
2290
2059
"BriefDescription": "Counts any other requests",
2060
+
"Counter": "0,1,2,3",
2291
2061
"EventCode": "0xB7, 0xBB",
2292
2062
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM",
2293
2063
"MSRIndex": "0x1a6,0x1a7",
···
2298
2066
},
2299
2067
{
2300
2068
"BriefDescription": "Counts any other requests",
2069
+
"Counter": "0,1,2,3",
2301
2070
"EventCode": "0xB7, 0xBB",
2302
2071
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
2303
2072
"MSRIndex": "0x1a6,0x1a7",
···
2308
2075
},
2309
2076
{
2310
2077
"BriefDescription": "Counts any other requests",
2078
+
"Counter": "0,1,2,3",
2311
2079
"EventCode": "0xB7, 0xBB",
2312
2080
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
2313
2081
"MSRIndex": "0x1a6,0x1a7",
···
2318
2084
},
2319
2085
{
2320
2086
"BriefDescription": "Counts any other requests",
2087
+
"Counter": "0,1,2,3",
2321
2088
"EventCode": "0xB7, 0xBB",
2322
2089
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
2323
2090
"MSRIndex": "0x1a6,0x1a7",
···
2328
2093
},
2329
2094
{
2330
2095
"BriefDescription": "Counts any other requests",
2096
+
"Counter": "0,1,2,3",
2331
2097
"EventCode": "0xB7, 0xBB",
2332
2098
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
2333
2099
"MSRIndex": "0x1a6,0x1a7",
···
2338
2102
},
2339
2103
{
2340
2104
"BriefDescription": "Counts any other requests",
2105
+
"Counter": "0,1,2,3",
2341
2106
"EventCode": "0xB7, 0xBB",
2342
2107
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT",
2343
2108
"MSRIndex": "0x1a6,0x1a7",
···
2348
2111
},
2349
2112
{
2350
2113
"BriefDescription": "Number of cache line split locks sent to uncore.",
2114
+
"Counter": "0,1,2,3",
2351
2115
"EventCode": "0xF4",
2352
2116
"EventName": "SQ_MISC.SPLIT_LOCK",
2353
2117
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
···
2356
2118
"UMask": "0x10"
2357
2119
},
2358
2120
{
2121
+
"BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
2122
+
"Counter": "0,1,2,3",
2123
+
"EventCode": "0x32",
2124
+
"EventName": "SW_PREFETCH_ACCESS.ANY",
2125
+
"SampleAfterValue": "2000003",
2126
+
"UMask": "0xf"
2127
+
},
2128
+
{
2359
2129
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
2130
+
"Counter": "0,1,2,3",
2360
2131
"EventCode": "0x32",
2361
2132
"EventName": "SW_PREFETCH_ACCESS.NTA",
2362
2133
"SampleAfterValue": "2000003",
···
2373
2126
},
2374
2127
{
2375
2128
"BriefDescription": "Number of PREFETCHW instructions executed.",
2129
+
"Counter": "0,1,2,3",
2376
2130
"EventCode": "0x32",
2377
2131
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
2378
2132
"SampleAfterValue": "2000003",
···
2381
2133
},
2382
2134
{
2383
2135
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
2136
+
"Counter": "0,1,2,3",
2384
2137
"EventCode": "0x32",
2385
2138
"EventName": "SW_PREFETCH_ACCESS.T0",
2386
2139
"SampleAfterValue": "2000003",
···
2389
2140
},
2390
2141
{
2391
2142
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
2143
+
"Counter": "0,1,2,3",
2392
2144
"EventCode": "0x32",
2393
2145
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
2394
2146
"SampleAfterValue": "2000003",
+22
tools/perf/pmu-events/arch/x86/skylake/counter.json
+22
tools/perf/pmu-events/arch/x86/skylake/counter.json
···
1
+
[
2
+
{
3
+
"Unit": "core",
4
+
"CountersNumFixed": "3",
5
+
"CountersNumGeneric": "4"
6
+
},
7
+
{
8
+
"Unit": "CBOX",
9
+
"CountersNumFixed": "0",
10
+
"CountersNumGeneric": "2"
11
+
},
12
+
{
13
+
"Unit": "ARB",
14
+
"CountersNumFixed": "0",
15
+
"CountersNumGeneric": "2"
16
+
},
17
+
{
18
+
"Unit": "cbox_0",
19
+
"CountersNumFixed": 1,
20
+
"CountersNumGeneric": "0"
21
+
}
22
+
]
+10
tools/perf/pmu-events/arch/x86/skylake/floating-point.json
+10
tools/perf/pmu-events/arch/x86/skylake/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xC7",
5
6
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
6
7
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xC7",
14
14
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
15
15
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xC7",
23
22
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
24
23
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
28
25
},
29
26
{
30
27
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xC7",
32
30
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
33
31
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
37
33
},
38
34
{
39
35
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
36
+
"Counter": "0,1,2,3",
40
37
"EventCode": "0xC7",
41
38
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
42
39
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
46
41
},
47
42
{
48
43
"BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
44
+
"Counter": "0,1,2,3",
49
45
"EventCode": "0xC7",
50
46
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
51
47
"PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
55
49
},
56
50
{
57
51
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
52
+
"Counter": "0,1,2,3",
58
53
"EventCode": "0xC7",
59
54
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
60
55
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
64
57
},
65
58
{
66
59
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
60
+
"Counter": "0,1,2,3",
67
61
"EventCode": "0xC7",
68
62
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
69
63
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
···
73
65
},
74
66
{
75
67
"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
68
+
"Counter": "0,1,2,3",
76
69
"EventCode": "0xC7",
77
70
"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
78
71
"SampleAfterValue": "2000003",
···
81
72
},
82
73
{
83
74
"BriefDescription": "Cycles with any input/output SSE or FP assist",
75
+
"Counter": "0,1,2,3",
84
76
"CounterMask": "1",
85
77
"EventCode": "0xCA",
86
78
"EventName": "FP_ASSIST.ANY",
+49
tools/perf/pmu-events/arch/x86/skylake/frontend.json
+49
tools/perf/pmu-events/arch/x86/skylake/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xE6",
5
6
"EventName": "BACLEARS.ANY",
6
7
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0x87",
14
14
"EventName": "DECODE.LCP",
15
15
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xAB",
23
22
"EventName": "DSB2MITE_SWITCHES.COUNT",
24
23
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking MITE requires two or three cycles delay.",
···
28
25
},
29
26
{
30
27
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28
+
"Counter": "0,1,2,3",
31
29
"EventCode": "0xAB",
32
30
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
33
31
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
···
37
33
},
38
34
{
39
35
"BriefDescription": "Retired Instructions who experienced DSB miss.",
36
+
"Counter": "0,1,2,3",
40
37
"EventCode": "0xC6",
41
38
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
42
39
"MSRIndex": "0x3F7",
···
49
44
},
50
45
{
51
46
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
47
+
"Counter": "0,1,2,3",
52
48
"EventCode": "0xC6",
53
49
"EventName": "FRONTEND_RETIRED.DSB_MISS",
54
50
"MSRIndex": "0x3F7",
···
61
55
},
62
56
{
63
57
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
58
+
"Counter": "0,1,2,3",
64
59
"EventCode": "0xC6",
65
60
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
66
61
"MSRIndex": "0x3F7",
···
73
66
},
74
67
{
75
68
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
69
+
"Counter": "0,1,2,3",
76
70
"EventCode": "0xC6",
77
71
"EventName": "FRONTEND_RETIRED.L1I_MISS",
78
72
"MSRIndex": "0x3F7",
···
84
76
},
85
77
{
86
78
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
79
+
"Counter": "0,1,2,3",
87
80
"EventCode": "0xC6",
88
81
"EventName": "FRONTEND_RETIRED.L2_MISS",
89
82
"MSRIndex": "0x3F7",
···
95
86
},
96
87
{
97
88
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
89
+
"Counter": "0,1,2,3",
98
90
"EventCode": "0xc6",
99
91
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
100
92
"MSRIndex": "0x3F7",
···
107
97
},
108
98
{
109
99
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
100
+
"Counter": "0,1,2,3",
110
101
"EventCode": "0xC6",
111
102
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
112
103
"MSRIndex": "0x3F7",
···
118
107
},
119
108
{
120
109
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
110
+
"Counter": "0,1,2,3",
121
111
"EventCode": "0xC6",
122
112
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
123
113
"MSRIndex": "0x3F7",
···
130
118
},
131
119
{
132
120
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
121
+
"Counter": "0,1,2,3",
133
122
"EventCode": "0xC6",
134
123
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
135
124
"MSRIndex": "0x3F7",
···
141
128
},
142
129
{
143
130
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
131
+
"Counter": "0,1,2,3",
144
132
"EventCode": "0xC6",
145
133
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
146
134
"MSRIndex": "0x3F7",
···
152
138
},
153
139
{
154
140
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
141
+
"Counter": "0,1,2,3",
155
142
"EventCode": "0xC6",
156
143
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
157
144
"MSRIndex": "0x3F7",
···
164
149
},
165
150
{
166
151
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
152
+
"Counter": "0,1,2,3",
167
153
"EventCode": "0xC6",
168
154
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
169
155
"MSRIndex": "0x3F7",
···
175
159
},
176
160
{
177
161
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
162
+
"Counter": "0,1,2,3",
178
163
"EventCode": "0xC6",
179
164
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
180
165
"MSRIndex": "0x3F7",
···
186
169
},
187
170
{
188
171
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
172
+
"Counter": "0,1,2,3",
189
173
"EventCode": "0xC6",
190
174
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
191
175
"MSRIndex": "0x3F7",
···
198
180
},
199
181
{
200
182
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
183
+
"Counter": "0,1,2,3",
201
184
"EventCode": "0xC6",
202
185
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
203
186
"MSRIndex": "0x3F7",
···
209
190
},
210
191
{
211
192
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
193
+
"Counter": "0,1,2,3",
212
194
"EventCode": "0xC6",
213
195
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
214
196
"MSRIndex": "0x3F7",
···
220
200
},
221
201
{
222
202
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
203
+
"Counter": "0,1,2,3",
223
204
"EventCode": "0xC6",
224
205
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
225
206
"MSRIndex": "0x3F7",
···
231
210
},
232
211
{
233
212
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
213
+
"Counter": "0,1,2,3",
234
214
"EventCode": "0xC6",
235
215
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
236
216
"MSRIndex": "0x3F7",
···
243
221
},
244
222
{
245
223
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
224
+
"Counter": "0,1,2,3",
246
225
"EventCode": "0xC6",
247
226
"EventName": "FRONTEND_RETIRED.STLB_MISS",
248
227
"MSRIndex": "0x3F7",
···
255
232
},
256
233
{
257
234
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
235
+
"Counter": "0,1,2,3",
258
236
"EventCode": "0x80",
259
237
"EventName": "ICACHE_16B.IFDATA_STALL",
260
238
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
···
264
240
},
265
241
{
266
242
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
243
+
"Counter": "0,1,2,3",
267
244
"EventCode": "0x83",
268
245
"EventName": "ICACHE_64B.IFTAG_HIT",
269
246
"SampleAfterValue": "200003",
···
272
247
},
273
248
{
274
249
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
250
+
"Counter": "0,1,2,3",
275
251
"EventCode": "0x83",
276
252
"EventName": "ICACHE_64B.IFTAG_MISS",
277
253
"SampleAfterValue": "200003",
···
280
254
},
281
255
{
282
256
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
257
+
"Counter": "0,1,2,3",
283
258
"EventCode": "0x83",
284
259
"EventName": "ICACHE_64B.IFTAG_STALL",
285
260
"SampleAfterValue": "200003",
···
288
261
},
289
262
{
290
263
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
264
+
"Counter": "0,1,2,3",
291
265
"EventCode": "0x83",
292
266
"EventName": "ICACHE_TAG.STALLS",
293
267
"SampleAfterValue": "200003",
···
296
268
},
297
269
{
298
270
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
271
+
"Counter": "0,1,2,3",
299
272
"CounterMask": "4",
300
273
"EventCode": "0x79",
301
274
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
···
306
277
},
307
278
{
308
279
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]",
280
+
"Counter": "0,1,2,3",
309
281
"CounterMask": "1",
310
282
"EventCode": "0x79",
311
283
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
···
316
286
},
317
287
{
318
288
"BriefDescription": "Cycles MITE is delivering 4 Uops",
289
+
"Counter": "0,1,2,3",
319
290
"CounterMask": "4",
320
291
"EventCode": "0x79",
321
292
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
···
326
295
},
327
296
{
328
297
"BriefDescription": "Cycles MITE is delivering any Uop",
298
+
"Counter": "0,1,2,3",
329
299
"CounterMask": "1",
330
300
"EventCode": "0x79",
331
301
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
···
336
304
},
337
305
{
338
306
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
307
+
"Counter": "0,1,2,3",
339
308
"CounterMask": "1",
340
309
"EventCode": "0x79",
341
310
"EventName": "IDQ.DSB_CYCLES",
···
346
313
},
347
314
{
348
315
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]",
316
+
"Counter": "0,1,2,3",
349
317
"CounterMask": "1",
350
318
"EventCode": "0x79",
351
319
"EventName": "IDQ.DSB_CYCLES_ANY",
···
356
322
},
357
323
{
358
324
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
325
+
"Counter": "0,1,2,3",
359
326
"CounterMask": "4",
360
327
"EventCode": "0x79",
361
328
"EventName": "IDQ.DSB_CYCLES_OK",
···
366
331
},
367
332
{
368
333
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
334
+
"Counter": "0,1,2,3",
369
335
"EventCode": "0x79",
370
336
"EventName": "IDQ.DSB_UOPS",
371
337
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
···
375
339
},
376
340
{
377
341
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
342
+
"Counter": "0,1,2,3",
378
343
"CounterMask": "1",
379
344
"EventCode": "0x79",
380
345
"EventName": "IDQ.MITE_CYCLES",
···
385
348
},
386
349
{
387
350
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
351
+
"Counter": "0,1,2,3",
388
352
"EventCode": "0x79",
389
353
"EventName": "IDQ.MITE_UOPS",
390
354
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
···
394
356
},
395
357
{
396
358
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
359
+
"Counter": "0,1,2,3",
397
360
"CounterMask": "1",
398
361
"EventCode": "0x79",
399
362
"EventName": "IDQ.MS_CYCLES",
···
404
365
},
405
366
{
406
367
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
368
+
"Counter": "0,1,2,3",
407
369
"CounterMask": "1",
408
370
"EventCode": "0x79",
409
371
"EventName": "IDQ.MS_DSB_CYCLES",
···
414
374
},
415
375
{
416
376
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
377
+
"Counter": "0,1,2,3",
417
378
"EventCode": "0x79",
418
379
"EventName": "IDQ.MS_MITE_UOPS",
419
380
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
···
423
382
},
424
383
{
425
384
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
385
+
"Counter": "0,1,2,3",
426
386
"CounterMask": "1",
427
387
"EdgeDetect": "1",
428
388
"EventCode": "0x79",
···
434
392
},
435
393
{
436
394
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
395
+
"Counter": "0,1,2,3",
437
396
"EventCode": "0x79",
438
397
"EventName": "IDQ.MS_UOPS",
439
398
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
···
443
400
},
444
401
{
445
402
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
403
+
"Counter": "0,1,2,3",
446
404
"EventCode": "0x9C",
447
405
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
448
406
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
···
452
408
},
453
409
{
454
410
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
411
+
"Counter": "0,1,2,3",
455
412
"CounterMask": "4",
456
413
"EventCode": "0x9C",
457
414
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
···
462
417
},
463
418
{
464
419
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
420
+
"Counter": "0,1,2,3",
465
421
"CounterMask": "1",
466
422
"EventCode": "0x9C",
467
423
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
···
472
426
},
473
427
{
474
428
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
429
+
"Counter": "0,1,2,3",
475
430
"CounterMask": "3",
476
431
"EventCode": "0x9C",
477
432
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
···
482
435
},
483
436
{
484
437
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
438
+
"Counter": "0,1,2,3",
485
439
"CounterMask": "2",
486
440
"EventCode": "0x9C",
487
441
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
···
492
444
},
493
445
{
494
446
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
447
+
"Counter": "0,1,2,3",
495
448
"CounterMask": "1",
496
449
"EventCode": "0x9C",
497
450
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
+131
tools/perf/pmu-events/arch/x86/skylake/memory.json
+131
tools/perf/pmu-events/arch/x86/skylake/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
4
+
"Counter": "0,1,2,3",
4
5
"CounterMask": "2",
5
6
"EventCode": "0xA3",
6
7
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
12
+
"Counter": "0,1,2,3",
13
13
"CounterMask": "6",
14
14
"EventCode": "0xA3",
15
15
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
20
+
"Counter": "0,1,2,3",
22
21
"EventCode": "0xC8",
23
22
"EventName": "HLE_RETIRED.ABORTED",
24
23
"PEBS": "1",
···
29
26
},
30
27
{
31
28
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
29
+
"Counter": "0,1,2,3",
32
30
"EventCode": "0xC8",
33
31
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
34
32
"SampleAfterValue": "2000003",
···
37
33
},
38
34
{
39
35
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
36
+
"Counter": "0,1,2,3",
40
37
"EventCode": "0xC8",
41
38
"EventName": "HLE_RETIRED.ABORTED_MEM",
42
39
"SampleAfterValue": "2000003",
···
45
40
},
46
41
{
47
42
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
43
+
"Counter": "0,1,2,3",
48
44
"EventCode": "0xC8",
49
45
"EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
50
46
"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
···
54
48
},
55
49
{
56
50
"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
51
+
"Counter": "0,1,2,3",
57
52
"EventCode": "0xC8",
58
53
"EventName": "HLE_RETIRED.ABORTED_TIMER",
59
54
"SampleAfterValue": "2000003",
···
62
55
},
63
56
{
64
57
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
58
+
"Counter": "0,1,2,3",
65
59
"EventCode": "0xC8",
66
60
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
67
61
"SampleAfterValue": "2000003",
···
70
62
},
71
63
{
72
64
"BriefDescription": "Number of times an HLE execution successfully committed",
65
+
"Counter": "0,1,2,3",
73
66
"EventCode": "0xC8",
74
67
"EventName": "HLE_RETIRED.COMMIT",
75
68
"PublicDescription": "Number of times HLE commit succeeded.",
···
79
70
},
80
71
{
81
72
"BriefDescription": "Number of times an HLE execution started.",
73
+
"Counter": "0,1,2,3",
82
74
"EventCode": "0xC8",
83
75
"EventName": "HLE_RETIRED.START",
84
76
"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
···
88
78
},
89
79
{
90
80
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
81
+
"Counter": "0,1,2,3",
91
82
"Errata": "SKL089",
92
83
"EventCode": "0xC3",
93
84
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
···
98
87
},
99
88
{
100
89
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
90
+
"Counter": "0,1,2,3",
101
91
"Data_LA": "1",
102
92
"EventCode": "0xcd",
103
93
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
···
111
99
},
112
100
{
113
101
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
102
+
"Counter": "0,1,2,3",
114
103
"Data_LA": "1",
115
104
"EventCode": "0xcd",
116
105
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
···
124
111
},
125
112
{
126
113
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
114
+
"Counter": "0,1,2,3",
127
115
"Data_LA": "1",
128
116
"EventCode": "0xcd",
129
117
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
···
137
123
},
138
124
{
139
125
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
126
+
"Counter": "0,1,2,3",
140
127
"Data_LA": "1",
141
128
"EventCode": "0xcd",
142
129
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
···
150
135
},
151
136
{
152
137
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
138
+
"Counter": "0,1,2,3",
153
139
"Data_LA": "1",
154
140
"EventCode": "0xcd",
155
141
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
···
163
147
},
164
148
{
165
149
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
150
+
"Counter": "0,1,2,3",
166
151
"Data_LA": "1",
167
152
"EventCode": "0xcd",
168
153
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
···
176
159
},
177
160
{
178
161
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
162
+
"Counter": "0,1,2,3",
179
163
"Data_LA": "1",
180
164
"EventCode": "0xcd",
181
165
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
···
189
171
},
190
172
{
191
173
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
174
+
"Counter": "0,1,2,3",
192
175
"Data_LA": "1",
193
176
"EventCode": "0xcd",
194
177
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
···
202
183
},
203
184
{
204
185
"BriefDescription": "Demand Data Read requests who miss L3 cache",
186
+
"Counter": "0,1,2,3",
205
187
"EventCode": "0xB0",
206
188
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
207
189
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
···
211
191
},
212
192
{
213
193
"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
194
+
"Counter": "0,1,2,3",
214
195
"CounterMask": "1",
215
196
"EventCode": "0x60",
216
197
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
···
220
199
},
221
200
{
222
201
"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
202
+
"Counter": "0,1,2,3",
223
203
"EventCode": "0x60",
224
204
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
225
205
"SampleAfterValue": "2000003",
···
228
206
},
229
207
{
230
208
"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
209
+
"Counter": "0,1,2,3",
231
210
"CounterMask": "6",
232
211
"EventCode": "0x60",
233
212
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
···
237
214
},
238
215
{
239
216
"BriefDescription": "Counts all demand code reads",
217
+
"Counter": "0,1,2,3",
240
218
"EventCode": "0xB7, 0xBB",
241
219
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
242
220
"MSRIndex": "0x1a6,0x1a7",
···
247
223
},
248
224
{
249
225
"BriefDescription": "Counts all demand code reads",
226
+
"Counter": "0,1,2,3",
250
227
"EventCode": "0xB7, 0xBB",
251
228
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
252
229
"MSRIndex": "0x1a6,0x1a7",
···
257
232
},
258
233
{
259
234
"BriefDescription": "Counts all demand code reads",
235
+
"Counter": "0,1,2,3",
260
236
"EventCode": "0xB7, 0xBB",
261
237
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
262
238
"MSRIndex": "0x1a6,0x1a7",
···
267
241
},
268
242
{
269
243
"BriefDescription": "Counts all demand code reads",
244
+
"Counter": "0,1,2,3",
270
245
"EventCode": "0xB7, 0xBB",
271
246
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
272
247
"MSRIndex": "0x1a6,0x1a7",
···
277
250
},
278
251
{
279
252
"BriefDescription": "Counts all demand code reads",
253
+
"Counter": "0,1,2,3",
280
254
"EventCode": "0xB7, 0xBB",
281
255
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
282
256
"MSRIndex": "0x1a6,0x1a7",
···
287
259
},
288
260
{
289
261
"BriefDescription": "Counts all demand code reads",
262
+
"Counter": "0,1,2,3",
290
263
"EventCode": "0xB7, 0xBB",
291
264
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
292
265
"MSRIndex": "0x1a6,0x1a7",
···
297
268
},
298
269
{
299
270
"BriefDescription": "Counts all demand code reads",
271
+
"Counter": "0,1,2,3",
300
272
"EventCode": "0xB7, 0xBB",
301
273
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
302
274
"MSRIndex": "0x1a6,0x1a7",
···
307
277
},
308
278
{
309
279
"BriefDescription": "Counts all demand code reads",
280
+
"Counter": "0,1,2,3",
310
281
"EventCode": "0xB7, 0xBB",
311
282
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
312
283
"MSRIndex": "0x1a6,0x1a7",
···
317
286
},
318
287
{
319
288
"BriefDescription": "Counts all demand code reads",
289
+
"Counter": "0,1,2,3",
320
290
"EventCode": "0xB7, 0xBB",
321
291
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
322
292
"MSRIndex": "0x1a6,0x1a7",
···
327
295
},
328
296
{
329
297
"BriefDescription": "Counts all demand code reads",
298
+
"Counter": "0,1,2,3",
330
299
"EventCode": "0xB7, 0xBB",
331
300
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
332
301
"MSRIndex": "0x1a6,0x1a7",
···
337
304
},
338
305
{
339
306
"BriefDescription": "Counts all demand code reads",
307
+
"Counter": "0,1,2,3",
340
308
"EventCode": "0xB7, 0xBB",
341
309
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
342
310
"MSRIndex": "0x1a6,0x1a7",
···
347
313
},
348
314
{
349
315
"BriefDescription": "Counts all demand code reads",
316
+
"Counter": "0,1,2,3",
350
317
"EventCode": "0xB7, 0xBB",
351
318
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
352
319
"MSRIndex": "0x1a6,0x1a7",
···
357
322
},
358
323
{
359
324
"BriefDescription": "Counts all demand code reads",
325
+
"Counter": "0,1,2,3",
360
326
"EventCode": "0xB7, 0xBB",
361
327
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
362
328
"MSRIndex": "0x1a6,0x1a7",
···
367
331
},
368
332
{
369
333
"BriefDescription": "Counts all demand code reads",
334
+
"Counter": "0,1,2,3",
370
335
"EventCode": "0xB7, 0xBB",
371
336
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
372
337
"MSRIndex": "0x1a6,0x1a7",
···
377
340
},
378
341
{
379
342
"BriefDescription": "Counts all demand code reads",
343
+
"Counter": "0,1,2,3",
380
344
"EventCode": "0xB7, 0xBB",
381
345
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
382
346
"MSRIndex": "0x1a6,0x1a7",
···
387
349
},
388
350
{
389
351
"BriefDescription": "Counts all demand code reads",
352
+
"Counter": "0,1,2,3",
390
353
"EventCode": "0xB7, 0xBB",
391
354
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
392
355
"MSRIndex": "0x1a6,0x1a7",
···
397
358
},
398
359
{
399
360
"BriefDescription": "Counts all demand code reads",
361
+
"Counter": "0,1,2,3",
400
362
"EventCode": "0xB7, 0xBB",
401
363
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
402
364
"MSRIndex": "0x1a6,0x1a7",
···
407
367
},
408
368
{
409
369
"BriefDescription": "Counts all demand code reads",
370
+
"Counter": "0,1,2,3",
410
371
"EventCode": "0xB7, 0xBB",
411
372
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
412
373
"MSRIndex": "0x1a6,0x1a7",
···
417
376
},
418
377
{
419
378
"BriefDescription": "Counts all demand code reads",
379
+
"Counter": "0,1,2,3",
420
380
"EventCode": "0xB7, 0xBB",
421
381
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
422
382
"MSRIndex": "0x1a6,0x1a7",
···
427
385
},
428
386
{
429
387
"BriefDescription": "Counts all demand code reads",
388
+
"Counter": "0,1,2,3",
430
389
"EventCode": "0xB7, 0xBB",
431
390
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
432
391
"MSRIndex": "0x1a6,0x1a7",
···
437
394
},
438
395
{
439
396
"BriefDescription": "Counts all demand code reads",
397
+
"Counter": "0,1,2,3",
440
398
"EventCode": "0xB7, 0xBB",
441
399
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
442
400
"MSRIndex": "0x1a6,0x1a7",
···
447
403
},
448
404
{
449
405
"BriefDescription": "Counts all demand code reads",
406
+
"Counter": "0,1,2,3",
450
407
"EventCode": "0xB7, 0xBB",
451
408
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
452
409
"MSRIndex": "0x1a6,0x1a7",
···
457
412
},
458
413
{
459
414
"BriefDescription": "Counts demand data reads",
415
+
"Counter": "0,1,2,3",
460
416
"EventCode": "0xB7, 0xBB",
461
417
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
462
418
"MSRIndex": "0x1a6,0x1a7",
···
467
421
},
468
422
{
469
423
"BriefDescription": "Counts demand data reads",
424
+
"Counter": "0,1,2,3",
470
425
"EventCode": "0xB7, 0xBB",
471
426
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
472
427
"MSRIndex": "0x1a6,0x1a7",
···
477
430
},
478
431
{
479
432
"BriefDescription": "Counts demand data reads",
433
+
"Counter": "0,1,2,3",
480
434
"EventCode": "0xB7, 0xBB",
481
435
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
482
436
"MSRIndex": "0x1a6,0x1a7",
···
487
439
},
488
440
{
489
441
"BriefDescription": "Counts demand data reads",
442
+
"Counter": "0,1,2,3",
490
443
"EventCode": "0xB7, 0xBB",
491
444
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
492
445
"MSRIndex": "0x1a6,0x1a7",
···
497
448
},
498
449
{
499
450
"BriefDescription": "Counts demand data reads",
451
+
"Counter": "0,1,2,3",
500
452
"EventCode": "0xB7, 0xBB",
501
453
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
502
454
"MSRIndex": "0x1a6,0x1a7",
···
507
457
},
508
458
{
509
459
"BriefDescription": "Counts demand data reads",
460
+
"Counter": "0,1,2,3",
510
461
"EventCode": "0xB7, 0xBB",
511
462
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
512
463
"MSRIndex": "0x1a6,0x1a7",
···
517
466
},
518
467
{
519
468
"BriefDescription": "Counts demand data reads",
469
+
"Counter": "0,1,2,3",
520
470
"EventCode": "0xB7, 0xBB",
521
471
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
522
472
"MSRIndex": "0x1a6,0x1a7",
···
527
475
},
528
476
{
529
477
"BriefDescription": "Counts demand data reads",
478
+
"Counter": "0,1,2,3",
530
479
"EventCode": "0xB7, 0xBB",
531
480
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
532
481
"MSRIndex": "0x1a6,0x1a7",
···
537
484
},
538
485
{
539
486
"BriefDescription": "Counts demand data reads",
487
+
"Counter": "0,1,2,3",
540
488
"EventCode": "0xB7, 0xBB",
541
489
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
542
490
"MSRIndex": "0x1a6,0x1a7",
···
547
493
},
548
494
{
549
495
"BriefDescription": "Counts demand data reads",
496
+
"Counter": "0,1,2,3",
550
497
"EventCode": "0xB7, 0xBB",
551
498
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
552
499
"MSRIndex": "0x1a6,0x1a7",
···
557
502
},
558
503
{
559
504
"BriefDescription": "Counts demand data reads",
505
+
"Counter": "0,1,2,3",
560
506
"EventCode": "0xB7, 0xBB",
561
507
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
562
508
"MSRIndex": "0x1a6,0x1a7",
···
567
511
},
568
512
{
569
513
"BriefDescription": "Counts demand data reads",
514
+
"Counter": "0,1,2,3",
570
515
"EventCode": "0xB7, 0xBB",
571
516
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
572
517
"MSRIndex": "0x1a6,0x1a7",
···
577
520
},
578
521
{
579
522
"BriefDescription": "Counts demand data reads",
523
+
"Counter": "0,1,2,3",
580
524
"EventCode": "0xB7, 0xBB",
581
525
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
582
526
"MSRIndex": "0x1a6,0x1a7",
···
587
529
},
588
530
{
589
531
"BriefDescription": "Counts demand data reads",
532
+
"Counter": "0,1,2,3",
590
533
"EventCode": "0xB7, 0xBB",
591
534
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
592
535
"MSRIndex": "0x1a6,0x1a7",
···
597
538
},
598
539
{
599
540
"BriefDescription": "Counts demand data reads",
541
+
"Counter": "0,1,2,3",
600
542
"EventCode": "0xB7, 0xBB",
601
543
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
602
544
"MSRIndex": "0x1a6,0x1a7",
···
607
547
},
608
548
{
609
549
"BriefDescription": "Counts demand data reads",
550
+
"Counter": "0,1,2,3",
610
551
"EventCode": "0xB7, 0xBB",
611
552
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
612
553
"MSRIndex": "0x1a6,0x1a7",
···
617
556
},
618
557
{
619
558
"BriefDescription": "Counts demand data reads",
559
+
"Counter": "0,1,2,3",
620
560
"EventCode": "0xB7, 0xBB",
621
561
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
622
562
"MSRIndex": "0x1a6,0x1a7",
···
627
565
},
628
566
{
629
567
"BriefDescription": "Counts demand data reads",
568
+
"Counter": "0,1,2,3",
630
569
"EventCode": "0xB7, 0xBB",
631
570
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
632
571
"MSRIndex": "0x1a6,0x1a7",
···
637
574
},
638
575
{
639
576
"BriefDescription": "Counts demand data reads",
577
+
"Counter": "0,1,2,3",
640
578
"EventCode": "0xB7, 0xBB",
641
579
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
642
580
"MSRIndex": "0x1a6,0x1a7",
···
647
583
},
648
584
{
649
585
"BriefDescription": "Counts demand data reads",
586
+
"Counter": "0,1,2,3",
650
587
"EventCode": "0xB7, 0xBB",
651
588
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
652
589
"MSRIndex": "0x1a6,0x1a7",
···
657
592
},
658
593
{
659
594
"BriefDescription": "Counts demand data reads",
595
+
"Counter": "0,1,2,3",
660
596
"EventCode": "0xB7, 0xBB",
661
597
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
662
598
"MSRIndex": "0x1a6,0x1a7",
···
667
601
},
668
602
{
669
603
"BriefDescription": "Counts demand data reads",
604
+
"Counter": "0,1,2,3",
670
605
"EventCode": "0xB7, 0xBB",
671
606
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
672
607
"MSRIndex": "0x1a6,0x1a7",
···
677
610
},
678
611
{
679
612
"BriefDescription": "Counts all demand data writes (RFOs)",
613
+
"Counter": "0,1,2,3",
680
614
"EventCode": "0xB7, 0xBB",
681
615
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
682
616
"MSRIndex": "0x1a6,0x1a7",
···
687
619
},
688
620
{
689
621
"BriefDescription": "Counts all demand data writes (RFOs)",
622
+
"Counter": "0,1,2,3",
690
623
"EventCode": "0xB7, 0xBB",
691
624
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
692
625
"MSRIndex": "0x1a6,0x1a7",
···
697
628
},
698
629
{
699
630
"BriefDescription": "Counts all demand data writes (RFOs)",
631
+
"Counter": "0,1,2,3",
700
632
"EventCode": "0xB7, 0xBB",
701
633
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
702
634
"MSRIndex": "0x1a6,0x1a7",
···
707
637
},
708
638
{
709
639
"BriefDescription": "Counts all demand data writes (RFOs)",
640
+
"Counter": "0,1,2,3",
710
641
"EventCode": "0xB7, 0xBB",
711
642
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
712
643
"MSRIndex": "0x1a6,0x1a7",
···
717
646
},
718
647
{
719
648
"BriefDescription": "Counts all demand data writes (RFOs)",
649
+
"Counter": "0,1,2,3",
720
650
"EventCode": "0xB7, 0xBB",
721
651
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
722
652
"MSRIndex": "0x1a6,0x1a7",
···
727
655
},
728
656
{
729
657
"BriefDescription": "Counts all demand data writes (RFOs)",
658
+
"Counter": "0,1,2,3",
730
659
"EventCode": "0xB7, 0xBB",
731
660
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
732
661
"MSRIndex": "0x1a6,0x1a7",
···
737
664
},
738
665
{
739
666
"BriefDescription": "Counts all demand data writes (RFOs)",
667
+
"Counter": "0,1,2,3",
740
668
"EventCode": "0xB7, 0xBB",
741
669
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
742
670
"MSRIndex": "0x1a6,0x1a7",
···
747
673
},
748
674
{
749
675
"BriefDescription": "Counts all demand data writes (RFOs)",
676
+
"Counter": "0,1,2,3",
750
677
"EventCode": "0xB7, 0xBB",
751
678
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
752
679
"MSRIndex": "0x1a6,0x1a7",
···
757
682
},
758
683
{
759
684
"BriefDescription": "Counts all demand data writes (RFOs)",
685
+
"Counter": "0,1,2,3",
760
686
"EventCode": "0xB7, 0xBB",
761
687
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
762
688
"MSRIndex": "0x1a6,0x1a7",
···
767
691
},
768
692
{
769
693
"BriefDescription": "Counts all demand data writes (RFOs)",
694
+
"Counter": "0,1,2,3",
770
695
"EventCode": "0xB7, 0xBB",
771
696
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
772
697
"MSRIndex": "0x1a6,0x1a7",
···
777
700
},
778
701
{
779
702
"BriefDescription": "Counts all demand data writes (RFOs)",
703
+
"Counter": "0,1,2,3",
780
704
"EventCode": "0xB7, 0xBB",
781
705
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
782
706
"MSRIndex": "0x1a6,0x1a7",
···
787
709
},
788
710
{
789
711
"BriefDescription": "Counts all demand data writes (RFOs)",
712
+
"Counter": "0,1,2,3",
790
713
"EventCode": "0xB7, 0xBB",
791
714
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
792
715
"MSRIndex": "0x1a6,0x1a7",
···
797
718
},
798
719
{
799
720
"BriefDescription": "Counts all demand data writes (RFOs)",
721
+
"Counter": "0,1,2,3",
800
722
"EventCode": "0xB7, 0xBB",
801
723
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
802
724
"MSRIndex": "0x1a6,0x1a7",
···
807
727
},
808
728
{
809
729
"BriefDescription": "Counts all demand data writes (RFOs)",
730
+
"Counter": "0,1,2,3",
810
731
"EventCode": "0xB7, 0xBB",
811
732
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
812
733
"MSRIndex": "0x1a6,0x1a7",
···
817
736
},
818
737
{
819
738
"BriefDescription": "Counts all demand data writes (RFOs)",
739
+
"Counter": "0,1,2,3",
820
740
"EventCode": "0xB7, 0xBB",
821
741
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
822
742
"MSRIndex": "0x1a6,0x1a7",
···
827
745
},
828
746
{
829
747
"BriefDescription": "Counts all demand data writes (RFOs)",
748
+
"Counter": "0,1,2,3",
830
749
"EventCode": "0xB7, 0xBB",
831
750
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
832
751
"MSRIndex": "0x1a6,0x1a7",
···
837
754
},
838
755
{
839
756
"BriefDescription": "Counts all demand data writes (RFOs)",
757
+
"Counter": "0,1,2,3",
840
758
"EventCode": "0xB7, 0xBB",
841
759
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
842
760
"MSRIndex": "0x1a6,0x1a7",
···
847
763
},
848
764
{
849
765
"BriefDescription": "Counts all demand data writes (RFOs)",
766
+
"Counter": "0,1,2,3",
850
767
"EventCode": "0xB7, 0xBB",
851
768
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
852
769
"MSRIndex": "0x1a6,0x1a7",
···
857
772
},
858
773
{
859
774
"BriefDescription": "Counts all demand data writes (RFOs)",
775
+
"Counter": "0,1,2,3",
860
776
"EventCode": "0xB7, 0xBB",
861
777
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
862
778
"MSRIndex": "0x1a6,0x1a7",
···
867
781
},
868
782
{
869
783
"BriefDescription": "Counts all demand data writes (RFOs)",
784
+
"Counter": "0,1,2,3",
870
785
"EventCode": "0xB7, 0xBB",
871
786
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
872
787
"MSRIndex": "0x1a6,0x1a7",
···
877
790
},
878
791
{
879
792
"BriefDescription": "Counts all demand data writes (RFOs)",
793
+
"Counter": "0,1,2,3",
880
794
"EventCode": "0xB7, 0xBB",
881
795
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
882
796
"MSRIndex": "0x1a6,0x1a7",
···
887
799
},
888
800
{
889
801
"BriefDescription": "Counts all demand data writes (RFOs)",
802
+
"Counter": "0,1,2,3",
890
803
"EventCode": "0xB7, 0xBB",
891
804
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
892
805
"MSRIndex": "0x1a6,0x1a7",
···
897
808
},
898
809
{
899
810
"BriefDescription": "Counts any other requests",
811
+
"Counter": "0,1,2,3",
900
812
"EventCode": "0xB7, 0xBB",
901
813
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
902
814
"MSRIndex": "0x1a6,0x1a7",
···
907
817
},
908
818
{
909
819
"BriefDescription": "Counts any other requests",
820
+
"Counter": "0,1,2,3",
910
821
"EventCode": "0xB7, 0xBB",
911
822
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
912
823
"MSRIndex": "0x1a6,0x1a7",
···
917
826
},
918
827
{
919
828
"BriefDescription": "Counts any other requests",
829
+
"Counter": "0,1,2,3",
920
830
"EventCode": "0xB7, 0xBB",
921
831
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
922
832
"MSRIndex": "0x1a6,0x1a7",
···
927
835
},
928
836
{
929
837
"BriefDescription": "Counts any other requests",
838
+
"Counter": "0,1,2,3",
930
839
"EventCode": "0xB7, 0xBB",
931
840
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
932
841
"MSRIndex": "0x1a6,0x1a7",
···
937
844
},
938
845
{
939
846
"BriefDescription": "Counts any other requests",
847
+
"Counter": "0,1,2,3",
940
848
"EventCode": "0xB7, 0xBB",
941
849
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
942
850
"MSRIndex": "0x1a6,0x1a7",
···
947
853
},
948
854
{
949
855
"BriefDescription": "Counts any other requests",
856
+
"Counter": "0,1,2,3",
950
857
"EventCode": "0xB7, 0xBB",
951
858
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
952
859
"MSRIndex": "0x1a6,0x1a7",
···
957
862
},
958
863
{
959
864
"BriefDescription": "Counts any other requests",
865
+
"Counter": "0,1,2,3",
960
866
"EventCode": "0xB7, 0xBB",
961
867
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
962
868
"MSRIndex": "0x1a6,0x1a7",
···
967
871
},
968
872
{
969
873
"BriefDescription": "Counts any other requests",
874
+
"Counter": "0,1,2,3",
970
875
"EventCode": "0xB7, 0xBB",
971
876
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
972
877
"MSRIndex": "0x1a6,0x1a7",
···
977
880
},
978
881
{
979
882
"BriefDescription": "Counts any other requests",
883
+
"Counter": "0,1,2,3",
980
884
"EventCode": "0xB7, 0xBB",
981
885
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
982
886
"MSRIndex": "0x1a6,0x1a7",
···
987
889
},
988
890
{
989
891
"BriefDescription": "Counts any other requests",
892
+
"Counter": "0,1,2,3",
990
893
"EventCode": "0xB7, 0xBB",
991
894
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
992
895
"MSRIndex": "0x1a6,0x1a7",
···
997
898
},
998
899
{
999
900
"BriefDescription": "Counts any other requests",
901
+
"Counter": "0,1,2,3",
1000
902
"EventCode": "0xB7, 0xBB",
1001
903
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
1002
904
"MSRIndex": "0x1a6,0x1a7",
···
1007
907
},
1008
908
{
1009
909
"BriefDescription": "Counts any other requests",
910
+
"Counter": "0,1,2,3",
1010
911
"EventCode": "0xB7, 0xBB",
1011
912
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
1012
913
"MSRIndex": "0x1a6,0x1a7",
···
1017
916
},
1018
917
{
1019
918
"BriefDescription": "Counts any other requests",
919
+
"Counter": "0,1,2,3",
1020
920
"EventCode": "0xB7, 0xBB",
1021
921
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1022
922
"MSRIndex": "0x1a6,0x1a7",
···
1027
925
},
1028
926
{
1029
927
"BriefDescription": "Counts any other requests",
928
+
"Counter": "0,1,2,3",
1030
929
"EventCode": "0xB7, 0xBB",
1031
930
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1032
931
"MSRIndex": "0x1a6,0x1a7",
···
1037
934
},
1038
935
{
1039
936
"BriefDescription": "Counts any other requests",
937
+
"Counter": "0,1,2,3",
1040
938
"EventCode": "0xB7, 0xBB",
1041
939
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1042
940
"MSRIndex": "0x1a6,0x1a7",
···
1047
943
},
1048
944
{
1049
945
"BriefDescription": "Counts any other requests",
946
+
"Counter": "0,1,2,3",
1050
947
"EventCode": "0xB7, 0xBB",
1051
948
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1052
949
"MSRIndex": "0x1a6,0x1a7",
···
1057
952
},
1058
953
{
1059
954
"BriefDescription": "Counts any other requests",
955
+
"Counter": "0,1,2,3",
1060
956
"EventCode": "0xB7, 0xBB",
1061
957
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1062
958
"MSRIndex": "0x1a6,0x1a7",
···
1067
961
},
1068
962
{
1069
963
"BriefDescription": "Counts any other requests",
964
+
"Counter": "0,1,2,3",
1070
965
"EventCode": "0xB7, 0xBB",
1071
966
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1072
967
"MSRIndex": "0x1a6,0x1a7",
···
1077
970
},
1078
971
{
1079
972
"BriefDescription": "Counts any other requests",
973
+
"Counter": "0,1,2,3",
1080
974
"EventCode": "0xB7, 0xBB",
1081
975
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1082
976
"MSRIndex": "0x1a6,0x1a7",
···
1087
979
},
1088
980
{
1089
981
"BriefDescription": "Counts any other requests",
982
+
"Counter": "0,1,2,3",
1090
983
"EventCode": "0xB7, 0xBB",
1091
984
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
1092
985
"MSRIndex": "0x1a6,0x1a7",
···
1097
988
},
1098
989
{
1099
990
"BriefDescription": "Counts any other requests",
991
+
"Counter": "0,1,2,3",
1100
992
"EventCode": "0xB7, 0xBB",
1101
993
"EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
1102
994
"MSRIndex": "0x1a6,0x1a7",
···
1107
997
},
1108
998
{
1109
999
"BriefDescription": "Counts any other requests",
1000
+
"Counter": "0,1,2,3",
1110
1001
"EventCode": "0xB7, 0xBB",
1111
1002
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
1112
1003
"MSRIndex": "0x1a6,0x1a7",
···
1117
1006
},
1118
1007
{
1119
1008
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
1009
+
"Counter": "0,1,2,3",
1120
1010
"EventCode": "0xC9",
1121
1011
"EventName": "RTM_RETIRED.ABORTED",
1122
1012
"PEBS": "2",
···
1127
1015
},
1128
1016
{
1129
1017
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
1018
+
"Counter": "0,1,2,3",
1130
1019
"EventCode": "0xC9",
1131
1020
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
1132
1021
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
···
1136
1023
},
1137
1024
{
1138
1025
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
1026
+
"Counter": "0,1,2,3",
1139
1027
"EventCode": "0xC9",
1140
1028
"EventName": "RTM_RETIRED.ABORTED_MEM",
1141
1029
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
···
1145
1031
},
1146
1032
{
1147
1033
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
1034
+
"Counter": "0,1,2,3",
1148
1035
"EventCode": "0xC9",
1149
1036
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
1150
1037
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
···
1154
1039
},
1155
1040
{
1156
1041
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
1042
+
"Counter": "0,1,2,3",
1157
1043
"EventCode": "0xC9",
1158
1044
"EventName": "RTM_RETIRED.ABORTED_TIMER",
1159
1045
"SampleAfterValue": "2000003",
···
1162
1046
},
1163
1047
{
1164
1048
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
1049
+
"Counter": "0,1,2,3",
1165
1050
"EventCode": "0xC9",
1166
1051
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
1167
1052
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
···
1171
1054
},
1172
1055
{
1173
1056
"BriefDescription": "Number of times an RTM execution successfully committed",
1057
+
"Counter": "0,1,2,3",
1174
1058
"EventCode": "0xC9",
1175
1059
"EventName": "RTM_RETIRED.COMMIT",
1176
1060
"PublicDescription": "Number of times RTM commit succeeded.",
···
1180
1062
},
1181
1063
{
1182
1064
"BriefDescription": "Number of times an RTM execution started.",
1065
+
"Counter": "0,1,2,3",
1183
1066
"EventCode": "0xC9",
1184
1067
"EventName": "RTM_RETIRED.START",
1185
1068
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
···
1189
1070
},
1190
1071
{
1191
1072
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1073
+
"Counter": "0,1,2,3",
1192
1074
"EventCode": "0x5d",
1193
1075
"EventName": "TX_EXEC.MISC1",
1194
1076
"SampleAfterValue": "2000003",
···
1197
1077
},
1198
1078
{
1199
1079
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1080
+
"Counter": "0,1,2,3",
1200
1081
"EventCode": "0x5d",
1201
1082
"EventName": "TX_EXEC.MISC2",
1202
1083
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
···
1206
1085
},
1207
1086
{
1208
1087
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1088
+
"Counter": "0,1,2,3",
1209
1089
"EventCode": "0x5d",
1210
1090
"EventName": "TX_EXEC.MISC3",
1211
1091
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
···
1215
1093
},
1216
1094
{
1217
1095
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1096
+
"Counter": "0,1,2,3",
1218
1097
"EventCode": "0x5d",
1219
1098
"EventName": "TX_EXEC.MISC4",
1220
1099
"PublicDescription": "RTM region detected inside HLE.",
···
1224
1101
},
1225
1102
{
1226
1103
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1104
+
"Counter": "0,1,2,3",
1227
1105
"EventCode": "0x5d",
1228
1106
"EventName": "TX_EXEC.MISC5",
1229
1107
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
···
1233
1109
},
1234
1110
{
1235
1111
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1112
+
"Counter": "0,1,2,3",
1236
1113
"EventCode": "0x54",
1237
1114
"EventName": "TX_MEM.ABORT_CAPACITY",
1238
1115
"SampleAfterValue": "2000003",
···
1241
1116
},
1242
1117
{
1243
1118
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1119
+
"Counter": "0,1,2,3",
1244
1120
"EventCode": "0x54",
1245
1121
"EventName": "TX_MEM.ABORT_CONFLICT",
1246
1122
"PublicDescription": "Number of times a TSX line had a cache conflict.",
···
1250
1124
},
1251
1125
{
1252
1126
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1127
+
"Counter": "0,1,2,3",
1253
1128
"EventCode": "0x54",
1254
1129
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1255
1130
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
···
1259
1132
},
1260
1133
{
1261
1134
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1135
+
"Counter": "0,1,2,3",
1262
1136
"EventCode": "0x54",
1263
1137
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1264
1138
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
···
1268
1140
},
1269
1141
{
1270
1142
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1143
+
"Counter": "0,1,2,3",
1271
1144
"EventCode": "0x54",
1272
1145
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1273
1146
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
···
1277
1148
},
1278
1149
{
1279
1150
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1151
+
"Counter": "0,1,2,3",
1280
1152
"EventCode": "0x54",
1281
1153
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1282
1154
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
···
1286
1156
},
1287
1157
{
1288
1158
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1159
+
"Counter": "0,1,2,3",
1289
1160
"EventCode": "0x54",
1290
1161
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1291
1162
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
+13
tools/perf/pmu-events/arch/x86/skylake/metricgroups.json
+13
tools/perf/pmu-events/arch/x86/skylake/metricgroups.json
···
5
5
"BigFootprint": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
6
6
"BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
7
7
"Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
8
+
"BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
9
+
"BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
10
+
"BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
11
+
"BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
12
+
"BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
13
+
"BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
14
+
"BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
15
+
"BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
16
+
"BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
17
+
"BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
18
+
"BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
19
+
"BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
8
20
"CacheHits": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
21
+
"CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
9
22
"CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
10
23
"Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
11
24
"Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
+2
tools/perf/pmu-events/arch/x86/skylake/other.json
+2
tools/perf/pmu-events/arch/x86/skylake/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Number of hardware interrupts received by the processor.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0xCB",
5
6
"EventName": "HW_INTERRUPTS.RECEIVED",
6
7
"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0x09",
14
14
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
15
15
"SampleAfterValue": "2000003",
+102
-1
tools/perf/pmu-events/arch/x86/skylake/pipeline.json
+102
-1
tools/perf/pmu-events/arch/x86/skylake/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
4
+
"Counter": "0,1,2,3",
4
5
"CounterMask": "1",
5
6
"EventCode": "0x14",
6
7
"EventName": "ARITH.DIVIDER_ACTIVE",
···
10
9
},
11
10
{
12
11
"BriefDescription": "All (macro) branch instructions retired.",
12
+
"Counter": "0,1,2,3",
13
13
"Errata": "SKL091",
14
14
"EventCode": "0xC4",
15
15
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
···
19
17
},
20
18
{
21
19
"BriefDescription": "All (macro) branch instructions retired.",
20
+
"Counter": "0,1,2,3",
22
21
"Errata": "SKL091",
23
22
"EventCode": "0xC4",
24
23
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
···
30
27
},
31
28
{
32
29
"BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]",
30
+
"Counter": "0,1,2,3",
33
31
"Errata": "SKL091",
34
32
"EventCode": "0xC4",
35
33
"EventName": "BR_INST_RETIRED.COND",
···
40
36
},
41
37
{
42
38
"BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]",
39
+
"Counter": "0,1,2,3",
43
40
"Errata": "SKL091",
44
41
"EventCode": "0xC4",
45
42
"EventName": "BR_INST_RETIRED.CONDITIONAL",
···
51
46
},
52
47
{
53
48
"BriefDescription": "Not taken branch instructions retired.",
49
+
"Counter": "0,1,2,3",
54
50
"Errata": "SKL091",
55
51
"EventCode": "0xc4",
56
52
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
···
61
55
},
62
56
{
63
57
"BriefDescription": "Far branch instructions retired.",
58
+
"Counter": "0,1,2,3",
64
59
"Errata": "SKL091",
65
60
"EventCode": "0xC4",
66
61
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
···
72
65
},
73
66
{
74
67
"BriefDescription": "Direct and indirect near call instructions retired.",
68
+
"Counter": "0,1,2,3",
75
69
"Errata": "SKL091",
76
70
"EventCode": "0xC4",
77
71
"EventName": "BR_INST_RETIRED.NEAR_CALL",
···
83
75
},
84
76
{
85
77
"BriefDescription": "Return instructions retired.",
78
+
"Counter": "0,1,2,3",
86
79
"Errata": "SKL091",
87
80
"EventCode": "0xC4",
88
81
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
···
94
85
},
95
86
{
96
87
"BriefDescription": "Taken branch instructions retired.",
88
+
"Counter": "0,1,2,3",
97
89
"Errata": "SKL091",
98
90
"EventCode": "0xC4",
99
91
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
···
105
95
},
106
96
{
107
97
"BriefDescription": "Not taken branch instructions retired.",
98
+
"Counter": "0,1,2,3",
108
99
"Errata": "SKL091",
109
100
"EventCode": "0xC4",
110
101
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
···
115
104
},
116
105
{
117
106
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
107
+
"Counter": "0,1,2,3",
118
108
"EventCode": "0x89",
119
109
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
120
110
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
···
124
112
},
125
113
{
126
114
"BriefDescription": "Speculative mispredicted indirect branches",
115
+
"Counter": "0,1,2,3",
127
116
"EventCode": "0x89",
128
117
"EventName": "BR_MISP_EXEC.INDIRECT",
129
118
"PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
···
133
120
},
134
121
{
135
122
"BriefDescription": "All mispredicted macro branch instructions retired.",
123
+
"Counter": "0,1,2,3",
136
124
"EventCode": "0xC5",
137
125
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
138
126
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
···
141
127
},
142
128
{
143
129
"BriefDescription": "Mispredicted macro branch instructions retired.",
130
+
"Counter": "0,1,2,3",
144
131
"EventCode": "0xC5",
145
132
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
146
133
"PEBS": "2",
···
151
136
},
152
137
{
153
138
"BriefDescription": "Mispredicted conditional branch instructions retired.",
139
+
"Counter": "0,1,2,3",
154
140
"EventCode": "0xC5",
155
141
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
156
142
"PEBS": "1",
···
161
145
},
162
146
{
163
147
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
148
+
"Counter": "0,1,2,3",
164
149
"EventCode": "0xC5",
165
150
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
166
151
"PEBS": "1",
···
171
154
},
172
155
{
173
156
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
157
+
"Counter": "0,1,2,3",
174
158
"EventCode": "0xC5",
175
159
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
176
160
"PEBS": "1",
···
180
162
},
181
163
{
182
164
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
165
+
"Counter": "0,1,2,3",
183
166
"EventCode": "0x3C",
184
167
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
185
168
"SampleAfterValue": "25003",
···
188
169
},
189
170
{
190
171
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
172
+
"Counter": "0,1,2,3",
191
173
"EventCode": "0x3C",
192
174
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
193
175
"SampleAfterValue": "25003",
···
197
177
{
198
178
"AnyThread": "1",
199
179
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
180
+
"Counter": "0,1,2,3",
200
181
"EventCode": "0x3C",
201
182
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
202
183
"SampleAfterValue": "25003",
···
205
184
},
206
185
{
207
186
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
187
+
"Counter": "0,1,2,3",
208
188
"EventCode": "0x3C",
209
189
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
210
190
"SampleAfterValue": "25003",
···
213
191
},
214
192
{
215
193
"BriefDescription": "Reference cycles when the core is not in halt state.",
194
+
"Counter": "Fixed counter 2",
216
195
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
217
196
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
218
197
"SampleAfterValue": "2000003",
···
221
198
},
222
199
{
223
200
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
201
+
"Counter": "0,1,2,3",
224
202
"EventCode": "0x3C",
225
203
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
226
204
"SampleAfterValue": "25003",
···
230
206
{
231
207
"AnyThread": "1",
232
208
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
209
+
"Counter": "0,1,2,3",
233
210
"EventCode": "0x3C",
234
211
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
235
212
"SampleAfterValue": "25003",
···
238
213
},
239
214
{
240
215
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
216
+
"Counter": "0,1,2,3",
241
217
"CounterMask": "1",
242
218
"EdgeDetect": "1",
243
219
"EventCode": "0x3C",
···
248
222
},
249
223
{
250
224
"BriefDescription": "Core cycles when the thread is not in halt state",
225
+
"Counter": "Fixed counter 1",
251
226
"EventName": "CPU_CLK_UNHALTED.THREAD",
252
227
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
253
228
"SampleAfterValue": "2000003",
···
257
230
{
258
231
"AnyThread": "1",
259
232
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
233
+
"Counter": "Fixed counter 1",
260
234
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
261
235
"SampleAfterValue": "2000003",
262
236
"UMask": "0x2"
263
237
},
264
238
{
265
239
"BriefDescription": "Thread cycles when thread is not in halt state",
240
+
"Counter": "0,1,2,3",
266
241
"EventCode": "0x3C",
267
242
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
268
243
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
···
273
244
{
274
245
"AnyThread": "1",
275
246
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
247
+
"Counter": "0,1,2,3",
276
248
"EventCode": "0x3C",
277
249
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
278
250
"SampleAfterValue": "2000003"
279
251
},
280
252
{
281
253
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
254
+
"Counter": "0,1,2,3",
282
255
"CounterMask": "8",
283
256
"EventCode": "0xA3",
284
257
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
···
289
258
},
290
259
{
291
260
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
261
+
"Counter": "0,1,2,3",
292
262
"CounterMask": "1",
293
263
"EventCode": "0xA3",
294
264
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
···
298
266
},
299
267
{
300
268
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
269
+
"Counter": "0,1,2,3",
301
270
"CounterMask": "16",
302
271
"EventCode": "0xA3",
303
272
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
···
307
274
},
308
275
{
309
276
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
277
+
"Counter": "0,1,2,3",
310
278
"CounterMask": "12",
311
279
"EventCode": "0xA3",
312
280
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
···
316
282
},
317
283
{
318
284
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
285
+
"Counter": "0,1,2,3",
319
286
"CounterMask": "5",
320
287
"EventCode": "0xA3",
321
288
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
···
325
290
},
326
291
{
327
292
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
293
+
"Counter": "0,1,2,3",
328
294
"CounterMask": "20",
329
295
"EventCode": "0xA3",
330
296
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
···
334
298
},
335
299
{
336
300
"BriefDescription": "Total execution stalls.",
301
+
"Counter": "0,1,2,3",
337
302
"CounterMask": "4",
338
303
"EventCode": "0xA3",
339
304
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
···
343
306
},
344
307
{
345
308
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
309
+
"Counter": "0,1,2,3",
346
310
"EventCode": "0xA6",
347
311
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
348
312
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
···
352
314
},
353
315
{
354
316
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
317
+
"Counter": "0,1,2,3",
355
318
"EventCode": "0xA6",
356
319
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
357
320
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
···
361
322
},
362
323
{
363
324
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
325
+
"Counter": "0,1,2,3",
364
326
"EventCode": "0xA6",
365
327
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
366
328
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
···
370
330
},
371
331
{
372
332
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
333
+
"Counter": "0,1,2,3",
373
334
"EventCode": "0xA6",
374
335
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
375
336
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
···
379
338
},
380
339
{
381
340
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
341
+
"Counter": "0,1,2,3",
382
342
"EventCode": "0xA6",
383
343
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
384
344
"SampleAfterValue": "2000003",
···
387
345
},
388
346
{
389
347
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
348
+
"Counter": "0,1,2,3",
390
349
"EventCode": "0xA6",
391
350
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
392
351
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
···
396
353
},
397
354
{
398
355
"BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
356
+
"Counter": "0,1,2,3",
399
357
"EventCode": "0x87",
400
358
"EventName": "ILD_STALL.LCP",
401
359
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
···
405
361
},
406
362
{
407
363
"BriefDescription": "Instruction decoders utilized in a cycle",
364
+
"Counter": "0,1,2,3",
408
365
"EventCode": "0x55",
409
366
"EventName": "INST_DECODED.DECODERS",
410
367
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
···
414
369
},
415
370
{
416
371
"BriefDescription": "Instructions retired from execution.",
372
+
"Counter": "Fixed counter 0",
417
373
"EventName": "INST_RETIRED.ANY",
418
374
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
419
375
"SampleAfterValue": "2000003",
···
422
376
},
423
377
{
424
378
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
379
+
"Counter": "0,1,2,3",
425
380
"Errata": "SKL091, SKL044",
426
381
"EventCode": "0xC0",
427
382
"EventName": "INST_RETIRED.ANY_P",
···
431
384
},
432
385
{
433
386
"BriefDescription": "Number of all retired NOP instructions.",
387
+
"Counter": "0,1,2,3",
434
388
"Errata": "SKL091, SKL044",
435
389
"EventCode": "0xC0",
436
390
"EventName": "INST_RETIRED.NOP",
437
-
"PEBS": "2",
391
+
"PEBS": "1",
438
392
"SampleAfterValue": "2000003",
439
393
"UMask": "0x2"
440
394
},
441
395
{
442
396
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
397
+
"Counter": "1",
443
398
"Errata": "SKL091, SKL044",
444
399
"EventCode": "0xC0",
445
400
"EventName": "INST_RETIRED.PREC_DIST",
···
452
403
},
453
404
{
454
405
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
406
+
"Counter": "0,2,3",
455
407
"CounterMask": "10",
456
408
"Errata": "SKL091, SKL044",
457
409
"EventCode": "0xC0",
···
465
415
},
466
416
{
467
417
"BriefDescription": "Clears speculative count",
418
+
"Counter": "0,1,2,3",
468
419
"CounterMask": "1",
469
420
"EdgeDetect": "1",
470
421
"EventCode": "0x0D",
···
476
425
},
477
426
{
478
427
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
428
+
"Counter": "0,1,2,3",
479
429
"EventCode": "0x0D",
480
430
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
481
431
"SampleAfterValue": "2000003",
···
484
432
},
485
433
{
486
434
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
435
+
"Counter": "0,1,2,3",
487
436
"EventCode": "0x0D",
488
437
"EventName": "INT_MISC.RECOVERY_CYCLES",
489
438
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
···
494
441
{
495
442
"AnyThread": "1",
496
443
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
444
+
"Counter": "0,1,2,3",
497
445
"EventCode": "0x0D",
498
446
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
499
447
"SampleAfterValue": "2000003",
···
502
448
},
503
449
{
504
450
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
451
+
"Counter": "0,1,2,3",
505
452
"EventCode": "0x03",
506
453
"EventName": "LD_BLOCKS.NO_SR",
507
454
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
···
511
456
},
512
457
{
513
458
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
459
+
"Counter": "0,1,2,3",
514
460
"EventCode": "0x03",
515
461
"EventName": "LD_BLOCKS.STORE_FORWARD",
516
462
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
···
520
464
},
521
465
{
522
466
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
467
+
"Counter": "0,1,2,3",
523
468
"EventCode": "0x07",
524
469
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
525
470
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
···
529
472
},
530
473
{
531
474
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
475
+
"Counter": "0,1,2,3",
532
476
"EventCode": "0x4C",
533
477
"EventName": "LOAD_HIT_PRE.SW_PF",
534
478
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
···
538
480
},
539
481
{
540
482
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]",
483
+
"Counter": "0,1,2,3",
541
484
"CounterMask": "4",
542
485
"EventCode": "0xA8",
543
486
"EventName": "LSD.CYCLES_4_UOPS",
···
548
489
},
549
490
{
550
491
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
492
+
"Counter": "0,1,2,3",
551
493
"CounterMask": "1",
552
494
"EventCode": "0xA8",
553
495
"EventName": "LSD.CYCLES_ACTIVE",
···
558
498
},
559
499
{
560
500
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]",
501
+
"Counter": "0,1,2,3",
561
502
"CounterMask": "4",
562
503
"EventCode": "0xA8",
563
504
"EventName": "LSD.CYCLES_OK",
···
568
507
},
569
508
{
570
509
"BriefDescription": "Number of Uops delivered by the LSD.",
510
+
"Counter": "0,1,2,3",
571
511
"EventCode": "0xA8",
572
512
"EventName": "LSD.UOPS",
573
513
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
···
577
515
},
578
516
{
579
517
"BriefDescription": "Number of machine clears (nukes) of any type.",
518
+
"Counter": "0,1,2,3",
580
519
"CounterMask": "1",
581
520
"EdgeDetect": "1",
582
521
"EventCode": "0xC3",
···
587
524
},
588
525
{
589
526
"BriefDescription": "Self-modifying code (SMC) detected.",
527
+
"Counter": "0,1,2,3",
590
528
"EventCode": "0xC3",
591
529
"EventName": "MACHINE_CLEARS.SMC",
592
530
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
···
596
532
},
597
533
{
598
534
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
535
+
"Counter": "0,1,2,3",
599
536
"EventCode": "0xC1",
600
537
"EventName": "OTHER_ASSISTS.ANY",
601
538
"SampleAfterValue": "100003",
···
604
539
},
605
540
{
606
541
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
542
+
"Counter": "0,1,2,3",
607
543
"EventCode": "0x59",
608
544
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
609
545
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
···
613
547
},
614
548
{
615
549
"BriefDescription": "Resource-related stall cycles",
550
+
"Counter": "0,1,2,3",
616
551
"EventCode": "0xa2",
617
552
"EventName": "RESOURCE_STALLS.ANY",
618
553
"PublicDescription": "Counts resource-related stall cycles.",
···
622
555
},
623
556
{
624
557
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
558
+
"Counter": "0,1,2,3",
625
559
"EventCode": "0xA2",
626
560
"EventName": "RESOURCE_STALLS.SB",
627
561
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
···
631
563
},
632
564
{
633
565
"BriefDescription": "Increments whenever there is an update to the LBR array.",
566
+
"Counter": "0,1,2,3",
634
567
"EventCode": "0xCC",
635
568
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
636
569
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
···
640
571
},
641
572
{
642
573
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
574
+
"Counter": "0,1,2,3",
643
575
"EventCode": "0xCC",
644
576
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
645
577
"SampleAfterValue": "2000003",
···
648
578
},
649
579
{
650
580
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
581
+
"Counter": "0,1,2,3",
651
582
"EventCode": "0x5E",
652
583
"EventName": "RS_EVENTS.EMPTY_CYCLES",
653
584
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
···
657
586
},
658
587
{
659
588
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
589
+
"Counter": "0,1,2,3",
660
590
"CounterMask": "1",
661
591
"EdgeDetect": "1",
662
592
"EventCode": "0x5E",
···
669
597
},
670
598
{
671
599
"BriefDescription": "Cycles per thread when uops are executed in port 0",
600
+
"Counter": "0,1,2,3",
672
601
"EventCode": "0xA1",
673
602
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
674
603
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
···
678
605
},
679
606
{
680
607
"BriefDescription": "Cycles per thread when uops are executed in port 1",
608
+
"Counter": "0,1,2,3",
681
609
"EventCode": "0xA1",
682
610
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
683
611
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
···
687
613
},
688
614
{
689
615
"BriefDescription": "Cycles per thread when uops are executed in port 2",
616
+
"Counter": "0,1,2,3",
690
617
"EventCode": "0xA1",
691
618
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
692
619
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
···
696
621
},
697
622
{
698
623
"BriefDescription": "Cycles per thread when uops are executed in port 3",
624
+
"Counter": "0,1,2,3",
699
625
"EventCode": "0xA1",
700
626
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
701
627
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
···
705
629
},
706
630
{
707
631
"BriefDescription": "Cycles per thread when uops are executed in port 4",
632
+
"Counter": "0,1,2,3",
708
633
"EventCode": "0xA1",
709
634
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
710
635
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
···
714
637
},
715
638
{
716
639
"BriefDescription": "Cycles per thread when uops are executed in port 5",
640
+
"Counter": "0,1,2,3",
717
641
"EventCode": "0xA1",
718
642
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
719
643
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
···
723
645
},
724
646
{
725
647
"BriefDescription": "Cycles per thread when uops are executed in port 6",
648
+
"Counter": "0,1,2,3",
726
649
"EventCode": "0xA1",
727
650
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
728
651
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
···
732
653
},
733
654
{
734
655
"BriefDescription": "Cycles per thread when uops are executed in port 7",
656
+
"Counter": "0,1,2,3",
735
657
"EventCode": "0xA1",
736
658
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
737
659
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
···
741
661
},
742
662
{
743
663
"BriefDescription": "Number of uops executed on the core.",
664
+
"Counter": "0,1,2,3",
744
665
"EventCode": "0xB1",
745
666
"EventName": "UOPS_EXECUTED.CORE",
746
667
"PublicDescription": "Number of uops executed from any thread.",
···
750
669
},
751
670
{
752
671
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
672
+
"Counter": "0,1,2,3",
753
673
"CounterMask": "1",
754
674
"EventCode": "0xB1",
755
675
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
···
759
677
},
760
678
{
761
679
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
680
+
"Counter": "0,1,2,3",
762
681
"CounterMask": "2",
763
682
"EventCode": "0xB1",
764
683
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
···
768
685
},
769
686
{
770
687
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
688
+
"Counter": "0,1,2,3",
771
689
"CounterMask": "3",
772
690
"EventCode": "0xB1",
773
691
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
···
777
693
},
778
694
{
779
695
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
696
+
"Counter": "0,1,2,3",
780
697
"CounterMask": "4",
781
698
"EventCode": "0xB1",
782
699
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
···
786
701
},
787
702
{
788
703
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
704
+
"Counter": "0,1,2,3",
789
705
"CounterMask": "1",
790
706
"EventCode": "0xB1",
791
707
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
···
796
710
},
797
711
{
798
712
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
713
+
"Counter": "0,1,2,3",
799
714
"CounterMask": "1",
800
715
"EventCode": "0xB1",
801
716
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
···
806
719
},
807
720
{
808
721
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
722
+
"Counter": "0,1,2,3",
809
723
"CounterMask": "2",
810
724
"EventCode": "0xB1",
811
725
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
···
816
728
},
817
729
{
818
730
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
731
+
"Counter": "0,1,2,3",
819
732
"CounterMask": "3",
820
733
"EventCode": "0xB1",
821
734
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
···
826
737
},
827
738
{
828
739
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
740
+
"Counter": "0,1,2,3",
829
741
"CounterMask": "4",
830
742
"EventCode": "0xB1",
831
743
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
···
836
746
},
837
747
{
838
748
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
749
+
"Counter": "0,1,2,3",
839
750
"CounterMask": "1",
840
751
"EventCode": "0xB1",
841
752
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
···
847
756
},
848
757
{
849
758
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
759
+
"Counter": "0,1,2,3",
850
760
"EventCode": "0xB1",
851
761
"EventName": "UOPS_EXECUTED.THREAD",
852
762
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
···
856
764
},
857
765
{
858
766
"BriefDescription": "Counts the number of x87 uops dispatched.",
767
+
"Counter": "0,1,2,3",
859
768
"EventCode": "0xB1",
860
769
"EventName": "UOPS_EXECUTED.X87",
861
770
"PublicDescription": "Counts the number of x87 uops executed.",
···
865
772
},
866
773
{
867
774
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
775
+
"Counter": "0,1,2,3",
868
776
"EventCode": "0x0E",
869
777
"EventName": "UOPS_ISSUED.ANY",
870
778
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
···
874
780
},
875
781
{
876
782
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
783
+
"Counter": "0,1,2,3",
877
784
"EventCode": "0x0E",
878
785
"EventName": "UOPS_ISSUED.SLOW_LEA",
879
786
"SampleAfterValue": "2000003",
···
882
787
},
883
788
{
884
789
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
790
+
"Counter": "0,1,2,3",
885
791
"CounterMask": "1",
886
792
"EventCode": "0x0E",
887
793
"EventName": "UOPS_ISSUED.STALL_CYCLES",
···
893
797
},
894
798
{
895
799
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
800
+
"Counter": "0,1,2,3",
896
801
"EventCode": "0x0E",
897
802
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
898
803
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
···
902
805
},
903
806
{
904
807
"BriefDescription": "Number of macro-fused uops retired. (non precise)",
808
+
"Counter": "0,1,2,3",
905
809
"EventCode": "0xc2",
906
810
"EventName": "UOPS_RETIRED.MACRO_FUSED",
907
811
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
···
911
813
},
912
814
{
913
815
"BriefDescription": "Retirement slots used.",
816
+
"Counter": "0,1,2,3",
914
817
"EventCode": "0xC2",
915
818
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
916
819
"PublicDescription": "Counts the retirement slots used.",
···
920
821
},
921
822
{
922
823
"BriefDescription": "Cycles without actually retired uops.",
824
+
"Counter": "0,1,2,3",
923
825
"CounterMask": "1",
924
826
"EventCode": "0xC2",
925
827
"EventName": "UOPS_RETIRED.STALL_CYCLES",
···
931
831
},
932
832
{
933
833
"BriefDescription": "Cycles with less than 10 actually retired uops.",
834
+
"Counter": "0,1,2,3",
934
835
"CounterMask": "16",
935
836
"EventCode": "0xC2",
936
837
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
+117
-79
tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
+117
-79
tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json
···
89
89
{
90
90
"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
91
91
"MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_thread_slots",
92
-
"MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
92
+
"MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
93
93
"MetricName": "tma_assists",
94
94
"MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
95
95
"PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
···
98
98
{
99
99
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
100
100
"MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_thread_slots",
101
-
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
101
+
"MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group",
102
102
"MetricName": "tma_backend_bound",
103
103
"MetricThreshold": "tma_backend_bound > 0.2",
104
104
"MetricgroupNoGroup": "TopdownL1",
···
119
119
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
120
120
"MetricConstraint": "NO_GROUP_EVENTS",
121
121
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
122
-
"MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
122
+
"MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
123
123
"MetricName": "tma_branch_mispredicts",
124
124
"MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
125
125
"MetricgroupNoGroup": "TopdownL2",
···
157
157
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
158
158
"MetricConstraint": "NO_GROUP_EVENTS",
159
159
"MetricExpr": "(18.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
160
-
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
160
+
"MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
161
161
"MetricName": "tma_contested_accesses",
162
162
"MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
163
163
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache",
···
178
178
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
179
179
"MetricConstraint": "NO_GROUP_EVENTS",
180
180
"MetricExpr": "16.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks",
181
-
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
181
+
"MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group",
182
182
"MetricName": "tma_data_sharing",
183
183
"MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
184
184
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache",
···
196
196
{
197
197
"BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
198
198
"MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks",
199
-
"MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
199
+
"MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group",
200
200
"MetricName": "tma_divider",
201
201
"MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
202
202
"PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
···
227
227
"MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
228
228
"MetricName": "tma_dsb_switches",
229
229
"MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
230
-
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
230
+
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
231
231
"ScaleUnit": "100%"
232
232
},
233
233
{
234
234
"BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
235
235
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
236
236
"MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
237
-
"MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
237
+
"MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group",
238
238
"MetricName": "tma_dtlb_load",
239
239
"MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
240
240
"PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
···
243
243
{
244
244
"BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
245
245
"MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks",
246
-
"MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
246
+
"MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group",
247
247
"MetricName": "tma_dtlb_store",
248
248
"MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
249
249
"PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchronization",
···
253
253
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
254
254
"MetricConstraint": "NO_GROUP_EVENTS",
255
255
"MetricExpr": "22 * tma_info_system_core_frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks",
256
-
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
256
+
"MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group",
257
257
"MetricName": "tma_false_sharing",
258
258
"MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
259
259
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache",
···
263
263
"BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
264
264
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
265
265
"MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_thread_clks",
266
-
"MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
266
+
"MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group",
267
267
"MetricName": "tma_fb_full",
268
268
"MetricThreshold": "tma_fb_full > 0.3",
269
269
"PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores",
···
276
276
"MetricName": "tma_fetch_bandwidth",
277
277
"MetricThreshold": "tma_fetch_bandwidth > 0.2",
278
278
"MetricgroupNoGroup": "TopdownL2",
279
-
"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
279
+
"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp",
280
280
"ScaleUnit": "100%"
281
281
},
282
282
{
···
291
291
},
292
292
{
293
293
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
294
+
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
294
295
"MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
295
296
"MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0",
296
297
"MetricName": "tma_few_uops_instructions",
···
320
319
},
321
320
{
322
321
"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
323
-
"MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS",
322
+
"MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_SLOTS",
324
323
"MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
325
324
"MetricName": "tma_fp_scalar",
326
325
"MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
···
330
329
{
331
330
"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
332
331
"MetricConstraint": "NO_GROUP_EVENTS",
333
-
"MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS",
332
+
"MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_SLOTS",
334
333
"MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P",
335
334
"MetricName": "tma_fp_vector",
336
335
"MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)",
···
358
357
{
359
358
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
360
359
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots",
361
-
"MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group",
360
+
"MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group",
362
361
"MetricName": "tma_frontend_bound",
363
362
"MetricThreshold": "tma_frontend_bound > 0.15",
364
363
"MetricgroupNoGroup": "TopdownL1",
···
368
367
{
369
368
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
370
369
"MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
371
-
"MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
370
+
"MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
372
371
"MetricName": "tma_fused_instructions",
373
372
"MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6",
374
373
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}",
···
387
386
{
388
387
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
389
388
"MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_thread_clks",
390
-
"MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
389
+
"MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
391
390
"MetricName": "tma_icache_misses",
392
391
"MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
393
392
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
···
429
428
"MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5"
430
429
},
431
430
{
431
+
"BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck",
432
+
"MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite)))",
433
+
"MetricGroup": "DSB;FetchBW;tma_issueFB",
434
+
"MetricName": "tma_info_botlnk_l2_dsb_bandwidth",
435
+
"MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10",
436
+
"PublicDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
437
+
},
438
+
{
432
439
"BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck",
433
440
"MetricConstraint": "NO_GROUP_EVENTS",
434
441
"MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
435
442
"MetricGroup": "DSBmiss;Fed;tma_issueFB",
436
443
"MetricName": "tma_info_botlnk_l2_dsb_misses",
437
444
"MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10",
438
-
"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
445
+
"PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp"
439
446
},
440
447
{
441
448
"BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck",
···
454
445
"PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: "
455
446
},
456
447
{
457
-
"BriefDescription": "Total pipeline cost of \"useful operations\" - the baseline operations not covered by Branching_Overhead nor Irregular_Overhead.",
458
-
"MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
459
-
"MetricGroup": "Ret",
460
-
"MetricName": "tma_info_bottleneck_base_non_br",
461
-
"MetricThreshold": "tma_info_bottleneck_base_non_br > 20"
462
-
},
463
-
{
464
448
"BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
465
449
"MetricConstraint": "NO_GROUP_EVENTS",
466
450
"MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
467
-
"MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB",
451
+
"MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB",
468
452
"MetricName": "tma_info_bottleneck_big_code",
469
453
"MetricThreshold": "tma_info_bottleneck_big_code > 20"
470
454
},
471
455
{
472
-
"BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
473
-
"MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots)",
474
-
"MetricGroup": "Ret",
456
+
"BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA",
457
+
"MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)",
458
+
"MetricGroup": "BvBO;Ret",
475
459
"MetricName": "tma_info_bottleneck_branching_overhead",
476
-
"MetricThreshold": "tma_info_bottleneck_branching_overhead > 5"
460
+
"MetricThreshold": "tma_info_bottleneck_branching_overhead > 5",
461
+
"PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)"
477
462
},
478
463
{
479
464
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks",
480
-
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
481
-
"MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW",
465
+
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
466
+
"MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW",
482
467
"MetricName": "tma_info_bottleneck_cache_memory_bandwidth",
483
468
"MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 20",
484
469
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full"
485
470
},
486
471
{
487
472
"BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
488
-
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
489
-
"MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat",
473
+
"MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
474
+
"MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat",
490
475
"MetricName": "tma_info_bottleneck_cache_memory_latency",
491
476
"MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20",
492
477
"PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency"
···
488
485
{
489
486
"BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
490
487
"MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))",
491
-
"MetricGroup": "Cor;tma_issueComp",
488
+
"MetricGroup": "BvCB;Cor;tma_issueComp",
492
489
"MetricName": "tma_info_bottleneck_compute_bound_est",
493
490
"MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20",
494
491
"PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: "
495
492
},
496
493
{
497
-
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
494
+
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
498
495
"MetricConstraint": "NO_GROUP_EVENTS",
499
496
"MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code",
500
-
"MetricGroup": "Fed;FetchBW;Frontend",
497
+
"MetricGroup": "BvFB;Fed;FetchBW;Frontend",
501
498
"MetricName": "tma_info_bottleneck_instruction_fetch_bw",
502
499
"MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20"
503
500
},
504
501
{
505
502
"BriefDescription": "Total pipeline cost of irregular execution (e.g",
506
503
"MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
507
-
"MetricGroup": "Bad;Cor;Ret;tma_issueMS",
504
+
"MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS",
508
505
"MetricName": "tma_info_bottleneck_irregular_overhead",
509
506
"MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10",
510
507
"PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches"
···
512
509
{
513
510
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
514
511
"MetricConstraint": "NO_GROUP_EVENTS",
515
-
"MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
516
-
"MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB",
512
+
"MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
513
+
"MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB",
517
514
"MetricName": "tma_info_bottleneck_memory_data_tlbs",
518
515
"MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20",
519
516
"PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_synchronization"
···
521
518
{
522
519
"BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)",
523
520
"MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))",
524
-
"MetricGroup": "Mem;Offcore;tma_issueTLB",
521
+
"MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB",
525
522
"MetricName": "tma_info_bottleneck_memory_synchronization",
526
523
"MetricThreshold": "tma_info_bottleneck_memory_synchronization > 10",
527
524
"PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs"
···
530
527
"BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
531
528
"MetricConstraint": "NO_GROUP_EVENTS",
532
529
"MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
533
-
"MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM",
530
+
"MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM",
534
531
"MetricName": "tma_info_bottleneck_mispredictions",
535
532
"MetricThreshold": "tma_info_bottleneck_mispredictions > 20",
536
533
"PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers"
537
534
},
538
535
{
539
-
"BriefDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class)",
540
-
"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_base_non_br)",
541
-
"MetricGroup": "Cor;Offcore",
536
+
"BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
537
+
"MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bottleneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info_bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_latency + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_synchronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_irregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottleneck_useful_work)",
538
+
"MetricGroup": "BvOB;Cor;Offcore",
542
539
"MetricName": "tma_info_bottleneck_other_bottlenecks",
543
540
"MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20",
544
-
"PublicDescription": "Total pipeline cost of remaining bottlenecks (apart from those listed in the Info.Bottlenecks metrics class). Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
541
+
"PublicDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls."
542
+
},
543
+
{
544
+
"BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",
545
+
"MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
546
+
"MetricGroup": "BvUW;Ret",
547
+
"MetricName": "tma_info_bottleneck_useful_work",
548
+
"MetricThreshold": "tma_info_bottleneck_useful_work > 20"
545
549
},
546
550
{
547
551
"BriefDescription": "Fraction of branches that are CALL or RET",
···
602
592
},
603
593
{
604
594
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
605
-
"MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@) / (2 * tma_info_core_core_clks)",
595
+
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR) / (2 * tma_info_core_core_clks)",
606
596
"MetricGroup": "Cor;Flops;HPC",
607
597
"MetricName": "tma_info_core_fp_arith_utilization",
608
598
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
···
619
609
"MetricGroup": "DSB;Fed;FetchBW;tma_issueFB",
620
610
"MetricName": "tma_info_frontend_dsb_coverage",
621
611
"MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 4 > 0.35",
622
-
"PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
612
+
"PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp"
623
613
},
624
614
{
625
615
"BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
···
680
670
{
681
671
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
682
672
"MetricConstraint": "NO_GROUP_EVENTS",
683
-
"MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)",
673
+
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIRED.VECTOR)",
684
674
"MetricGroup": "Flops;InsType",
685
675
"MetricName": "tma_info_inst_mix_iparith",
686
676
"MetricThreshold": "tma_info_inst_mix_iparith < 10",
···
762
752
"MetricThreshold": "tma_info_inst_mix_ipswpf < 100"
763
753
},
764
754
{
765
-
"BriefDescription": "Instruction per taken branch",
755
+
"BriefDescription": "Instructions per taken branch",
766
756
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
767
757
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB",
768
758
"MetricName": "tma_info_inst_mix_iptb",
769
759
"MetricThreshold": "tma_info_inst_mix_iptb < 9",
770
-
"PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
760
+
"PublicDescription": "Instructions per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp"
771
761
},
772
762
{
773
763
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
···
800
790
"MetricName": "tma_info_memory_fb_hpki"
801
791
},
802
792
{
803
-
"BriefDescription": "",
793
+
"BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
804
794
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
805
795
"MetricGroup": "Mem;MemoryBW",
806
796
"MetricName": "tma_info_memory_l1d_cache_fill_bw"
···
818
808
"MetricName": "tma_info_memory_l1mpki_load"
819
809
},
820
810
{
821
-
"BriefDescription": "",
811
+
"BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
822
812
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
823
813
"MetricGroup": "Mem;MemoryBW",
824
814
"MetricName": "tma_info_memory_l2_cache_fill_bw"
···
854
844
"MetricName": "tma_info_memory_l2mpki_load"
855
845
},
856
846
{
857
-
"BriefDescription": "",
847
+
"BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs",
848
+
"MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.ANY",
849
+
"MetricGroup": "CacheMisses;Offcore",
850
+
"MetricName": "tma_info_memory_l2mpki_rfo"
851
+
},
852
+
{
853
+
"BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
858
854
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
859
855
"MetricGroup": "Mem;MemoryBW;Offcore",
860
856
"MetricName": "tma_info_memory_l3_cache_access_bw"
861
857
},
862
858
{
863
-
"BriefDescription": "",
859
+
"BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
864
860
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
865
861
"MetricGroup": "Mem;MemoryBW",
866
862
"MetricName": "tma_info_memory_l3_cache_fill_bw"
···
941
925
"MetricName": "tma_info_memory_tlb_store_stlb_mpki"
942
926
},
943
927
{
944
-
"BriefDescription": "",
928
+
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core",
945
929
"MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@)",
946
930
"MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
947
931
"MetricName": "tma_info_pipeline_execute"
932
+
},
933
+
{
934
+
"BriefDescription": "Average number of uops fetched from DSB per cycle",
935
+
"MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY",
936
+
"MetricGroup": "Fed;FetchBW",
937
+
"MetricName": "tma_info_pipeline_fetch_dsb"
938
+
},
939
+
{
940
+
"BriefDescription": "Average number of uops fetched from MITE per cycle",
941
+
"MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES",
942
+
"MetricGroup": "Fed;FetchBW",
943
+
"MetricName": "tma_info_pipeline_fetch_mite"
948
944
},
949
945
{
950
946
"BriefDescription": "Instructions per a microcode Assist invocation",
···
980
952
},
981
953
{
982
954
"BriefDescription": "Average CPU Utilization (percentage)",
983
-
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
955
+
"MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online",
984
956
"MetricGroup": "HPC;Summary",
985
957
"MetricName": "tma_info_system_cpu_utilization"
986
958
},
987
959
{
988
960
"BriefDescription": "Average number of utilized CPUs",
989
-
"MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization",
961
+
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
990
962
"MetricGroup": "Summary",
991
963
"MetricName": "tma_info_system_cpus_utilized"
992
964
},
···
1096
1068
"MetricThreshold": "tma_info_thread_uoppi > 1.05"
1097
1069
},
1098
1070
{
1099
-
"BriefDescription": "Instruction per taken branch",
1071
+
"BriefDescription": "Uops per taken branch",
1100
1072
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
1101
1073
"MetricGroup": "Branches;Fed;FetchBW",
1102
1074
"MetricName": "tma_info_thread_uptb",
···
1105
1077
{
1106
1078
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
1107
1079
"MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks",
1108
-
"MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
1080
+
"MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
1109
1081
"MetricName": "tma_itlb_misses",
1110
1082
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
1111
1083
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
···
1121
1093
"ScaleUnit": "100%"
1122
1094
},
1123
1095
{
1096
+
"BriefDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache",
1097
+
"MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETIRED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks",
1098
+
"MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound_group",
1099
+
"MetricName": "tma_l1_hit_latency",
1100
+
"MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1101
+
"PublicDescription": "This metric roughly estimates fraction of cycles with demand load accesses that hit the L1 cache. The short latency of the L1 data cache may be exposed in pointer-chasing memory access patterns as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT",
1102
+
"ScaleUnit": "100%"
1103
+
},
1104
+
{
1124
1105
"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
1125
1106
"MetricConstraint": "NO_GROUP_EVENTS",
1126
1107
"MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks)",
1127
-
"MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
1108
+
"MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
1128
1109
"MetricName": "tma_l2_bound",
1129
1110
"MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)",
1130
1111
"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
···
1151
1114
{
1152
1115
"BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
1153
1116
"MetricExpr": "6.5 * tma_info_system_core_frequency * (MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) / tma_info_thread_clks",
1154
-
"MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
1117
+
"MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group",
1155
1118
"MetricName": "tma_l3_hit_latency",
1156
1119
"MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1157
1120
"PublicDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_cache_memory_latency, tma_mem_latency",
···
1163
1126
"MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB",
1164
1127
"MetricName": "tma_lcp",
1165
1128
"MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
1166
-
"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
1129
+
"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb",
1167
1130
"ScaleUnit": "100%"
1168
1131
},
1169
1132
{
···
1208
1171
"MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group",
1209
1172
"MetricName": "tma_lock_latency",
1210
1173
"MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1211
-
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency",
1174
+
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS. Related metrics: tma_store_latency",
1212
1175
"ScaleUnit": "100%"
1213
1176
},
1214
1177
{
1215
1178
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
1216
1179
"MetricConstraint": "NO_GROUP_EVENTS",
1217
1180
"MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
1218
-
"MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
1181
+
"MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn",
1219
1182
"MetricName": "tma_machine_clears",
1220
1183
"MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15",
1221
1184
"MetricgroupNoGroup": "TopdownL2",
···
1225
1188
{
1226
1189
"BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM)",
1227
1190
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks",
1228
-
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
1191
+
"MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW",
1229
1192
"MetricName": "tma_mem_bandwidth",
1230
1193
"MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1231
1194
"PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full",
···
1234
1197
{
1235
1198
"BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM)",
1236
1199
"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth",
1237
-
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
1200
+
"MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat",
1238
1201
"MetricName": "tma_mem_latency",
1239
1202
"MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1240
1203
"PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_latency",
···
1261
1224
},
1262
1225
{
1263
1226
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
1227
+
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
1264
1228
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots",
1265
1229
"MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS",
1266
1230
"MetricName": "tma_microcode_sequencer",
···
1272
1234
{
1273
1235
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
1274
1236
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks",
1275
-
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
1237
+
"MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM",
1276
1238
"MetricName": "tma_mispredicts_resteers",
1277
1239
"MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
1278
1240
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions",
···
1308
1270
{
1309
1271
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
1310
1272
"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
1311
-
"MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
1273
+
"MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
1312
1274
"MetricName": "tma_non_fused_branches",
1313
1275
"MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6",
1314
1276
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
···
1317
1279
{
1318
1280
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
1319
1281
"MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
1320
-
"MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
1282
+
"MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_light_ops_group",
1321
1283
"MetricName": "tma_nop_instructions",
1322
1284
"MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_ops > 0.3 & tma_light_operations > 0.6)",
1323
1285
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
···
1335
1297
{
1336
1298
"BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).",
1337
1299
"MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.ALL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)",
1338
-
"MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
1300
+
"MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_branch_mispredicts_group",
1339
1301
"MetricName": "tma_other_mispredicts",
1340
1302
"MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15)",
1341
1303
"ScaleUnit": "100%"
···
1343
1305
{
1344
1306
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.",
1345
1307
"MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.COUNT), 0.0001)",
1346
-
"MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
1308
+
"MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_machine_clears_group",
1347
1309
"MetricName": "tma_other_nukes",
1348
1310
"MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears > 0.1 & tma_bad_speculation > 0.15)",
1349
1311
"ScaleUnit": "100%"
···
1431
1393
},
1432
1394
{
1433
1395
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
1434
-
"MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks",
1396
+
"MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_clks",
1435
1397
"MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
1436
1398
"MetricName": "tma_ports_utilized_0",
1437
1399
"MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
···
1459
1421
{
1460
1422
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
1461
1423
"MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks",
1462
-
"MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
1424
+
"MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
1463
1425
"MetricName": "tma_ports_utilized_3m",
1464
1426
"MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
1465
1427
"ScaleUnit": "100%"
···
1467
1429
{
1468
1430
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
1469
1431
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots",
1470
-
"MetricGroup": "TmaL1;TopdownL1;tma_L1_group",
1432
+
"MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group",
1471
1433
"MetricName": "tma_retiring",
1472
1434
"MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1",
1473
1435
"MetricgroupNoGroup": "TopdownL1",
···
1477
1439
{
1478
1440
"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
1479
1441
"MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clks",
1480
-
"MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
1442
+
"MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group;tma_issueSO",
1481
1443
"MetricName": "tma_serializing_operation",
1482
1444
"MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)",
1483
1445
"PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches",
···
1505
1467
{
1506
1468
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
1507
1469
"MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks",
1508
-
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
1470
+
"MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group",
1509
1471
"MetricName": "tma_sq_full",
1510
1472
"MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1511
1473
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth",
···
1533
1495
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
1534
1496
"MetricConstraint": "NO_GROUP_EVENTS_NMI",
1535
1497
"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks",
1536
-
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
1498
+
"MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group",
1537
1499
"MetricName": "tma_store_latency",
1538
1500
"MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))",
1539
1501
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency",
···
1566
1528
{
1567
1529
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
1568
1530
"MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks",
1569
-
"MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
1531
+
"MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
1570
1532
"MetricName": "tma_unknown_branches",
1571
1533
"MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
1572
1534
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches. Sample with: BACLEARS.ANY",
+23
tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
+23
tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x34",
5
6
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
6
7
"PerPkg": "1",
···
11
10
},
12
11
{
13
12
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
13
+
"Counter": "0,1",
14
14
"EventCode": "0x34",
15
15
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
16
16
"PerPkg": "1",
···
21
19
},
22
20
{
23
21
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
22
+
"Counter": "0,1",
24
23
"EventCode": "0x34",
25
24
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
26
25
"PerPkg": "1",
···
31
28
},
32
29
{
33
30
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
31
+
"Counter": "0,1",
34
32
"EventCode": "0x34",
35
33
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
36
34
"PerPkg": "1",
···
41
37
},
42
38
{
43
39
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
40
+
"Counter": "0,1",
44
41
"EventCode": "0x34",
45
42
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
46
43
"PerPkg": "1",
···
51
46
},
52
47
{
53
48
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
49
+
"Counter": "0,1",
54
50
"EventCode": "0x34",
55
51
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
56
52
"PerPkg": "1",
···
61
55
},
62
56
{
63
57
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
58
+
"Counter": "0,1",
64
59
"EventCode": "0x34",
65
60
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
66
61
"PerPkg": "1",
···
71
64
},
72
65
{
73
66
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
67
+
"Counter": "0,1",
74
68
"EventCode": "0x34",
75
69
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
76
70
"PerPkg": "1",
···
81
73
},
82
74
{
83
75
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
76
+
"Counter": "0,1",
84
77
"EventCode": "0x34",
85
78
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
86
79
"PerPkg": "1",
···
91
82
},
92
83
{
93
84
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
85
+
"Counter": "0,1",
94
86
"EventCode": "0x34",
95
87
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
96
88
"PerPkg": "1",
···
101
91
},
102
92
{
103
93
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
94
+
"Counter": "0,1",
104
95
"EventCode": "0x22",
105
96
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
106
97
"PerPkg": "1",
···
110
99
},
111
100
{
112
101
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
102
+
"Counter": "0,1",
113
103
"EventCode": "0x22",
114
104
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
115
105
"PerPkg": "1",
···
119
107
},
120
108
{
121
109
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
110
+
"Counter": "0,1",
122
111
"EventCode": "0x22",
123
112
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
124
113
"PerPkg": "1",
···
128
115
},
129
116
{
130
117
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
118
+
"Counter": "0,1",
131
119
"EventCode": "0x22",
132
120
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
133
121
"PerPkg": "1",
134
122
"UMask": "0x41",
135
123
"Unit": "CBOX"
124
+
},
125
+
{
126
+
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
127
+
"Counter": "FIXED",
128
+
"EventCode": "0xff",
129
+
"EventName": "UNC_CLOCK.SOCKET",
130
+
"PerPkg": "1",
131
+
"PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
132
+
"Unit": "cbox_0"
136
133
}
137
134
]
+8
tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
+8
tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
4
+
"Counter": "0,1",
4
5
"EventCode": "0x84",
5
6
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
6
7
"PerPkg": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
12
+
"Counter": "0",
13
13
"EventCode": "0x80",
14
14
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
15
15
"PerPkg": "1",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
20
+
"Counter": "0",
22
21
"CounterMask": "1",
23
22
"EventCode": "0x80",
24
23
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
···
29
26
},
30
27
{
31
28
"BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
29
+
"Counter": "0",
32
30
"EventCode": "0x80",
33
31
"EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
34
32
"PerPkg": "1",
···
38
34
},
39
35
{
40
36
"BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
37
+
"Counter": "0,1",
41
38
"EventCode": "0x81",
42
39
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
43
40
"PerPkg": "1",
···
47
42
},
48
43
{
49
44
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
45
+
"Counter": "0,1",
50
46
"EventCode": "0x81",
51
47
"EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
52
48
"PerPkg": "1",
···
56
50
},
57
51
{
58
52
"BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
53
+
"Counter": "0,1",
59
54
"EventCode": "0x81",
60
55
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
61
56
"PerPkg": "1",
···
65
58
},
66
59
{
67
60
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
61
+
"Counter": "0,1",
68
62
"EventCode": "0x81",
69
63
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
70
64
"PerPkg": "1",
-10
tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
-10
tools/perf/pmu-events/arch/x86/skylake/uncore-other.json
+28
tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
+28
tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x08",
5
6
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
6
7
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0x08",
14
14
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
15
15
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
···
19
17
},
20
18
{
21
19
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
20
+
"Counter": "0,1,2,3",
22
21
"CounterMask": "1",
23
22
"EventCode": "0x08",
24
23
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
···
29
26
},
30
27
{
31
28
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
29
+
"Counter": "0,1,2,3",
32
30
"EventCode": "0x08",
33
31
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
34
32
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
38
34
},
39
35
{
40
36
"BriefDescription": "Page walk completed due to a demand data load to a 1G page",
37
+
"Counter": "0,1,2,3",
41
38
"EventCode": "0x08",
42
39
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
43
40
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
47
42
},
48
43
{
49
44
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
45
+
"Counter": "0,1,2,3",
50
46
"EventCode": "0x08",
51
47
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
52
48
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
56
50
},
57
51
{
58
52
"BriefDescription": "Page walk completed due to a demand data load to a 4K page",
53
+
"Counter": "0,1,2,3",
59
54
"EventCode": "0x08",
60
55
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
61
56
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
65
58
},
66
59
{
67
60
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
61
+
"Counter": "0,1,2,3",
68
62
"EventCode": "0x08",
69
63
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
70
64
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
···
74
66
},
75
67
{
76
68
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
69
+
"Counter": "0,1,2,3",
77
70
"EventCode": "0x49",
78
71
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
79
72
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
···
83
74
},
84
75
{
85
76
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
77
+
"Counter": "0,1,2,3",
86
78
"EventCode": "0x49",
87
79
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
88
80
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
···
92
82
},
93
83
{
94
84
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
85
+
"Counter": "0,1,2,3",
95
86
"CounterMask": "1",
96
87
"EventCode": "0x49",
97
88
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
···
102
91
},
103
92
{
104
93
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
94
+
"Counter": "0,1,2,3",
105
95
"EventCode": "0x49",
106
96
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
107
97
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
111
99
},
112
100
{
113
101
"BriefDescription": "Page walk completed due to a demand data store to a 1G page",
102
+
"Counter": "0,1,2,3",
114
103
"EventCode": "0x49",
115
104
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
116
105
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
120
107
},
121
108
{
122
109
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
110
+
"Counter": "0,1,2,3",
123
111
"EventCode": "0x49",
124
112
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
125
113
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
129
115
},
130
116
{
131
117
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
118
+
"Counter": "0,1,2,3",
132
119
"EventCode": "0x49",
133
120
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
134
121
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
···
138
123
},
139
124
{
140
125
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
126
+
"Counter": "0,1,2,3",
141
127
"EventCode": "0x49",
142
128
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
143
129
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
···
147
131
},
148
132
{
149
133
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
134
+
"Counter": "0,1,2,3",
150
135
"EventCode": "0x4f",
151
136
"EventName": "EPT.WALK_PENDING",
152
137
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
···
156
139
},
157
140
{
158
141
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
142
+
"Counter": "0,1,2,3",
159
143
"EventCode": "0xAE",
160
144
"EventName": "ITLB.ITLB_FLUSH",
161
145
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
···
165
147
},
166
148
{
167
149
"BriefDescription": "Misses at all ITLB levels that cause page walks",
150
+
"Counter": "0,1,2,3",
168
151
"EventCode": "0x85",
169
152
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
170
153
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
···
174
155
},
175
156
{
176
157
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
158
+
"Counter": "0,1,2,3",
177
159
"EventCode": "0x85",
178
160
"EventName": "ITLB_MISSES.STLB_HIT",
179
161
"SampleAfterValue": "100003",
···
182
162
},
183
163
{
184
164
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
165
+
"Counter": "0,1,2,3",
185
166
"CounterMask": "1",
186
167
"EventCode": "0x85",
187
168
"EventName": "ITLB_MISSES.WALK_ACTIVE",
···
192
171
},
193
172
{
194
173
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
174
+
"Counter": "0,1,2,3",
195
175
"EventCode": "0x85",
196
176
"EventName": "ITLB_MISSES.WALK_COMPLETED",
197
177
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
···
201
179
},
202
180
{
203
181
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
182
+
"Counter": "0,1,2,3",
204
183
"EventCode": "0x85",
205
184
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
206
185
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
···
210
187
},
211
188
{
212
189
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
190
+
"Counter": "0,1,2,3",
213
191
"EventCode": "0x85",
214
192
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
215
193
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
···
219
195
},
220
196
{
221
197
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
198
+
"Counter": "0,1,2,3",
222
199
"EventCode": "0x85",
223
200
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
224
201
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
···
228
203
},
229
204
{
230
205
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
206
+
"Counter": "0,1,2,3",
231
207
"EventCode": "0x85",
232
208
"EventName": "ITLB_MISSES.WALK_PENDING",
233
209
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake microarchitecture.",
···
237
211
},
238
212
{
239
213
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
214
+
"Counter": "0,1,2,3",
240
215
"EventCode": "0xBD",
241
216
"EventName": "TLB_FLUSH.DTLB_THREAD",
242
217
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
···
246
219
},
247
220
{
248
221
"BriefDescription": "STLB flush attempts",
222
+
"Counter": "0,1,2,3",
249
223
"EventCode": "0xBD",
250
224
"EventName": "TLB_FLUSH.STLB_ANY",
251
225
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",