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clk: gcc-sm8350: drop PLL test clock

There is no user of core_bi_pll_test_se test clock so drop it.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228140917.118861-3-krzysztof.kozlowski@linaro.org

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson
e35b4b9e 412df0f9

-15
-15
drivers/clk/qcom/gcc-sm8350.c
··· 22 22 23 23 enum { 24 24 P_BI_TCXO, 25 - P_CORE_BI_PLL_TEST_SE, 26 25 P_GCC_GPLL0_OUT_EVEN, 27 26 P_GCC_GPLL0_OUT_MAIN, 28 27 P_GCC_GPLL4_OUT_MAIN, ··· 118 119 { P_BI_TCXO, 0 }, 119 120 { P_GCC_GPLL0_OUT_MAIN, 1 }, 120 121 { P_GCC_GPLL0_OUT_EVEN, 6 }, 121 - { P_CORE_BI_PLL_TEST_SE, 7 }, 122 122 }; 123 123 124 124 static const struct clk_parent_data gcc_parent_data_0[] = { 125 125 { .fw_name = "bi_tcxo" }, 126 126 { .hw = &gcc_gpll0.clkr.hw }, 127 127 { .hw = &gcc_gpll0_out_even.clkr.hw }, 128 - { .fw_name = "core_bi_pll_test_se" }, 129 128 }; 130 129 131 130 static const struct parent_map gcc_parent_map_1[] = { ··· 131 134 { P_GCC_GPLL0_OUT_MAIN, 1 }, 132 135 { P_SLEEP_CLK, 5 }, 133 136 { P_GCC_GPLL0_OUT_EVEN, 6 }, 134 - { P_CORE_BI_PLL_TEST_SE, 7 }, 135 137 }; 136 138 137 139 static const struct clk_parent_data gcc_parent_data_1[] = { ··· 138 142 { .hw = &gcc_gpll0.clkr.hw }, 139 143 { .fw_name = "sleep_clk" }, 140 144 { .hw = &gcc_gpll0_out_even.clkr.hw }, 141 - { .fw_name = "core_bi_pll_test_se" }, 142 145 }; 143 146 144 147 static const struct parent_map gcc_parent_map_2[] = { 145 148 { P_BI_TCXO, 0 }, 146 149 { P_SLEEP_CLK, 5 }, 147 - { P_CORE_BI_PLL_TEST_SE, 7 }, 148 150 }; 149 151 150 152 static const struct clk_parent_data gcc_parent_data_2[] = { 151 153 { .fw_name = "bi_tcxo" }, 152 154 { .fw_name = "sleep_clk" }, 153 - { .fw_name = "core_bi_pll_test_se" }, 154 155 }; 155 156 156 157 static const struct parent_map gcc_parent_map_3[] = { 157 158 { P_BI_TCXO, 0 }, 158 - { P_CORE_BI_PLL_TEST_SE, 7 }, 159 159 }; 160 160 161 161 static const struct clk_parent_data gcc_parent_data_3[] = { 162 162 { .fw_name = "bi_tcxo" }, 163 - { .fw_name = "core_bi_pll_test_se" }, 164 163 }; 165 164 166 165 static const struct parent_map gcc_parent_map_4[] = { ··· 184 193 { P_GCC_GPLL9_OUT_MAIN, 2 }, 185 194 { P_GCC_GPLL4_OUT_MAIN, 5 }, 186 195 { P_GCC_GPLL0_OUT_EVEN, 6 }, 187 - { P_CORE_BI_PLL_TEST_SE, 7 }, 188 196 }; 189 197 190 198 static const struct clk_parent_data gcc_parent_data_6[] = { ··· 192 202 { .hw = &gcc_gpll9.clkr.hw }, 193 203 { .hw = &gcc_gpll4.clkr.hw }, 194 204 { .hw = &gcc_gpll0_out_even.clkr.hw }, 195 - { .fw_name = "core_bi_pll_test_se" }, 196 205 }; 197 206 198 207 static const struct parent_map gcc_parent_map_7[] = { ··· 256 267 257 268 static const struct parent_map gcc_parent_map_13[] = { 258 269 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 259 - { P_CORE_BI_PLL_TEST_SE, 1 }, 260 270 { P_BI_TCXO, 2 }, 261 271 }; 262 272 263 273 static const struct clk_parent_data gcc_parent_data_13[] = { 264 274 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, 265 - { .fw_name = "core_bi_pll_test_se" }, 266 275 { .fw_name = "bi_tcxo" }, 267 276 }; 268 277 269 278 static const struct parent_map gcc_parent_map_14[] = { 270 279 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 }, 271 - { P_CORE_BI_PLL_TEST_SE, 1 }, 272 280 { P_BI_TCXO, 2 }, 273 281 }; 274 282 275 283 static const struct clk_parent_data gcc_parent_data_14[] = { 276 284 { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" }, 277 - { .fw_name = "core_bi_pll_test_se" }, 278 285 { .fw_name = "bi_tcxo" }, 279 286 }; 280 287