Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: gcc-sm8350: drop PLL test clock
There is no user of core_bi_pll_test_se test clock so drop it.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228140917.118861-3-krzysztof.kozlowski@linaro.org
authored by
Krzysztof Kozlowski
and committed by
Bjorn Andersson
e35b4b9e
412df0f9
-15
-15
drivers/clk/qcom/gcc-sm8350.c
-15
drivers/clk/qcom/gcc-sm8350.c
···
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_GCC_GPLL0_OUT_EVEN,
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P_GCC_GPLL0_OUT_MAIN,
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P_GCC_GPLL4_OUT_MAIN,
···
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{ P_BI_TCXO, 0 },
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gcc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &gcc_gpll0.clkr.hw },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_1[] = {
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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{ P_SLEEP_CLK, 5 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gcc_parent_data_1[] = {
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{ .hw = &gcc_gpll0.clkr.hw },
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{ .fw_name = "sleep_clk" },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_SLEEP_CLK, 5 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gcc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "sleep_clk" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gcc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_4[] = {
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{ P_GCC_GPLL9_OUT_MAIN, 2 },
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{ P_GCC_GPLL4_OUT_MAIN, 5 },
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{ P_GCC_GPLL0_OUT_EVEN, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gcc_parent_data_6[] = {
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{ .hw = &gcc_gpll9.clkr.hw },
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{ .hw = &gcc_gpll4.clkr.hw },
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{ .hw = &gcc_gpll0_out_even.clkr.hw },
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{ .fw_name = "core_bi_pll_test_se" },
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};
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static const struct parent_map gcc_parent_map_7[] = {
···
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static const struct parent_map gcc_parent_map_13[] = {
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{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
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{ P_CORE_BI_PLL_TEST_SE, 1 },
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{ P_BI_TCXO, 2 },
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};
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static const struct clk_parent_data gcc_parent_data_13[] = {
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{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
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{ .fw_name = "core_bi_pll_test_se" },
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{ .fw_name = "bi_tcxo" },
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};
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static const struct parent_map gcc_parent_map_14[] = {
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{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
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{ P_CORE_BI_PLL_TEST_SE, 1 },
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{ P_BI_TCXO, 2 },
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};
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static const struct clk_parent_data gcc_parent_data_14[] = {
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{ .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
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{ .fw_name = "core_bi_pll_test_se" },
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{ .fw_name = "bi_tcxo" },
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};
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