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Merge tag 'zynqmp-dt-for-6.18' of https://github.com/Xilinx/linux-xlnx into soc/dt

arm64: Xilinx DT changes for 6.18

- Fix some issues reported by dtschema
- Properly mark EMMC devices
- Update PSCI version
- Update DP description and enable it on boards
- Disable DEBUG IPs by default

SOM:
- Describe usb hubs
- Fix PWM polarity issue
- Add support for k24, kr260 and kd240

Versal NET:
- Describe CPU cache layout
- Fix RTC calibration value

* tag 'zynqmp-dt-for-6.18' of https://github.com/Xilinx/linux-xlnx:
arm64: versal-net: Describe L1/L2/L3/LLC caches
arm64: zynqmp: Enable DP in kr260/kv260 revA
arm64: zynqmp: Describe ethernet controllers via aliases on SOM
arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
arm64: zynqmp: Disable coresight by default
arm64: zynqmp: Add support for kd240 board
arm64: zynqmp: Add support for kr260 board
dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs
arm64: zynqmp: Enable PSCI 1.0
arm64: zynqmp: Enable DP for zcu100, zcu102, zcu104, zcu111
arm64: zynqmp: Introduce DP port labels
arm64: zynqmp: Fix pwm-fan polarity
arm64: zynqmp: Update the usb5744 hub node as per binding
arm64: zynqmp: Add cap-mmc-hw-reset and no-sd, no-sdio property to eMMC
arm64: zynqmp: Remove undocumented arasan,has-mdma property
arm64: zynqmp: Use generic spi@ name in zcu111-revA
arm64: versal-net: Update rtc calibration value

Link: https://lore.kernel.org/r/CAHTX3dK6if9f+-DW5ZEnfSO4=K_Zje-WH-fwysTY77farsSS9g@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann e3fa766a 55f624c7

+2046 -29
+81
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
··· 116 116 - const: xlnx,zynqmp-zcu111 117 117 - const: xlnx,zynqmp 118 118 119 + - description: Xilinx Kria SOMs K24 120 + minItems: 3 121 + items: 122 + enum: 123 + - xlnx,zynqmp-sm-k24-rev1 124 + - xlnx,zynqmp-sm-k24-revB 125 + - xlnx,zynqmp-sm-k24-revA 126 + - xlnx,zynqmp-sm-k24 127 + - xlnx,zynqmp 128 + allOf: 129 + - contains: 130 + const: xlnx,zynqmp 131 + - contains: 132 + const: xlnx,zynqmp-sm-k24 133 + 134 + - description: Xilinx Kria SOMs K24 (starter) 135 + minItems: 3 136 + items: 137 + enum: 138 + - xlnx,zynqmp-smk-k24-rev1 139 + - xlnx,zynqmp-smk-k24-revB 140 + - xlnx,zynqmp-smk-k24-revA 141 + - xlnx,zynqmp-smk-k24 142 + - xlnx,zynqmp 143 + allOf: 144 + - contains: 145 + const: xlnx,zynqmp 146 + - contains: 147 + const: xlnx,zynqmp-smk-k24 148 + 119 149 - description: Xilinx Kria SOMs 120 150 minItems: 3 121 151 items: ··· 177 147 const: xlnx,zynqmp 178 148 - contains: 179 149 const: xlnx,zynqmp-smk-k26 150 + 151 + - description: Xilinx Kria SOM KD240 revA/B/1 152 + minItems: 3 153 + items: 154 + enum: 155 + - xlnx,zynqmp-sk-kd240-rev1 156 + - xlnx,zynqmp-sk-kd240-revB 157 + - xlnx,zynqmp-sk-kd240-revA 158 + - xlnx,zynqmp-sk-kd240 159 + - xlnx,zynqmp 160 + allOf: 161 + - contains: 162 + const: xlnx,zynqmp-sk-kd240-revA 163 + - contains: 164 + const: xlnx,zynqmp-sk-kd240 165 + - contains: 166 + const: xlnx,zynqmp 167 + 168 + - description: Xilinx Kria SOM KR260 revA/Y/Z 169 + minItems: 3 170 + items: 171 + enum: 172 + - xlnx,zynqmp-sk-kr260-revA 173 + - xlnx,zynqmp-sk-kr260-revY 174 + - xlnx,zynqmp-sk-kr260-revZ 175 + - xlnx,zynqmp-sk-kr260 176 + - xlnx,zynqmp 177 + allOf: 178 + - contains: 179 + const: xlnx,zynqmp-sk-kr260-revA 180 + - contains: 181 + const: xlnx,zynqmp-sk-kr260 182 + - contains: 183 + const: xlnx,zynqmp 184 + 185 + - description: Xilinx Kria SOM KR260 rev2/1/B 186 + minItems: 3 187 + items: 188 + enum: 189 + - xlnx,zynqmp-sk-kr260-rev2 190 + - xlnx,zynqmp-sk-kr260-rev1 191 + - xlnx,zynqmp-sk-kr260-revB 192 + - xlnx,zynqmp-sk-kr260 193 + - xlnx,zynqmp 194 + allOf: 195 + - contains: 196 + const: xlnx,zynqmp-sk-kr260-revB 197 + - contains: 198 + const: xlnx,zynqmp-sk-kr260 199 + - contains: 200 + const: xlnx,zynqmp 180 201 181 202 - description: Xilinx Kria SOM KV260 revA/Y/Z 182 203 minItems: 3
+24
arch/arm64/boot/dts/xilinx/Makefile
··· 30 30 zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo 31 31 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb 32 32 33 + zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo 34 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb 35 + zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo 36 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb 37 + zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo 38 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb 39 + zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo 40 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb 41 + 42 + zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo 43 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb 44 + zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo 45 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb 46 + 47 + zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo 48 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb 49 + zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo 50 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb 51 + 52 + zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo 53 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb 54 + zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo 55 + dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb 56 + 33 57 dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb
+409 -1
arch/arm64/boot/dts/xilinx/versal-net.dtsi
··· 104 104 reg = <0>; 105 105 operating-points-v2 = <&cpu_opp_table>; 106 106 cpu-idle-states = <&CPU_SLEEP_0>; 107 + d-cache-size = <0x10000>; /* 64kB */ 108 + d-cache-line-size = <64>; 109 + /* 4 ways set associativity */ 110 + /* cache_size / (line_size / associativity) */ 111 + d-cache-sets = <256>; 112 + i-cache-size = <0x10000>; /* 64kB */ 113 + i-cache-line-size = <64>; 114 + /* 4 ways set associativity */ 115 + /* cache_size / (line_size / associativity) */ 116 + i-cache-sets = <256>; 117 + next-level-cache = <&l2_00>; 118 + l2_00: l2-cache { 119 + compatible = "cache"; 120 + cache-level = <2>; 121 + cache-size = <0x80000>; /* 512kB */ 122 + cache-line-size = <64>; 123 + /* 8 ways set associativity */ 124 + /* cache_size / (line_size/associativity) */ 125 + cache-sets = <1024>; 126 + cache-unified; 127 + next-level-cache = <&l3_0>; 128 + }; 107 129 }; 108 130 cpu100: cpu@100 { 109 131 compatible = "arm,cortex-a78"; ··· 134 112 reg = <0x100>; 135 113 operating-points-v2 = <&cpu_opp_table>; 136 114 cpu-idle-states = <&CPU_SLEEP_0>; 115 + d-cache-size = <0x10000>; /* 64kB */ 116 + d-cache-line-size = <64>; 117 + /* 4 ways set associativity */ 118 + /* cache_size / (line_size / associativity) */ 119 + d-cache-sets = <256>; 120 + i-cache-size = <0x10000>; /* 64kB */ 121 + i-cache-line-size = <64>; 122 + /* 4 ways set associativity */ 123 + /* cache_size / (line_size / associativity) */ 124 + i-cache-sets = <256>; 125 + next-level-cache = <&l2_01>; 126 + l2_01: l2-cache { 127 + compatible = "cache"; 128 + cache-level = <2>; 129 + cache-size = <0x80000>; /* 512kB */ 130 + cache-line-size = <64>; 131 + /* 8 ways set associativity */ 132 + /* cache_size / (line_size/associativity) */ 133 + cache-sets = <1024>; 134 + cache-unified; 135 + next-level-cache = <&l3_0>; 136 + }; 137 137 }; 138 138 cpu200: cpu@200 { 139 139 compatible = "arm,cortex-a78"; ··· 164 120 reg = <0x200>; 165 121 operating-points-v2 = <&cpu_opp_table>; 166 122 cpu-idle-states = <&CPU_SLEEP_0>; 123 + d-cache-size = <0x10000>; /* 64kB */ 124 + d-cache-line-size = <64>; 125 + /* 4 ways set associativity */ 126 + /* cache_size / (line_size / associativity) */ 127 + d-cache-sets = <256>; 128 + i-cache-size = <0x10000>; /* 64kB */ 129 + i-cache-line-size = <64>; 130 + /* 4 ways set associativity */ 131 + /* cache_size / (line_size / associativity) */ 132 + i-cache-sets = <256>; 133 + next-level-cache = <&l2_02>; 134 + l2_02: l2-cache { 135 + compatible = "cache"; 136 + cache-level = <2>; 137 + cache-size = <0x80000>; /* 512kB */ 138 + cache-line-size = <64>; 139 + /* 8 ways set associativity */ 140 + /* cache_size / (line_size/associativity) */ 141 + cache-sets = <1024>; 142 + cache-unified; 143 + next-level-cache = <&l3_0>; 144 + }; 167 145 }; 168 146 cpu300: cpu@300 { 169 147 compatible = "arm,cortex-a78"; ··· 194 128 reg = <0x300>; 195 129 operating-points-v2 = <&cpu_opp_table>; 196 130 cpu-idle-states = <&CPU_SLEEP_0>; 131 + d-cache-size = <0x10000>; /* 64kB */ 132 + d-cache-line-size = <64>; 133 + /* 4 ways set associativity */ 134 + /* cache_size / (line_size / associativity) */ 135 + d-cache-sets = <256>; 136 + i-cache-size = <0x10000>; /* 64kB */ 137 + i-cache-line-size = <64>; 138 + /* 4 ways set associativity */ 139 + /* cache_size / (line_size / associativity) */ 140 + i-cache-sets = <256>; 141 + next-level-cache = <&l2_03>; 142 + l2_03: l2-cache { 143 + compatible = "cache"; 144 + cache-level = <2>; 145 + cache-size = <0x80000>; /* 512kB */ 146 + cache-line-size = <64>; 147 + /* 8 ways set associativity */ 148 + /* cache_size / (line_size/associativity) */ 149 + cache-sets = <1024>; 150 + cache-unified; 151 + next-level-cache = <&l3_0>; 152 + }; 197 153 }; 198 154 cpu10000: cpu@10000 { 199 155 compatible = "arm,cortex-a78"; ··· 224 136 reg = <0x10000>; 225 137 operating-points-v2 = <&cpu_opp_table>; 226 138 cpu-idle-states = <&CPU_SLEEP_0>; 139 + d-cache-size = <0x10000>; /* 64kB */ 140 + d-cache-line-size = <64>; 141 + /* 4 ways set associativity */ 142 + /* cache_size / (line_size / associativity) */ 143 + d-cache-sets = <256>; 144 + i-cache-size = <0x10000>; /* 64kB */ 145 + i-cache-line-size = <64>; 146 + /* 4 ways set associativity */ 147 + /* cache_size / (line_size / associativity) */ 148 + i-cache-sets = <256>; 149 + next-level-cache = <&l2_10>; 150 + l2_10: l2-cache { 151 + compatible = "cache"; 152 + cache-level = <2>; 153 + cache-size = <0x80000>; /* 512kB */ 154 + cache-line-size = <64>; 155 + /* 8 ways set associativity */ 156 + /* cache_size / (line_size/associativity) */ 157 + cache-sets = <1024>; 158 + cache-unified; 159 + next-level-cache = <&l3_1>; 160 + }; 227 161 }; 228 162 cpu10100: cpu@10100 { 229 163 compatible = "arm,cortex-a78"; ··· 254 144 reg = <0x10100>; 255 145 operating-points-v2 = <&cpu_opp_table>; 256 146 cpu-idle-states = <&CPU_SLEEP_0>; 147 + d-cache-size = <0x10000>; /* 64kB */ 148 + d-cache-line-size = <64>; 149 + /* 4 ways set associativity */ 150 + /* cache_size / (line_size / associativity) */ 151 + d-cache-sets = <256>; 152 + i-cache-size = <0x10000>; /* 64kB */ 153 + i-cache-line-size = <64>; 154 + /* 4 ways set associativity */ 155 + /* cache_size / (line_size / associativity) */ 156 + i-cache-sets = <256>; 157 + next-level-cache = <&l2_11>; 158 + l2_11: l2-cache { 159 + compatible = "cache"; 160 + cache-level = <2>; 161 + cache-size = <0x80000>; /* 512kB */ 162 + cache-line-size = <64>; 163 + /* 8 ways set associativity */ 164 + /* cache_size / (line_size/associativity) */ 165 + cache-sets = <1024>; 166 + cache-unified; 167 + next-level-cache = <&l3_1>; 168 + }; 257 169 }; 258 170 cpu10200: cpu@10200 { 259 171 compatible = "arm,cortex-a78"; ··· 284 152 reg = <0x10200>; 285 153 operating-points-v2 = <&cpu_opp_table>; 286 154 cpu-idle-states = <&CPU_SLEEP_0>; 155 + d-cache-size = <0x10000>; /* 64kB */ 156 + d-cache-line-size = <64>; 157 + /* 4 ways set associativity */ 158 + /* cache_size / (line_size / associativity) */ 159 + d-cache-sets = <256>; 160 + i-cache-size = <0x10000>; /* 64kB */ 161 + i-cache-line-size = <64>; 162 + /* 4 ways set associativity */ 163 + /* cache_size / (line_size / associativity) */ 164 + i-cache-sets = <256>; 165 + next-level-cache = <&l2_12>; 166 + l2_12: l2-cache { 167 + compatible = "cache"; 168 + cache-level = <2>; 169 + cache-size = <0x80000>; /* 512kB */ 170 + cache-line-size = <64>; 171 + /* 8 ways set associativity */ 172 + /* cache_size / (line_size/associativity) */ 173 + cache-sets = <1024>; 174 + cache-unified; 175 + next-level-cache = <&l3_1>; 176 + }; 287 177 }; 288 178 cpu10300: cpu@10300 { 289 179 compatible = "arm,cortex-a78"; ··· 314 160 reg = <0x10300>; 315 161 operating-points-v2 = <&cpu_opp_table>; 316 162 cpu-idle-states = <&CPU_SLEEP_0>; 163 + d-cache-size = <0x10000>; /* 64kB */ 164 + d-cache-line-size = <64>; 165 + /* 4 ways set associativity */ 166 + /* cache_size / (line_size / associativity) */ 167 + d-cache-sets = <256>; 168 + i-cache-size = <0x10000>; /* 64kB */ 169 + i-cache-line-size = <64>; 170 + /* 4 ways set associativity */ 171 + /* cache_size / (line_size / associativity) */ 172 + i-cache-sets = <256>; 173 + next-level-cache = <&l2_13>; 174 + l2_13: l2-cache { 175 + compatible = "cache"; 176 + cache-level = <2>; 177 + cache-size = <0x80000>; /* 512kB */ 178 + cache-line-size = <64>; 179 + /* 8 ways set associativity */ 180 + /* cache_size / (line_size/associativity) */ 181 + cache-sets = <1024>; 182 + cache-unified; 183 + next-level-cache = <&l3_1>; 184 + }; 317 185 }; 318 186 cpu20000: cpu@20000 { 319 187 compatible = "arm,cortex-a78"; ··· 344 168 reg = <0x20000>; 345 169 operating-points-v2 = <&cpu_opp_table>; 346 170 cpu-idle-states = <&CPU_SLEEP_0>; 171 + d-cache-size = <0x10000>; /* 64kB */ 172 + d-cache-line-size = <64>; 173 + /* 4 ways set associativity */ 174 + /* cache_size / (line_size / associativity) */ 175 + d-cache-sets = <256>; 176 + i-cache-size = <0x10000>; /* 64kB */ 177 + i-cache-line-size = <64>; 178 + /* 4 ways set associativity */ 179 + /* cache_size / (line_size / associativity) */ 180 + i-cache-sets = <256>; 181 + next-level-cache = <&l2_20>; 182 + l2_20: l2-cache { 183 + compatible = "cache"; 184 + cache-level = <2>; 185 + cache-size = <0x80000>; /* 512kB */ 186 + cache-line-size = <64>; 187 + /* 8 ways set associativity */ 188 + /* cache_size / (line_size/associativity) */ 189 + cache-sets = <1024>; 190 + cache-unified; 191 + next-level-cache = <&l3_2>; 192 + }; 347 193 }; 348 194 cpu20100: cpu@20100 { 349 195 compatible = "arm,cortex-a78"; ··· 374 176 reg = <0x20100>; 375 177 operating-points-v2 = <&cpu_opp_table>; 376 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 + d-cache-size = <0x10000>; /* 64kB */ 180 + d-cache-line-size = <64>; 181 + /* 4 ways set associativity */ 182 + /* cache_size / (line_size / associativity) */ 183 + d-cache-sets = <256>; 184 + i-cache-size = <0x10000>; /* 64kB */ 185 + i-cache-line-size = <64>; 186 + /* 4 ways set associativity */ 187 + /* cache_size / (line_size / associativity) */ 188 + i-cache-sets = <256>; 189 + next-level-cache = <&l2_21>; 190 + l2_21: l2-cache { 191 + compatible = "cache"; 192 + cache-level = <2>; 193 + cache-size = <0x80000>; /* 512kB */ 194 + cache-line-size = <64>; 195 + /* 8 ways set associativity */ 196 + /* cache_size / (line_size/associativity) */ 197 + cache-sets = <1024>; 198 + cache-unified; 199 + next-level-cache = <&l3_2>; 200 + }; 377 201 }; 378 202 cpu20200: cpu@20200 { 379 203 compatible = "arm,cortex-a78"; ··· 404 184 reg = <0x20200>; 405 185 operating-points-v2 = <&cpu_opp_table>; 406 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 + d-cache-size = <0x10000>; /* 64kB */ 188 + d-cache-line-size = <64>; 189 + /* 4 ways set associativity */ 190 + /* cache_size / (line_size / associativity) */ 191 + d-cache-sets = <256>; 192 + i-cache-size = <0x10000>; /* 64kB */ 193 + i-cache-line-size = <64>; 194 + /* 4 ways set associativity */ 195 + /* cache_size / (line_size / associativity) */ 196 + i-cache-sets = <256>; 197 + next-level-cache = <&l2_22>; 198 + l2_22: l2-cache { 199 + compatible = "cache"; 200 + cache-level = <2>; 201 + cache-size = <0x80000>; /* 512kB */ 202 + cache-line-size = <64>; 203 + /* 8 ways set associativity */ 204 + /* cache_size / (line_size/associativity) */ 205 + cache-sets = <1024>; 206 + cache-unified; 207 + next-level-cache = <&l3_2>; 208 + }; 407 209 }; 408 210 cpu20300: cpu@20300 { 409 211 compatible = "arm,cortex-a78"; ··· 434 192 reg = <0x20300>; 435 193 operating-points-v2 = <&cpu_opp_table>; 436 194 cpu-idle-states = <&CPU_SLEEP_0>; 195 + d-cache-size = <0x10000>; /* 64kB */ 196 + d-cache-line-size = <64>; 197 + /* 4 ways set associativity */ 198 + /* cache_size / (line_size / associativity) */ 199 + d-cache-sets = <256>; 200 + i-cache-size = <0x10000>; /* 64kB */ 201 + i-cache-line-size = <64>; 202 + /* 4 ways set associativity */ 203 + /* cache_size / (line_size / associativity) */ 204 + i-cache-sets = <256>; 205 + next-level-cache = <&l2_23>; 206 + l2_23: l2-cache { 207 + compatible = "cache"; 208 + cache-level = <2>; 209 + cache-size = <0x80000>; /* 512kB */ 210 + cache-line-size = <64>; 211 + /* 8 ways set associativity */ 212 + /* cache_size / (line_size/associativity) */ 213 + cache-sets = <1024>; 214 + cache-unified; 215 + next-level-cache = <&l3_2>; 216 + }; 437 217 }; 438 218 cpu30000: cpu@30000 { 439 219 compatible = "arm,cortex-a78"; ··· 464 200 reg = <0x30000>; 465 201 operating-points-v2 = <&cpu_opp_table>; 466 202 cpu-idle-states = <&CPU_SLEEP_0>; 203 + d-cache-size = <0x10000>; /* 64kB */ 204 + d-cache-line-size = <64>; 205 + /* 4 ways set associativity */ 206 + /* cache_size / (line_size / associativity) */ 207 + d-cache-sets = <256>; 208 + i-cache-size = <0x10000>; /* 64kB */ 209 + i-cache-line-size = <64>; 210 + /* 4 ways set associativity */ 211 + /* cache_size / (line_size / associativity) */ 212 + i-cache-sets = <256>; 213 + next-level-cache = <&l2_30>; 214 + l2_30: l2-cache { 215 + compatible = "cache"; 216 + cache-level = <2>; 217 + cache-size = <0x80000>; /* 512kB */ 218 + cache-line-size = <64>; 219 + /* 8 ways set associativity */ 220 + /* cache_size / (line_size/associativity) */ 221 + cache-sets = <1024>; 222 + cache-unified; 223 + next-level-cache = <&l3_3>; 224 + }; 467 225 }; 468 226 cpu30100: cpu@30100 { 469 227 compatible = "arm,cortex-a78"; ··· 494 208 reg = <0x30100>; 495 209 operating-points-v2 = <&cpu_opp_table>; 496 210 cpu-idle-states = <&CPU_SLEEP_0>; 211 + d-cache-size = <0x10000>; /* 64kB */ 212 + d-cache-line-size = <64>; 213 + /* 4 ways set associativity */ 214 + /* cache_size / (line_size / associativity) */ 215 + d-cache-sets = <256>; 216 + i-cache-size = <0x10000>; /* 64kB */ 217 + i-cache-line-size = <64>; 218 + /* 4 ways set associativity */ 219 + /* cache_size / (line_size / associativity) */ 220 + i-cache-sets = <256>; 221 + next-level-cache = <&l2_31>; 222 + l2_31: l2-cache { 223 + compatible = "cache"; 224 + cache-level = <2>; 225 + cache-size = <0x80000>; /* 512kB */ 226 + cache-line-size = <64>; 227 + /* 8 ways set associativity */ 228 + /* cache_size / (line_size/associativity) */ 229 + cache-sets = <1024>; 230 + cache-unified; 231 + next-level-cache = <&l3_3>; 232 + }; 497 233 }; 498 234 cpu30200: cpu@30200 { 499 235 compatible = "arm,cortex-a78"; ··· 524 216 reg = <0x30200>; 525 217 operating-points-v2 = <&cpu_opp_table>; 526 218 cpu-idle-states = <&CPU_SLEEP_0>; 219 + d-cache-size = <0x10000>; /* 64kB */ 220 + d-cache-line-size = <64>; 221 + /* 4 ways set associativity */ 222 + /* cache_size / (line_size / associativity) */ 223 + d-cache-sets = <256>; 224 + i-cache-size = <0x10000>; /* 64kB */ 225 + i-cache-line-size = <64>; 226 + /* 4 ways set associativity */ 227 + /* cache_size / (line_size / associativity) */ 228 + i-cache-sets = <256>; 229 + next-level-cache = <&l2_32>; 230 + l2_32: l2-cache { 231 + compatible = "cache"; 232 + cache-level = <2>; 233 + cache-size = <0x80000>; /* 512kB */ 234 + cache-line-size = <64>; 235 + /* 8 ways set associativity */ 236 + /* cache_size / (line_size/associativity) */ 237 + cache-sets = <1024>; 238 + cache-unified; 239 + next-level-cache = <&l3_3>; 240 + }; 527 241 }; 528 242 cpu30300: cpu@30300 { 529 243 compatible = "arm,cortex-a78"; ··· 554 224 reg = <0x30300>; 555 225 operating-points-v2 = <&cpu_opp_table>; 556 226 cpu-idle-states = <&CPU_SLEEP_0>; 227 + d-cache-size = <0x10000>; /* 64kB */ 228 + d-cache-line-size = <64>; 229 + /* 4 ways set associativity */ 230 + /* cache_size / (line_size / associativity) */ 231 + d-cache-sets = <256>; 232 + i-cache-size = <0x10000>; /* 64kB */ 233 + i-cache-line-size = <64>; 234 + /* 4 ways set associativity */ 235 + /* cache_size / (line_size / associativity) */ 236 + i-cache-sets = <256>; 237 + next-level-cache = <&l2_33>; 238 + l2_33: l2-cache { 239 + compatible = "cache"; 240 + cache-level = <2>; 241 + cache-size = <0x80000>; /* 512kB */ 242 + cache-line-size = <64>; 243 + /* 8 ways set associativity */ 244 + /* cache_size / (line_size/associativity) */ 245 + cache-sets = <1024>; 246 + cache-unified; 247 + next-level-cache = <&l3_3>; 248 + }; 557 249 }; 250 + 251 + l3_0: l3-0-cache { /* cluster private */ 252 + compatible = "cache"; 253 + cache-level = <3>; 254 + cache-size = <0x200000>; /* 2MB */ 255 + cache-line-size = <64>; 256 + /* 16 ways set associativity */ 257 + /* cache_size / (line_size/associativity) */ 258 + cache-sets = <2048>; 259 + cache-unified; 260 + next-level-cache = <&llc>; 261 + }; 262 + 263 + l3_1: l3-1-cache { /* cluster private */ 264 + compatible = "cache"; 265 + cache-level = <3>; 266 + cache-size = <0x200000>; /* 2MB */ 267 + cache-line-size = <64>; 268 + /* 16 ways set associativity */ 269 + /* cache_size / (line_size/associativity) */ 270 + cache-sets = <2048>; 271 + cache-unified; 272 + next-level-cache = <&llc>; 273 + }; 274 + 275 + l3_2: l3-2-cache { /* cluster private */ 276 + compatible = "cache"; 277 + cache-level = <3>; 278 + cache-size = <0x200000>; /* 2MB */ 279 + cache-line-size = <64>; 280 + /* 16 ways set associativity */ 281 + /* cache_size / (line_size/associativity) */ 282 + cache-sets = <2048>; 283 + cache-unified; 284 + next-level-cache = <&llc>; 285 + }; 286 + 287 + l3_3: l3-3-cache { /* cluster private */ 288 + compatible = "cache"; 289 + cache-level = <3>; 290 + cache-size = <0x200000>; /* 2MB */ 291 + cache-line-size = <64>; 292 + /* 16 ways set associativity */ 293 + /* cache_size / (line_size/associativity) */ 294 + cache-sets = <2048>; 295 + cache-unified; 296 + next-level-cache = <&llc>; 297 + }; 298 + 299 + llc: l4-cache { /* LLC inside CMN */ 300 + compatible = "cache"; 301 + cache-level = <4>; 302 + cache-size = <0x1000000>; /* 16MB */ 303 + cache-unified; 304 + }; 305 + 558 306 idle-states { 559 307 entry-method = "psci"; 560 308 ··· 964 556 reg = <0 0xf12a0000 0 0x100>; 965 557 interrupts = <0 200 4>, <0 201 4>; 966 558 interrupt-names = "alarm", "sec"; 967 - calibration = <0x8000>; 559 + calibration = <0x7FFF>; 968 560 }; 969 561 970 562 sdhci0: mmc@f1040000 {
+390
arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for KD240 revA Carrier Card 4 + * 5 + * Copyright (C) 2021 - 2022, Xilinx, Inc. 6 + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. 7 + * 8 + * Michal Simek <michal.simek@amd.com> 9 + */ 10 + 11 + #include <dt-bindings/gpio/gpio.h> 12 + #include <dt-bindings/phy/phy.h> 13 + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 + 15 + /dts-v1/; 16 + /plugin/; 17 + 18 + &{/} { 19 + compatible = "xlnx,zynqmp-sk-kd240-rev1", 20 + "xlnx,zynqmp-sk-kd240-revB", 21 + "xlnx,zynqmp-sk-kd240-revA", 22 + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; 23 + model = "ZynqMP KD240 revA/B/1"; 24 + 25 + aliases { 26 + ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ 27 + }; 28 + 29 + ina260-u3 { 30 + compatible = "iio-hwmon"; 31 + io-channels = <&u3 0>, <&u3 1>, <&u3 2>; 32 + }; 33 + 34 + clk_26: clock2 { /* u17 - USB */ 35 + compatible = "fixed-clock"; 36 + #clock-cells = <0>; 37 + clock-frequency = <26000000>; 38 + }; 39 + 40 + clk_25_0: clock4 { /* u92/u91 - GEM2 */ 41 + compatible = "fixed-clock"; 42 + #clock-cells = <0>; 43 + clock-frequency = <25000000>; 44 + }; 45 + 46 + clk_25_1: clock5 { /* u92/u91 - GEM3 */ 47 + compatible = "fixed-clock"; 48 + #clock-cells = <0>; 49 + clock-frequency = <25000000>; 50 + }; 51 + }; 52 + 53 + &can0 { 54 + status = "okay"; 55 + pinctrl-names = "default"; 56 + pinctrl-0 = <&pinctrl_can0_default>; 57 + }; 58 + 59 + &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ 60 + #address-cells = <1>; 61 + #size-cells = <0>; 62 + pinctrl-names = "default", "gpio"; 63 + pinctrl-0 = <&pinctrl_i2c1_default>; 64 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 65 + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 66 + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 67 + 68 + u3: ina260@40 { /* u3 */ 69 + compatible = "ti,ina260"; 70 + #io-channel-cells = <1>; 71 + label = "ina260-u14"; 72 + reg = <0x40>; 73 + }; 74 + 75 + slg7xl45106: gpio@11 { /* u13 - reset logic */ 76 + compatible = "dlg,slg7xl45106"; 77 + reg = <0x11>; 78 + label = "resetchip"; 79 + gpio-controller; 80 + #gpio-cells = <2>; 81 + gpio-line-names = "USB0_PHY_RESET_B", "", 82 + "SD_RESET_B", "USB0_HUB_RESET_B", 83 + "", "PS_GEM0_RESET_B", 84 + "", ""; 85 + }; 86 + 87 + hub: usb-hub@2d { /* u36 */ 88 + compatible = "microchip,usb5744"; 89 + reg = <0x2d>; 90 + }; 91 + }; 92 + 93 + /* USB 3.0 */ 94 + &psgtr { 95 + status = "okay"; 96 + /* usb */ 97 + clocks = <&clk_26>; 98 + clock-names = "ref2"; 99 + }; 100 + 101 + &usb0 { /* mio52 - mio63 */ 102 + status = "okay"; 103 + pinctrl-names = "default"; 104 + pinctrl-0 = <&pinctrl_usb0_default>; 105 + phy-names = "usb3-phy"; 106 + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 107 + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; 108 + assigned-clock-rates = <250000000>, <20000000>; 109 + }; 110 + 111 + &dwc3_0 { 112 + status = "okay"; 113 + dr_mode = "host"; 114 + snps,usb3_lpm_capable; 115 + maximum-speed = "super-speed"; 116 + #address-cells = <1>; 117 + #size-cells = <0>; 118 + 119 + /* 2.0 hub on port 1 */ 120 + hub_2_0: hub@1 { 121 + compatible = "usb424,2744"; 122 + reg = <1>; 123 + peer-hub = <&hub_3_0>; 124 + i2c-bus = <&hub>; 125 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 126 + }; 127 + 128 + /* 3.0 hub on port 2 */ 129 + hub_3_0: hub@2 { 130 + compatible = "usb424,5744"; 131 + reg = <2>; 132 + peer-hub = <&hub_2_0>; 133 + i2c-bus = <&hub>; 134 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 135 + }; 136 + }; 137 + 138 + &gem1 { /* mdio mio50/51 */ 139 + status = "okay"; 140 + pinctrl-names = "default"; 141 + pinctrl-0 = <&pinctrl_gem1_default>; 142 + assigned-clock-rates = <250000000>; 143 + 144 + phy-handle = <&phy0>; 145 + phy-mode = "rgmii-id"; 146 + mdio: mdio { 147 + #address-cells = <1>; 148 + #size-cells = <0>; 149 + phy0: ethernet-phy@8 { /* Adin u31 */ 150 + #phy-cells = <1>; 151 + compatible = "ethernet-phy-id0283.bc30"; 152 + reg = <8>; 153 + adi,rx-internal-delay-ps = <2000>; 154 + adi,tx-internal-delay-ps = <2000>; 155 + adi,fifo-depth-bits = <8>; 156 + reset-assert-us = <10>; 157 + reset-deassert-us = <5000>; 158 + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; 159 + }; 160 + }; 161 + }; 162 + 163 + /* 2 more ethernet phys u32@2 and u34@3 */ 164 + 165 + &pinctrl0 { /* required by spec */ 166 + status = "okay"; 167 + 168 + pinctrl_can0_default: can0-default { 169 + mux { 170 + function = "can0"; 171 + groups = "can0_16_grp"; 172 + }; 173 + 174 + conf { 175 + groups = "can0_16_grp"; 176 + slew-rate = <SLEW_RATE_SLOW>; 177 + power-source = <IO_STANDARD_LVCMOS18>; 178 + }; 179 + 180 + conf-rx { 181 + pins = "MIO66"; 182 + bias-pull-up; 183 + }; 184 + 185 + conf-tx { 186 + pins = "MIO67"; 187 + bias-pull-up; 188 + drive-strength = <4>; 189 + }; 190 + }; 191 + 192 + pinctrl_uart0_default: uart0-default { 193 + conf { 194 + groups = "uart0_17_grp"; 195 + slew-rate = <SLEW_RATE_SLOW>; 196 + power-source = <IO_STANDARD_LVCMOS18>; 197 + drive-strength = <12>; 198 + }; 199 + 200 + conf-rx { 201 + pins = "MIO70"; 202 + bias-high-impedance; 203 + }; 204 + 205 + conf-tx { 206 + pins = "MIO71"; 207 + bias-disable; 208 + }; 209 + 210 + mux { 211 + groups = "uart0_17_grp"; 212 + function = "uart0"; 213 + }; 214 + }; 215 + 216 + pinctrl_uart1_default: uart1-default { 217 + conf { 218 + groups = "uart1_9_grp"; 219 + slew-rate = <SLEW_RATE_SLOW>; 220 + power-source = <IO_STANDARD_LVCMOS18>; 221 + drive-strength = <12>; 222 + }; 223 + 224 + conf-rx { 225 + pins = "MIO37"; 226 + bias-high-impedance; 227 + }; 228 + 229 + conf-tx { 230 + pins = "MIO36"; 231 + bias-disable; 232 + output-enable; 233 + }; 234 + 235 + mux { 236 + groups = "uart1_9_grp"; 237 + function = "uart1"; 238 + }; 239 + }; 240 + 241 + pinctrl_i2c1_default: i2c1-default { 242 + conf { 243 + groups = "i2c1_6_grp"; 244 + bias-pull-up; 245 + slew-rate = <SLEW_RATE_SLOW>; 246 + power-source = <IO_STANDARD_LVCMOS18>; 247 + }; 248 + 249 + mux { 250 + groups = "i2c1_6_grp"; 251 + function = "i2c1"; 252 + }; 253 + }; 254 + 255 + pinctrl_i2c1_gpio: i2c1-gpio-grp { 256 + conf { 257 + groups = "gpio0_24_grp", "gpio0_25_grp"; 258 + slew-rate = <SLEW_RATE_SLOW>; 259 + power-source = <IO_STANDARD_LVCMOS18>; 260 + }; 261 + 262 + mux { 263 + groups = "gpio0_24_grp", "gpio0_25_grp"; 264 + function = "gpio0"; 265 + }; 266 + }; 267 + 268 + pinctrl_gem1_default: gem1-default { 269 + conf { 270 + groups = "ethernet1_0_grp"; 271 + slew-rate = <SLEW_RATE_SLOW>; 272 + power-source = <IO_STANDARD_LVCMOS18>; 273 + }; 274 + 275 + conf-rx { 276 + pins = "MIO45", "MIO46", "MIO47", "MIO48"; 277 + bias-disable; 278 + low-power-disable; 279 + }; 280 + 281 + conf-bootstrap { 282 + pins = "MIO44", "MIO49"; 283 + bias-disable; 284 + output-enable; 285 + low-power-disable; 286 + }; 287 + 288 + conf-tx { 289 + pins = "MIO38", "MIO39", "MIO40", 290 + "MIO41", "MIO42", "MIO43"; 291 + bias-disable; 292 + output-enable; 293 + low-power-enable; 294 + }; 295 + 296 + conf-mdio { 297 + groups = "mdio1_0_grp"; 298 + slew-rate = <SLEW_RATE_SLOW>; 299 + power-source = <IO_STANDARD_LVCMOS18>; 300 + bias-disable; 301 + output-enable; 302 + }; 303 + 304 + mux-mdio { 305 + function = "mdio1"; 306 + groups = "mdio1_0_grp"; 307 + }; 308 + 309 + mux { 310 + function = "ethernet1"; 311 + groups = "ethernet1_0_grp"; 312 + }; 313 + }; 314 + 315 + pinctrl_usb0_default: usb0-default { 316 + conf { 317 + groups = "usb0_0_grp"; 318 + power-source = <IO_STANDARD_LVCMOS18>; 319 + }; 320 + 321 + conf-rx { 322 + pins = "MIO52", "MIO53", "MIO55"; 323 + bias-high-impedance; 324 + drive-strength = <12>; 325 + slew-rate = <SLEW_RATE_FAST>; 326 + }; 327 + 328 + conf-tx { 329 + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 330 + "MIO60", "MIO61", "MIO62", "MIO63"; 331 + bias-disable; 332 + output-enable; 333 + drive-strength = <4>; 334 + slew-rate = <SLEW_RATE_SLOW>; 335 + }; 336 + 337 + mux { 338 + groups = "usb0_0_grp"; 339 + function = "usb0"; 340 + }; 341 + }; 342 + 343 + pinctrl_usb1_default: usb1-default { 344 + conf { 345 + groups = "usb1_0_grp"; 346 + power-source = <IO_STANDARD_LVCMOS18>; 347 + }; 348 + 349 + conf-rx { 350 + pins = "MIO64", "MIO65", "MIO67"; 351 + bias-high-impedance; 352 + drive-strength = <12>; 353 + slew-rate = <SLEW_RATE_FAST>; 354 + }; 355 + 356 + conf-tx { 357 + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", 358 + "MIO72", "MIO73", "MIO74", "MIO75"; 359 + bias-disable; 360 + output-enable; 361 + drive-strength = <4>; 362 + slew-rate = <SLEW_RATE_SLOW>; 363 + }; 364 + 365 + mux { 366 + groups = "usb1_0_grp"; 367 + function = "usb1"; 368 + }; 369 + }; 370 + }; 371 + 372 + &uart0 { 373 + status = "okay"; 374 + rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; 375 + linux,rs485-enabled-at-boot-time; 376 + rs485-rts-delay = <10 10>; 377 + pinctrl-names = "default"; 378 + pinctrl-0 = <&pinctrl_uart0_default>; 379 + assigned-clock-rates = <100000000>; 380 + }; 381 + 382 + &uart1 { 383 + status = "okay"; 384 + pinctrl-names = "default"; 385 + pinctrl-0 = <&pinctrl_uart1_default>; 386 + }; 387 + 388 + &zynqmp_dpsub { 389 + status = "disabled"; 390 + };
+455
arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for KR260 revA Carrier Card 4 + * 5 + * (C) Copyright 2021, Xilinx, Inc. 6 + * 7 + * Michal Simek <michal.simek@amd.com> 8 + */ 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/net/ti-dp83867.h> 12 + #include <dt-bindings/phy/phy.h> 13 + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 + 15 + /dts-v1/; 16 + /plugin/; 17 + 18 + &{/} { 19 + compatible = "xlnx,zynqmp-sk-kr260-revA", 20 + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; 21 + model = "ZynqMP KR260 revA"; 22 + 23 + aliases { 24 + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ 25 + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ 26 + }; 27 + 28 + ina260-u14 { 29 + compatible = "iio-hwmon"; 30 + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; 31 + }; 32 + 33 + clk_27: clock0 { /* u86 - DP */ 34 + compatible = "fixed-clock"; 35 + #clock-cells = <0>; 36 + clock-frequency = <27000000>; 37 + }; 38 + 39 + clk_125: si5332-0 { /* u17 - GEM0/1 */ 40 + compatible = "fixed-clock"; 41 + #clock-cells = <0>; 42 + clock-frequency = <125000000>; 43 + }; 44 + 45 + clk_74: si5332-5 { /* u17 - SLVC-EC */ 46 + compatible = "fixed-clock"; 47 + #clock-cells = <0>; 48 + clock-frequency = <74250000>; 49 + }; 50 + 51 + clk_26: si5332-2 { /* u17 - USB */ 52 + compatible = "fixed-clock"; 53 + #clock-cells = <0>; 54 + clock-frequency = <26000000>; 55 + }; 56 + 57 + clk_156: si5332-3 { /* u17 - SFP+ */ 58 + compatible = "fixed-clock"; 59 + #clock-cells = <0>; 60 + clock-frequency = <156250000>; 61 + }; 62 + 63 + clk_25_0: si5332-1 { /* u17 - GEM2 */ 64 + compatible = "fixed-clock"; 65 + #clock-cells = <0>; 66 + clock-frequency = <25000000>; 67 + }; 68 + 69 + clk_25_1: si5332-4 { /* u17 - GEM3 */ 70 + compatible = "fixed-clock"; 71 + #clock-cells = <0>; 72 + clock-frequency = <25000000>; 73 + }; 74 + dpcon { 75 + compatible = "dp-connector"; 76 + label = "P11"; 77 + type = "full-size"; 78 + 79 + port { 80 + dpcon_in: endpoint { 81 + remote-endpoint = <&dpsub_dp_out>; 82 + }; 83 + }; 84 + }; 85 + }; 86 + 87 + &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ 88 + #address-cells = <1>; 89 + #size-cells = <0>; 90 + pinctrl-names = "default", "gpio"; 91 + pinctrl-0 = <&pinctrl_i2c1_default>; 92 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 93 + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 94 + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 95 + 96 + u14: ina260@40 { /* u14 */ 97 + compatible = "ti,ina260"; 98 + #io-channel-cells = <1>; 99 + label = "ina260-u14"; 100 + reg = <0x40>; 101 + }; 102 + 103 + slg7xl45106: gpio@11 { /* u19 - reset logic */ 104 + compatible = "dlg,slg7xl45106"; 105 + reg = <0x11>; 106 + label = "resetchip"; 107 + gpio-controller; 108 + #gpio-cells = <2>; 109 + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", 110 + "SD_RESET_B", "USB0_HUB_RESET_B", 111 + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", 112 + "PS_GEM1_RESET_B", ""; 113 + }; 114 + 115 + i2c-mux@74 { /* u18 */ 116 + compatible = "nxp,pca9546"; 117 + #address-cells = <1>; 118 + #size-cells = <0>; 119 + reg = <0x74>; 120 + usbhub_i2c0: i2c@0 { 121 + #address-cells = <1>; 122 + #size-cells = <0>; 123 + reg = <0>; 124 + hub_1: usb-hub@2d { 125 + compatible = "microchip,usb5744"; 126 + reg = <0x2d>; 127 + }; 128 + }; 129 + usbhub_i2c1: i2c@1 { 130 + #address-cells = <1>; 131 + #size-cells = <0>; 132 + reg = <1>; 133 + hub_2: usb-hub@2d { 134 + compatible = "microchip,usb5744"; 135 + reg = <0x2d>; 136 + }; 137 + }; 138 + /* Bus 2/3 are not connected */ 139 + }; 140 + 141 + /* si5332@6a - u17 - clock-generator */ 142 + }; 143 + 144 + /* GEM SGMII/DP and USB 3.0 */ 145 + &psgtr { 146 + status = "okay"; 147 + /* gem0/1, dp, usb */ 148 + clocks = <&clk_125>, <&clk_27>, <&clk_26>; 149 + clock-names = "ref0", "ref1", "ref2"; 150 + }; 151 + 152 + &zynqmp_dpsub { 153 + status = "okay"; 154 + phy-names = "dp-phy0"; 155 + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; 156 + assigned-clock-rates = <27000000>, <25000000>, <300000000>; 157 + }; 158 + 159 + &out_dp { 160 + dpsub_dp_out: endpoint { 161 + remote-endpoint = <&dpcon_in>; 162 + }; 163 + }; 164 + 165 + &zynqmp_dpdma { 166 + status = "okay"; 167 + assigned-clock-rates = <600000000>; 168 + }; 169 + 170 + &usb0 { /* mio52 - mio63 */ 171 + status = "okay"; 172 + pinctrl-names = "default"; 173 + pinctrl-0 = <&pinctrl_usb0_default>; 174 + phy-names = "usb3-phy"; 175 + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 176 + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; 177 + assigned-clock-rates = <250000000>, <20000000>; 178 + }; 179 + 180 + &dwc3_0 { 181 + status = "okay"; 182 + dr_mode = "host"; 183 + snps,usb3_lpm_capable; 184 + maximum-speed = "super-speed"; 185 + #address-cells = <1>; 186 + #size-cells = <0>; 187 + 188 + /* 2.0 hub on port 1 */ 189 + hub_2_0: hub@1 { 190 + compatible = "usb424,2744"; 191 + reg = <1>; 192 + peer-hub = <&hub_3_0>; 193 + i2c-bus = <&hub_1>; 194 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 195 + }; 196 + 197 + /* 3.0 hub on port 2 */ 198 + hub_3_0: hub@2 { 199 + compatible = "usb424,5744"; 200 + reg = <2>; 201 + peer-hub = <&hub_2_0>; 202 + i2c-bus = <&hub_1>; 203 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 204 + }; 205 + }; 206 + 207 + &usb1 { /* mio64 - mio75 */ 208 + status = "okay"; 209 + pinctrl-names = "default"; 210 + pinctrl-0 = <&pinctrl_usb1_default>; 211 + phy-names = "usb3-phy"; 212 + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; 213 + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; 214 + assigned-clock-rates = <250000000>, <20000000>; 215 + }; 216 + 217 + &dwc3_1 { 218 + status = "okay"; 219 + dr_mode = "host"; 220 + snps,usb3_lpm_capable; 221 + maximum-speed = "super-speed"; 222 + #address-cells = <1>; 223 + #size-cells = <0>; 224 + 225 + /* 2.0 hub on port 1 */ 226 + hub1_2_0: hub@1 { 227 + compatible = "usb424,2744"; 228 + reg = <1>; 229 + peer-hub = <&hub1_3_0>; 230 + i2c-bus = <&hub_2>; 231 + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; 232 + }; 233 + 234 + /* 3.0 hub on port 2 */ 235 + hub1_3_0: hub@2 { 236 + compatible = "usb424,5744"; 237 + reg = <2>; 238 + peer-hub = <&hub1_2_0>; 239 + i2c-bus = <&hub_2>; 240 + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; 241 + }; 242 + }; 243 + 244 + &gem0 { /* mdio mio50/51 */ 245 + status = "okay"; 246 + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; 247 + phy-handle = <&phy0>; 248 + phy-mode = "sgmii"; 249 + assigned-clock-rates = <250000000>; 250 + }; 251 + 252 + &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ 253 + status = "okay"; 254 + pinctrl-names = "default"; 255 + pinctrl-0 = <&pinctrl_gem1_default>; 256 + phy-handle = <&phy1>; 257 + phy-mode = "rgmii-id"; 258 + assigned-clock-rates = <250000000>; 259 + 260 + mdio: mdio { 261 + #address-cells = <1>; 262 + #size-cells = <0>; 263 + phy0: ethernet-phy@4 { /* u81 */ 264 + #phy-cells = <1>; 265 + compatible = "ethernet-phy-id2000.a231"; 266 + reg = <4>; 267 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 268 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 269 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 270 + ti,dp83867-rxctrl-strap-quirk; 271 + reset-assert-us = <300>; 272 + reset-deassert-us = <280>; 273 + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; 274 + }; 275 + phy1: ethernet-phy@8 { /* u36 */ 276 + #phy-cells = <1>; 277 + compatible = "ethernet-phy-id2000.a231"; 278 + reg = <8>; 279 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 280 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 281 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 282 + ti,dp83867-rxctrl-strap-quirk; 283 + reset-assert-us = <100>; 284 + reset-deassert-us = <280>; 285 + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; 286 + }; 287 + }; 288 + }; 289 + 290 + /* gem2/gem3 via PL with phys u79@2 and u80@3 */ 291 + 292 + &pinctrl0 { 293 + status = "okay"; 294 + 295 + pinctrl_uart1_default: uart1-default { 296 + conf { 297 + groups = "uart1_9_grp"; 298 + slew-rate = <SLEW_RATE_SLOW>; 299 + power-source = <IO_STANDARD_LVCMOS18>; 300 + drive-strength = <12>; 301 + }; 302 + 303 + conf-rx { 304 + pins = "MIO37"; 305 + bias-high-impedance; 306 + }; 307 + 308 + conf-tx { 309 + pins = "MIO36"; 310 + bias-disable; 311 + output-enable; 312 + }; 313 + 314 + mux { 315 + groups = "uart1_9_grp"; 316 + function = "uart1"; 317 + }; 318 + }; 319 + 320 + pinctrl_i2c1_default: i2c1-default { 321 + conf { 322 + groups = "i2c1_6_grp"; 323 + bias-pull-up; 324 + slew-rate = <SLEW_RATE_SLOW>; 325 + power-source = <IO_STANDARD_LVCMOS18>; 326 + }; 327 + 328 + mux { 329 + groups = "i2c1_6_grp"; 330 + function = "i2c1"; 331 + }; 332 + }; 333 + 334 + pinctrl_i2c1_gpio: i2c1-gpio-grp { 335 + conf { 336 + groups = "gpio0_24_grp", "gpio0_25_grp"; 337 + slew-rate = <SLEW_RATE_SLOW>; 338 + power-source = <IO_STANDARD_LVCMOS18>; 339 + }; 340 + 341 + mux { 342 + groups = "gpio0_24_grp", "gpio0_25_grp"; 343 + function = "gpio0"; 344 + }; 345 + }; 346 + 347 + pinctrl_gem1_default: gem1-default { 348 + conf { 349 + groups = "ethernet1_0_grp"; 350 + slew-rate = <SLEW_RATE_SLOW>; 351 + power-source = <IO_STANDARD_LVCMOS18>; 352 + }; 353 + 354 + conf-rx { 355 + pins = "MIO44", "MIO46", "MIO48"; 356 + bias-high-impedance; 357 + low-power-disable; 358 + }; 359 + 360 + conf-bootstrap { 361 + pins = "MIO45", "MIO47", "MIO49"; 362 + bias-disable; 363 + output-enable; 364 + low-power-disable; 365 + }; 366 + 367 + conf-tx { 368 + pins = "MIO38", "MIO39", "MIO40", 369 + "MIO41", "MIO42", "MIO43"; 370 + bias-disable; 371 + output-enable; 372 + low-power-enable; 373 + }; 374 + 375 + conf-mdio { 376 + groups = "mdio1_0_grp"; 377 + slew-rate = <SLEW_RATE_SLOW>; 378 + power-source = <IO_STANDARD_LVCMOS18>; 379 + bias-disable; 380 + output-enable; 381 + }; 382 + 383 + mux-mdio { 384 + function = "mdio1"; 385 + groups = "mdio1_0_grp"; 386 + }; 387 + 388 + mux { 389 + function = "ethernet1"; 390 + groups = "ethernet1_0_grp"; 391 + }; 392 + }; 393 + 394 + pinctrl_usb0_default: usb0-default { 395 + conf { 396 + groups = "usb0_0_grp"; 397 + power-source = <IO_STANDARD_LVCMOS18>; 398 + }; 399 + 400 + conf-rx { 401 + pins = "MIO52", "MIO53", "MIO55"; 402 + bias-high-impedance; 403 + drive-strength = <12>; 404 + slew-rate = <SLEW_RATE_FAST>; 405 + }; 406 + 407 + conf-tx { 408 + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 409 + "MIO60", "MIO61", "MIO62", "MIO63"; 410 + bias-disable; 411 + output-enable; 412 + drive-strength = <4>; 413 + slew-rate = <SLEW_RATE_SLOW>; 414 + }; 415 + 416 + mux { 417 + groups = "usb0_0_grp"; 418 + function = "usb0"; 419 + }; 420 + }; 421 + 422 + pinctrl_usb1_default: usb1-default { 423 + conf { 424 + groups = "usb1_0_grp"; 425 + power-source = <IO_STANDARD_LVCMOS18>; 426 + }; 427 + 428 + conf-rx { 429 + pins = "MIO64", "MIO65", "MIO67"; 430 + bias-high-impedance; 431 + drive-strength = <12>; 432 + slew-rate = <SLEW_RATE_FAST>; 433 + }; 434 + 435 + conf-tx { 436 + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", 437 + "MIO72", "MIO73", "MIO74", "MIO75"; 438 + bias-disable; 439 + output-enable; 440 + drive-strength = <4>; 441 + slew-rate = <SLEW_RATE_SLOW>; 442 + }; 443 + 444 + mux { 445 + groups = "usb1_0_grp"; 446 + function = "usb1"; 447 + }; 448 + }; 449 + }; 450 + 451 + &uart1 { 452 + status = "okay"; 453 + pinctrl-names = "default"; 454 + pinctrl-0 = <&pinctrl_uart1_default>; 455 + };
+456
arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for KR260 revB Carrier Card (A03 revision) 4 + * 5 + * (C) Copyright 2021 - 2022, Xilinx, Inc. 6 + * 7 + * Michal Simek <michal.simek@amd.com> 8 + */ 9 + 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/net/ti-dp83867.h> 12 + #include <dt-bindings/phy/phy.h> 13 + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 + 15 + /dts-v1/; 16 + /plugin/; 17 + 18 + &{/} { 19 + compatible = "xlnx,zynqmp-sk-kr260-revB", 20 + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; 21 + model = "ZynqMP KR260 revB"; 22 + 23 + aliases { 24 + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ 25 + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ 26 + }; 27 + 28 + ina260-u14 { 29 + compatible = "iio-hwmon"; 30 + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; 31 + }; 32 + 33 + clk_125: clock0 { /* u87 - GEM0/1 */ 34 + compatible = "fixed-clock"; 35 + #clock-cells = <0>; 36 + clock-frequency = <125000000>; 37 + }; 38 + 39 + clk_27: clock1 { /* u86 - DP */ 40 + compatible = "fixed-clock"; 41 + #clock-cells = <0>; 42 + clock-frequency = <27000000>; 43 + }; 44 + 45 + clk_26: clock2 { /* u89 - USB */ 46 + compatible = "fixed-clock"; 47 + #clock-cells = <0>; 48 + clock-frequency = <26000000>; 49 + }; 50 + 51 + clk_156: clock3 { /* u90 - SFP+ */ 52 + compatible = "fixed-clock"; 53 + #clock-cells = <0>; 54 + clock-frequency = <156250000>; 55 + }; 56 + 57 + clk_25_0: clock4 { /* u92/u91 - GEM2 */ 58 + compatible = "fixed-clock"; 59 + #clock-cells = <0>; 60 + clock-frequency = <25000000>; 61 + }; 62 + 63 + clk_25_1: clock5 { /* u92/u91 - GEM3 */ 64 + compatible = "fixed-clock"; 65 + #clock-cells = <0>; 66 + clock-frequency = <25000000>; 67 + }; 68 + 69 + clk_74: clock6 { /* u88 - SLVC-EC */ 70 + compatible = "fixed-clock"; 71 + #clock-cells = <0>; 72 + clock-frequency = <74250000>; 73 + }; 74 + 75 + dpcon { 76 + compatible = "dp-connector"; 77 + label = "P11"; 78 + type = "full-size"; 79 + 80 + port { 81 + dpcon_in: endpoint { 82 + remote-endpoint = <&dpsub_dp_out>; 83 + }; 84 + }; 85 + }; 86 + }; 87 + 88 + &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ 89 + #address-cells = <1>; 90 + #size-cells = <0>; 91 + pinctrl-names = "default", "gpio"; 92 + pinctrl-0 = <&pinctrl_i2c1_default>; 93 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 94 + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 95 + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 96 + 97 + u14: ina260@40 { /* u14 */ 98 + compatible = "ti,ina260"; 99 + #io-channel-cells = <1>; 100 + label = "ina260-u14"; 101 + reg = <0x40>; 102 + }; 103 + 104 + slg7xl45106: gpio@11 { /* u19 - reset logic */ 105 + compatible = "dlg,slg7xl45106"; 106 + reg = <0x11>; 107 + label = "resetchip"; 108 + gpio-controller; 109 + #gpio-cells = <2>; 110 + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", 111 + "SD_RESET_B", "USB0_HUB_RESET_B", 112 + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", 113 + "PS_GEM1_RESET_B", ""; 114 + }; 115 + 116 + i2c-mux@74 { /* u18 */ 117 + compatible = "nxp,pca9546"; 118 + #address-cells = <1>; 119 + #size-cells = <0>; 120 + reg = <0x74>; 121 + usbhub_i2c0: i2c@0 { 122 + #address-cells = <1>; 123 + #size-cells = <0>; 124 + reg = <0>; 125 + hub_1: usb-hub@2d { 126 + compatible = "microchip,usb5744"; 127 + reg = <0x2d>; 128 + }; 129 + }; 130 + usbhub_i2c1: i2c@1 { 131 + #address-cells = <1>; 132 + #size-cells = <0>; 133 + reg = <1>; 134 + hub_2: usb-hub@2d { 135 + compatible = "microchip,usb5744"; 136 + reg = <0x2d>; 137 + }; 138 + }; 139 + /* Bus 2/3 are not connected */ 140 + }; 141 + 142 + /* si5332@6a - u17 - clock-generator */ 143 + }; 144 + 145 + /* GEM SGMII/DP and USB 3.0 */ 146 + &psgtr { 147 + status = "okay"; 148 + /* gem0/1, dp, usb */ 149 + clocks = <&clk_125>, <&clk_27>, <&clk_26>; 150 + clock-names = "ref0", "ref1", "ref2"; 151 + }; 152 + 153 + &zynqmp_dpsub { 154 + status = "okay"; 155 + phy-names = "dp-phy0"; 156 + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; 157 + assigned-clock-rates = <27000000>, <25000000>, <300000000>; 158 + }; 159 + 160 + &out_dp { 161 + dpsub_dp_out: endpoint { 162 + remote-endpoint = <&dpcon_in>; 163 + }; 164 + }; 165 + 166 + &zynqmp_dpdma { 167 + status = "okay"; 168 + assigned-clock-rates = <600000000>; 169 + }; 170 + 171 + &usb0 { /* mio52 - mio63 */ 172 + status = "okay"; 173 + pinctrl-names = "default"; 174 + pinctrl-0 = <&pinctrl_usb0_default>; 175 + phy-names = "usb3-phy"; 176 + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 177 + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; 178 + assigned-clock-rates = <250000000>, <20000000>; 179 + }; 180 + 181 + &dwc3_0 { 182 + status = "okay"; 183 + dr_mode = "host"; 184 + snps,usb3_lpm_capable; 185 + maximum-speed = "super-speed"; 186 + #address-cells = <1>; 187 + #size-cells = <0>; 188 + 189 + /* 2.0 hub on port 1 */ 190 + hub_2_0: hub@1 { 191 + compatible = "usb424,2744"; 192 + reg = <1>; 193 + peer-hub = <&hub_3_0>; 194 + i2c-bus = <&hub_1>; 195 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 196 + }; 197 + 198 + /* 3.0 hub on port 2 */ 199 + hub_3_0: hub@2 { 200 + compatible = "usb424,5744"; 201 + reg = <2>; 202 + peer-hub = <&hub_2_0>; 203 + i2c-bus = <&hub_1>; 204 + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; 205 + }; 206 + }; 207 + 208 + &usb1 { /* mio64 - mio75 */ 209 + status = "okay"; 210 + pinctrl-names = "default"; 211 + pinctrl-0 = <&pinctrl_usb1_default>; 212 + phy-names = "usb3-phy"; 213 + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; 214 + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; 215 + assigned-clock-rates = <250000000>, <20000000>; 216 + }; 217 + 218 + &dwc3_1 { 219 + status = "okay"; 220 + dr_mode = "host"; 221 + snps,usb3_lpm_capable; 222 + maximum-speed = "super-speed"; 223 + #address-cells = <1>; 224 + #size-cells = <0>; 225 + 226 + /* 2.0 hub on port 1 */ 227 + hub1_2_0: hub@1 { 228 + compatible = "usb424,2744"; 229 + reg = <1>; 230 + peer-hub = <&hub1_3_0>; 231 + i2c-bus = <&hub_2>; 232 + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; 233 + }; 234 + 235 + /* 3.0 hub on port 2 */ 236 + hub1_3_0: hub@2 { 237 + compatible = "usb424,5744"; 238 + reg = <2>; 239 + peer-hub = <&hub1_2_0>; 240 + i2c-bus = <&hub_2>; 241 + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; 242 + }; 243 + }; 244 + 245 + &gem0 { /* mdio mio50/51 */ 246 + status = "okay"; 247 + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; 248 + phy-handle = <&phy0>; 249 + phy-mode = "sgmii"; 250 + assigned-clock-rates = <250000000>; 251 + }; 252 + 253 + &gem1 { /* mdio mio50/51, gem mio38 - mio49 */ 254 + status = "okay"; 255 + pinctrl-names = "default"; 256 + pinctrl-0 = <&pinctrl_gem1_default>; 257 + phy-handle = <&phy1>; 258 + phy-mode = "rgmii-id"; 259 + assigned-clock-rates = <250000000>; 260 + 261 + mdio: mdio { 262 + #address-cells = <1>; 263 + #size-cells = <0>; 264 + phy0: ethernet-phy@4 { /* u81 */ 265 + #phy-cells = <1>; 266 + compatible = "ethernet-phy-id2000.a231"; 267 + reg = <4>; 268 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 269 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 270 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 271 + ti,dp83867-rxctrl-strap-quirk; 272 + reset-assert-us = <300>; 273 + reset-deassert-us = <280>; 274 + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; 275 + }; 276 + phy1: ethernet-phy@8 { /* u36 */ 277 + #phy-cells = <1>; 278 + compatible = "ethernet-phy-id2000.a231"; 279 + reg = <8>; 280 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 281 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 282 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 283 + ti,dp83867-rxctrl-strap-quirk; 284 + reset-assert-us = <100>; 285 + reset-deassert-us = <280>; 286 + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; 287 + }; 288 + }; 289 + }; 290 + 291 + /* gem2/gem3 via PL with phys u79@2 and u80@3 */ 292 + 293 + &pinctrl0 { 294 + status = "okay"; 295 + 296 + pinctrl_uart1_default: uart1-default { 297 + conf { 298 + groups = "uart1_9_grp"; 299 + slew-rate = <SLEW_RATE_SLOW>; 300 + power-source = <IO_STANDARD_LVCMOS18>; 301 + drive-strength = <12>; 302 + }; 303 + 304 + conf-rx { 305 + pins = "MIO37"; 306 + bias-high-impedance; 307 + }; 308 + 309 + conf-tx { 310 + pins = "MIO36"; 311 + bias-disable; 312 + output-enable; 313 + }; 314 + 315 + mux { 316 + groups = "uart1_9_grp"; 317 + function = "uart1"; 318 + }; 319 + }; 320 + 321 + pinctrl_i2c1_default: i2c1-default { 322 + conf { 323 + groups = "i2c1_6_grp"; 324 + bias-pull-up; 325 + slew-rate = <SLEW_RATE_SLOW>; 326 + power-source = <IO_STANDARD_LVCMOS18>; 327 + }; 328 + 329 + mux { 330 + groups = "i2c1_6_grp"; 331 + function = "i2c1"; 332 + }; 333 + }; 334 + 335 + pinctrl_i2c1_gpio: i2c1-gpio-grp { 336 + conf { 337 + groups = "gpio0_24_grp", "gpio0_25_grp"; 338 + slew-rate = <SLEW_RATE_SLOW>; 339 + power-source = <IO_STANDARD_LVCMOS18>; 340 + }; 341 + 342 + mux { 343 + groups = "gpio0_24_grp", "gpio0_25_grp"; 344 + function = "gpio0"; 345 + }; 346 + }; 347 + 348 + pinctrl_gem1_default: gem1-default { 349 + conf { 350 + groups = "ethernet1_0_grp"; 351 + slew-rate = <SLEW_RATE_SLOW>; 352 + power-source = <IO_STANDARD_LVCMOS18>; 353 + }; 354 + 355 + conf-rx { 356 + pins = "MIO44", "MIO46", "MIO48"; 357 + bias-high-impedance; 358 + low-power-disable; 359 + }; 360 + 361 + conf-bootstrap { 362 + pins = "MIO45", "MIO47", "MIO49"; 363 + bias-disable; 364 + output-enable; 365 + low-power-disable; 366 + }; 367 + 368 + conf-tx { 369 + pins = "MIO38", "MIO39", "MIO40", 370 + "MIO41", "MIO42", "MIO43"; 371 + bias-disable; 372 + output-enable; 373 + low-power-enable; 374 + }; 375 + 376 + conf-mdio { 377 + groups = "mdio1_0_grp"; 378 + slew-rate = <SLEW_RATE_SLOW>; 379 + power-source = <IO_STANDARD_LVCMOS18>; 380 + bias-disable; 381 + output-enable; 382 + }; 383 + 384 + mux-mdio { 385 + function = "mdio1"; 386 + groups = "mdio1_0_grp"; 387 + }; 388 + 389 + mux { 390 + function = "ethernet1"; 391 + groups = "ethernet1_0_grp"; 392 + }; 393 + }; 394 + 395 + pinctrl_usb0_default: usb0-default { 396 + conf { 397 + groups = "usb0_0_grp"; 398 + power-source = <IO_STANDARD_LVCMOS18>; 399 + }; 400 + 401 + conf-rx { 402 + pins = "MIO52", "MIO53", "MIO55"; 403 + bias-high-impedance; 404 + drive-strength = <12>; 405 + slew-rate = <SLEW_RATE_FAST>; 406 + }; 407 + 408 + conf-tx { 409 + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 410 + "MIO60", "MIO61", "MIO62", "MIO63"; 411 + bias-disable; 412 + output-enable; 413 + drive-strength = <4>; 414 + slew-rate = <SLEW_RATE_SLOW>; 415 + }; 416 + 417 + mux { 418 + groups = "usb0_0_grp"; 419 + function = "usb0"; 420 + }; 421 + }; 422 + 423 + pinctrl_usb1_default: usb1-default { 424 + conf { 425 + groups = "usb1_0_grp"; 426 + power-source = <IO_STANDARD_LVCMOS18>; 427 + }; 428 + 429 + conf-rx { 430 + pins = "MIO64", "MIO65", "MIO67"; 431 + bias-high-impedance; 432 + drive-strength = <12>; 433 + slew-rate = <SLEW_RATE_FAST>; 434 + }; 435 + 436 + conf-tx { 437 + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", 438 + "MIO72", "MIO73", "MIO74", "MIO75"; 439 + bias-disable; 440 + output-enable; 441 + drive-strength = <4>; 442 + slew-rate = <SLEW_RATE_SLOW>; 443 + }; 444 + 445 + mux { 446 + groups = "usb1_0_grp"; 447 + function = "usb1"; 448 + }; 449 + }; 450 + }; 451 + 452 + &uart1 { 453 + status = "okay"; 454 + pinctrl-names = "default"; 455 + pinctrl-0 = <&pinctrl_uart1_default>; 456 + };
+39 -1
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
··· 28 28 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; 29 29 model = "ZynqMP KV260 revA"; 30 30 31 + aliases { 32 + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ 33 + }; 34 + 31 35 ina260-u14 { 32 36 compatible = "iio-hwmon"; 33 37 io-channels = <&u14 0>, <&u14 1>, <&u14 2>; ··· 71 67 compatible = "fixed-clock"; 72 68 #clock-cells = <0>; 73 69 clock-frequency = <27000000>; 70 + }; 71 + dpcon { 72 + compatible = "dp-connector"; 73 + label = "P11"; 74 + type = "full-size"; 75 + 76 + port { 77 + dpcon_in: endpoint { 78 + remote-endpoint = <&dpsub_dp_out>; 79 + }; 80 + }; 74 81 }; 75 82 }; 76 83 ··· 133 118 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 134 119 }; 135 120 121 + &out_dp { 122 + dpsub_dp_out: endpoint { 123 + remote-endpoint = <&dpcon_in>; 124 + }; 125 + }; 126 + 136 127 &zynqmp_dpdma { 137 128 status = "okay"; 138 129 assigned-clock-rates = <600000000>; ··· 150 129 pinctrl-0 = <&pinctrl_usb0_default>; 151 130 phy-names = "usb3-phy"; 152 131 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 153 - /* missing usb5744 - u43 */ 154 132 }; 155 133 156 134 &dwc3_0 { ··· 157 137 dr_mode = "host"; 158 138 snps,usb3_lpm_capable; 159 139 maximum-speed = "super-speed"; 140 + #address-cells = <1>; 141 + #size-cells = <0>; 142 + 143 + /* 2.0 hub on port 1 */ 144 + hub_2_0: hub@1 { 145 + compatible = "usb424,2744"; 146 + reg = <1>; 147 + peer-hub = <&hub_3_0>; 148 + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; 149 + }; 150 + 151 + /* 3.0 hub on port 2 */ 152 + hub_3_0: hub@2 { 153 + compatible = "usb424,5744"; 154 + reg = <2>; 155 + peer-hub = <&hub_2_0>; 156 + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; 157 + }; 160 158 }; 161 159 162 160 &sdhci1 { /* on CC with tuned parameters */
+32 -7
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
··· 23 23 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; 24 24 model = "ZynqMP KV260 revB"; 25 25 26 + aliases { 27 + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ 28 + }; 29 + 26 30 ina260-u14 { 27 31 compatible = "iio-hwmon"; 28 32 io-channels = <&u14 0>, <&u14 1>, <&u14 2>; ··· 96 92 label = "ina260-u14"; 97 93 reg = <0x40>; 98 94 }; 99 - /* u43 - 0x2d - USB hub */ 95 + hub: usb-hub@2d { 96 + compatible = "microchip,usb5744"; 97 + reg = <0x2d>; 98 + }; 100 99 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 101 100 }; 102 101 ··· 116 109 phy-names = "dp-phy0", "dp-phy1"; 117 110 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 118 111 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 112 + }; 119 113 120 - ports { 121 - port@5 { 122 - dpsub_dp_out: endpoint { 123 - remote-endpoint = <&dpcon_in>; 124 - }; 125 - }; 114 + &out_dp { 115 + dpsub_dp_out: endpoint { 116 + remote-endpoint = <&dpcon_in>; 126 117 }; 127 118 }; 128 119 ··· 143 138 dr_mode = "host"; 144 139 snps,usb3_lpm_capable; 145 140 maximum-speed = "super-speed"; 141 + #address-cells = <1>; 142 + #size-cells = <0>; 143 + 144 + /* 2.0 hub on port 1 */ 145 + hub_2_0: hub@1 { 146 + compatible = "usb424,2744"; 147 + reg = <1>; 148 + peer-hub = <&hub_3_0>; 149 + i2c-bus = <&hub>; 150 + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; 151 + }; 152 + 153 + /* 3.0 hub on port 2 */ 154 + hub_3_0: hub@2 { 155 + compatible = "usb424,5744"; 156 + reg = <2>; 157 + peer-hub = <&hub_2_0>; 158 + i2c-bus = <&hub>; 159 + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; 160 + }; 146 161 }; 147 162 148 163 &sdhci1 { /* on CC with tuned parameters */
+23
arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for Xilinx ZynqMP SM-K24 RevA 4 + * 5 + * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 + * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 + * 8 + * Michal Simek <michal.simek@amd.com> 9 + */ 10 + 11 + #include "zynqmp-sm-k26-revA.dts" 12 + 13 + / { 14 + model = "ZynqMP SM-K24 RevA/B/1"; 15 + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", 16 + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", 17 + "xlnx,zynqmp"; 18 + 19 + memory@0 { 20 + device_type = "memory"; /* 2GB */ 21 + reg = <0 0 0 0x80000000>; 22 + }; 23 + };
+5 -2
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
··· 90 90 }; 91 91 }; 92 92 93 - pwm-fan { 93 + pwm_fan: pwm-fan { 94 94 compatible = "pwm-fan"; 95 95 status = "okay"; 96 - pwms = <&ttc0 2 40000 0>; 96 + pwms = <&ttc0 2 40000 1>; 97 97 }; 98 98 }; 99 99 ··· 233 233 pinctrl-0 = <&pinctrl_sdhci0_default>; 234 234 non-removable; 235 235 disable-wp; 236 + no-sd; 237 + no-sdio; 238 + cap-mmc-hw-reset; 236 239 bus-width = <8>; 237 240 xlnx,mio-bank = <0>; 238 241 assigned-clock-rates = <187498123>;
+21
arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * dts file for Xilinx ZynqMP SMK-K24 RevA 4 + * 5 + * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 + * (C) Copyright 2022, Advanced Micro Devices, Inc. 7 + * 8 + * Michal Simek <michal.simek@amd.com> 9 + */ 10 + 11 + #include "zynqmp-sm-k24-revA.dts" 12 + 13 + / { 14 + model = "ZynqMP SMK-K24 RevA"; 15 + compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", 16 + "xlnx,zynqmp"; 17 + }; 18 + 19 + &sdhci0 { 20 + status = "disabled"; 21 + };
-1
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
··· 135 135 status = "okay"; 136 136 pinctrl-names = "default"; 137 137 pinctrl-0 = <&pinctrl_nand0_default>; 138 - arasan,has-mdma; 139 138 140 139 nand@0 { 141 140 reg = <0x0>;
-1
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
··· 129 129 /* MT29F64G08AECDBJ4-6 */ 130 130 &nand0 { 131 131 status = "okay"; 132 - arasan,has-mdma; 133 132 num-cs = <2>; 134 133 }; 135 134
+21
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
··· 134 134 #clock-cells = <0>; 135 135 clock-frequency = <27000000>; 136 136 }; 137 + 138 + dpcon { 139 + compatible = "dp-connector"; 140 + label = "P11"; 141 + type = "full-size"; 142 + 143 + port { 144 + dpcon_in: endpoint { 145 + remote-endpoint = <&dpsub_dp_out>; 146 + }; 147 + }; 148 + }; 137 149 }; 138 150 139 151 &dcc { ··· 521 509 xlnx,mio-bank = <0>; 522 510 non-removable; 523 511 disable-wp; 512 + no-sd; 513 + no-sdio; 514 + cap-mmc-hw-reset; 524 515 cap-power-off-card; 525 516 mmc-pwrseq = <&sdio_pwrseq>; 526 517 vqmmc-supply = <&wmmcsdio_fixed>; ··· 618 603 phy-names = "dp-phy0", "dp-phy1"; 619 604 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 620 605 <&psgtr 0 PHY_TYPE_DP 1 1>; 606 + }; 607 + 608 + &out_dp { 609 + dpsub_dp_out: endpoint { 610 + remote-endpoint = <&dpcon_in>; 611 + }; 621 612 };
+18
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
··· 151 151 #clock-cells = <0>; 152 152 clock-frequency = <114285000>; 153 153 }; 154 + 155 + dpcon { 156 + compatible = "dp-connector"; 157 + label = "P11"; 158 + type = "full-size"; 159 + 160 + port { 161 + dpcon_in: endpoint { 162 + remote-endpoint = <&dpsub_dp_out>; 163 + }; 164 + }; 165 + }; 154 166 }; 155 167 156 168 &can1 { ··· 1056 1044 status = "okay"; 1057 1045 phy-names = "dp-phy0"; 1058 1046 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1047 + }; 1048 + 1049 + &out_dp { 1050 + dpsub_dp_out: endpoint { 1051 + remote-endpoint = <&dpcon_in>; 1052 + }; 1059 1053 };
+18
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
··· 60 60 #clock-cells = <0>; 61 61 clock-frequency = <27000000>; 62 62 }; 63 + 64 + dpcon { 65 + compatible = "dp-connector"; 66 + label = "P11"; 67 + type = "full-size"; 68 + 69 + port { 70 + dpcon_in: endpoint { 71 + remote-endpoint = <&dpsub_dp_out>; 72 + }; 73 + }; 74 + }; 63 75 }; 64 76 65 77 &can1 { ··· 540 528 phy-names = "dp-phy0", "dp-phy1"; 541 529 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 542 530 <&psgtr 0 PHY_TYPE_DP 1 3>; 531 + }; 532 + 533 + &out_dp { 534 + dpsub_dp_out: endpoint { 535 + remote-endpoint = <&dpcon_in>; 536 + }; 543 537 };
+18
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
··· 65 65 #clock-cells = <0>; 66 66 clock-frequency = <27000000>; 67 67 }; 68 + 69 + dpcon { 70 + compatible = "dp-connector"; 71 + label = "P11"; 72 + type = "full-size"; 73 + 74 + port { 75 + dpcon_in: endpoint { 76 + remote-endpoint = <&dpsub_dp_out>; 77 + }; 78 + }; 79 + }; 68 80 }; 69 81 70 82 &can1 { ··· 552 540 phy-names = "dp-phy0", "dp-phy1"; 553 541 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 554 542 <&psgtr 0 PHY_TYPE_DP 1 3>; 543 + }; 544 + 545 + &out_dp { 546 + dpsub_dp_out: endpoint { 547 + remote-endpoint = <&dpcon_in>; 548 + }; 555 549 };
+6 -8
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
··· 808 808 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 809 809 "MIO60", "MIO61", "MIO62", "MIO63"; 810 810 bias-disable; 811 - drive-strength = <4>; 812 - slew-rate = <SLEW_RATE_SLOW>; 811 + drive-strength = <12>; 812 + slew-rate = <SLEW_RATE_FAST>; 813 813 }; 814 814 }; 815 815 ··· 1042 1042 phy-names = "dp-phy0", "dp-phy1"; 1043 1043 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 1044 1044 <&psgtr 0 PHY_TYPE_DP 1 3>; 1045 + }; 1045 1046 1046 - ports { 1047 - port@5 { 1048 - dpsub_dp_out: endpoint { 1049 - remote-endpoint = <&dpcon_in>; 1050 - }; 1051 - }; 1047 + &out_dp { 1048 + dpsub_dp_out: endpoint { 1049 + remote-endpoint = <&dpcon_in>; 1052 1050 }; 1053 1051 };
+19 -1
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
··· 129 129 #clock-cells = <0>; 130 130 clock-frequency = <48000000>; 131 131 }; 132 + 133 + dpcon { 134 + compatible = "dp-connector"; 135 + label = "P11"; 136 + type = "full-size"; 137 + 138 + port { 139 + dpcon_in: endpoint { 140 + remote-endpoint = <&dpsub_dp_out>; 141 + }; 142 + }; 143 + }; 132 144 }; 133 145 134 146 &dcc { ··· 506 494 #address-cells = <1>; 507 495 #size-cells = <0>; 508 496 reg = <5>; 509 - sc18is603@2f { /* sc18is602 - u93 */ 497 + sc18is603: spi@2f { /* sc18is602 - u93 */ 510 498 compatible = "nxp,sc18is603"; 511 499 reg = <0x2f>; 512 500 /* 4 gpios for CS not handled by driver */ ··· 875 863 phy-names = "dp-phy0", "dp-phy1"; 876 864 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 877 865 <&psgtr 0 PHY_TYPE_DP 1 1>; 866 + }; 867 + 868 + &out_dp { 869 + dpsub_dp_out: endpoint { 870 + remote-endpoint = <&dpcon_in>; 871 + }; 878 872 };
+11 -7
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
··· 187 187 }; 188 188 189 189 psci { 190 - compatible = "arm,psci-0.2"; 190 + compatible = "arm,psci-1.0", "arm,psci-0.2"; 191 191 method = "smc"; 192 192 }; 193 193 ··· 550 550 reg = <0x0 0xfec10000 0x0 0x1000>; 551 551 clock-names = "apb_pclk"; 552 552 cpu = <&cpu0>; 553 + status = "disabled"; 553 554 }; 554 555 555 556 cpu1_debug: debug@fed10000 { ··· 558 557 reg = <0x0 0xfed10000 0x0 0x1000>; 559 558 clock-names = "apb_pclk"; 560 559 cpu = <&cpu1>; 560 + status = "disabled"; 561 561 }; 562 562 563 563 cpu2_debug: debug@fee10000 { ··· 566 564 reg = <0x0 0xfee10000 0x0 0x1000>; 567 565 clock-names = "apb_pclk"; 568 566 cpu = <&cpu2>; 567 + status = "disabled"; 569 568 }; 570 569 571 570 cpu3_debug: debug@fef10000 { ··· 574 571 reg = <0x0 0xfef10000 0x0 0x1000>; 575 572 clock-names = "apb_pclk"; 576 573 cpu = <&cpu3>; 574 + status = "disabled"; 577 575 }; 578 576 579 577 /* GDMA */ ··· 1323 1319 #address-cells = <1>; 1324 1320 #size-cells = <0>; 1325 1321 1326 - port@0 { 1322 + live_video: port@0 { 1327 1323 reg = <0>; 1328 1324 }; 1329 - port@1 { 1325 + live_gfx: port@1 { 1330 1326 reg = <1>; 1331 1327 }; 1332 - port@2 { 1328 + live_audio: port@2 { 1333 1329 reg = <2>; 1334 1330 }; 1335 - port@3 { 1331 + out_video: port@3 { 1336 1332 reg = <3>; 1337 1333 }; 1338 - port@4 { 1334 + out_audio: port@4 { 1339 1335 reg = <4>; 1340 1336 }; 1341 - port@5 { 1337 + out_dp: port@5 { 1342 1338 reg = <5>; 1343 1339 }; 1344 1340 };