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pwm: pwm-mediatek: Add support for PWM IP V3.0.2 in MT6991/MT8196

Add support for the PWM IP version 3.0.2, found in MediaTek's
Dimensity 9400 MT6991 and in the MT8196 Chromebook SoC: this
needs a new register offset array and also a different offset
for the PWM_CK_26M_SEL register.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250623120118.109170-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Uwe Kleine-König e47026fa d4f1e7a2

+14
+14
drivers/pwm/pwm-mediatek.c
··· 29 29 #define PWM45DWIDTH_FIXUP 0x30 30 30 #define PWMTHRES 0x30 31 31 #define PWM45THRES_FIXUP 0x34 32 + #define PWM_CK_26M_SEL_V3 0x74 32 33 #define PWM_CK_26M_SEL 0x210 33 34 34 35 #define PWM_CLK_DIV_MAX 7 ··· 63 62 64 63 static const unsigned int mtk_pwm_reg_offset_v2[] = { 65 64 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 65 + }; 66 + 67 + /* PWM IP Version 3.0.2 */ 68 + static const unsigned int mtk_pwm_reg_offset_v3[] = { 69 + 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800 66 70 }; 67 71 68 72 static inline struct pwm_mediatek_chip * ··· 375 369 .reg_offset = mtk_pwm_reg_offset_v1, 376 370 }; 377 371 372 + static const struct pwm_mediatek_of_data mt6991_pwm_data = { 373 + .num_pwms = 4, 374 + .pwm45_fixup = false, 375 + .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3, 376 + .reg_offset = mtk_pwm_reg_offset_v3, 377 + }; 378 + 378 379 static const struct of_device_id pwm_mediatek_of_match[] = { 379 380 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 380 381 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data }, 382 + { .compatible = "mediatek,mt6991-pwm", .data = &mt6991_pwm_data }, 381 383 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 382 384 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 383 385 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },