Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add GMC 9.0 support (v2)
On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).
v2: drop sdma from Makefile, fix duplicate return statement.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Alex Xie
and committed by
Alex Deucher
e60f8db5
c1d83da9
+2013
-7
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+30
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+30
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
121
121
/* max number of IP instances */
122
122
#define AMDGPU_MAX_SDMA_INSTANCES 2
123
123
124
+
/* max number of VMHUB */
125
+
#define AMDGPU_MAX_VMHUBS 2
126
+
#define AMDGPU_MMHUB 0
127
+
#define AMDGPU_GFXHUB 1
128
+
124
129
/* hardcode that limit for now */
125
130
#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
126
131
···
311
306
/* set pte flags based per asic */
312
307
uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
313
308
uint32_t flags);
309
+
};
310
+
311
+
/* provided by the mc block */
312
+
struct amdgpu_mc_funcs {
313
+
/* adjust mc addr in fb for APU case */
314
+
u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
314
315
};
315
316
316
317
/* provided by the ih block */
···
568
557
int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
569
558
570
559
/*
560
+
* VMHUB structures, functions & helpers
561
+
*/
562
+
struct amdgpu_vmhub {
563
+
uint32_t ctx0_ptb_addr_lo32;
564
+
uint32_t ctx0_ptb_addr_hi32;
565
+
uint32_t vm_inv_eng0_req;
566
+
uint32_t vm_inv_eng0_ack;
567
+
uint32_t vm_context0_cntl;
568
+
uint32_t vm_l2_pro_fault_status;
569
+
uint32_t vm_l2_pro_fault_cntl;
570
+
uint32_t (*get_invalidate_req)(unsigned int vm_id);
571
+
uint32_t (*get_vm_protection_bits)(void);
572
+
};
573
+
574
+
/*
571
575
* GPU MC structures, functions & helpers
572
576
*/
573
577
struct amdgpu_mc {
···
615
589
u64 shared_aperture_end;
616
590
u64 private_aperture_start;
617
591
u64 private_aperture_end;
592
+
/* protects concurrent invalidation */
593
+
spinlock_t invalidate_lock;
594
+
const struct amdgpu_mc_funcs *mc_funcs;
618
595
};
619
596
620
597
/*
···
1502
1473
struct amdgpu_gart gart;
1503
1474
struct amdgpu_dummy_page dummy_page;
1504
1475
struct amdgpu_vm_manager vm_manager;
1476
+
struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1505
1477
1506
1478
/* memory management */
1507
1479
struct amdgpu_mman mman;
+22
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+22
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
447
447
return false;
448
448
}
449
449
450
+
static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
451
+
{
452
+
u64 addr = mc_addr;
453
+
454
+
if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
455
+
addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);
456
+
457
+
return addr;
458
+
}
459
+
450
460
/**
451
461
* amdgpu_vm_flush - hardware flush the vm
452
462
*
···
487
477
if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
488
478
amdgpu_vm_is_gpu_reset(adev, id))) {
489
479
struct dma_fence *fence;
480
+
u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
490
481
491
-
trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id);
492
-
amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
482
+
trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
483
+
amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
493
484
494
485
r = amdgpu_fence_emit(ring, &fence);
495
486
if (r)
···
726
715
(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
727
716
728
717
if (count) {
718
+
uint64_t pt_addr =
719
+
amdgpu_vm_adjust_mc_addr(adev, last_pt);
720
+
729
721
if (shadow)
730
722
amdgpu_vm_do_set_ptes(¶ms,
731
723
last_shadow,
732
-
last_pt, count,
724
+
pt_addr, count,
733
725
incr,
734
726
AMDGPU_PTE_VALID);
735
727
736
728
amdgpu_vm_do_set_ptes(¶ms, last_pde,
737
-
last_pt, count, incr,
729
+
pt_addr, count, incr,
738
730
AMDGPU_PTE_VALID);
739
731
}
740
732
···
751
737
}
752
738
753
739
if (count) {
740
+
uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
741
+
754
742
if (vm->page_directory->shadow)
755
-
amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt,
743
+
amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr,
756
744
count, incr, AMDGPU_PTE_VALID);
757
745
758
-
amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt,
746
+
amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr,
759
747
count, incr, AMDGPU_PTE_VALID);
760
748
}
761
749
+447
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+447
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#include "amdgpu.h"
24
+
#include "gfxhub_v1_0.h"
25
+
26
+
#include "vega10/soc15ip.h"
27
+
#include "vega10/GC/gc_9_0_offset.h"
28
+
#include "vega10/GC/gc_9_0_sh_mask.h"
29
+
#include "vega10/GC/gc_9_0_default.h"
30
+
#include "vega10/vega10_enum.h"
31
+
32
+
#include "soc15_common.h"
33
+
34
+
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
35
+
{
36
+
u32 tmp;
37
+
u64 value;
38
+
u32 i;
39
+
40
+
/* Program MC. */
41
+
/* Update configuration */
42
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
43
+
adev->mc.vram_start >> 18);
44
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
45
+
adev->mc.vram_end >> 18);
46
+
47
+
value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
48
+
+ adev->vm_manager.vram_base_offset;
49
+
WREG32(SOC15_REG_OFFSET(GC, 0,
50
+
mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
51
+
(u32)(value >> 12));
52
+
WREG32(SOC15_REG_OFFSET(GC, 0,
53
+
mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
54
+
(u32)(value >> 44));
55
+
56
+
/* Disable AGP. */
57
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
58
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
59
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
60
+
61
+
/* GART Enable. */
62
+
63
+
/* Setup TLB control */
64
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
65
+
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
66
+
tmp = REG_SET_FIELD(tmp,
67
+
MC_VM_MX_L1_TLB_CNTL,
68
+
SYSTEM_ACCESS_MODE,
69
+
3);
70
+
tmp = REG_SET_FIELD(tmp,
71
+
MC_VM_MX_L1_TLB_CNTL,
72
+
ENABLE_ADVANCED_DRIVER_MODEL,
73
+
1);
74
+
tmp = REG_SET_FIELD(tmp,
75
+
MC_VM_MX_L1_TLB_CNTL,
76
+
SYSTEM_APERTURE_UNMAPPED_ACCESS,
77
+
0);
78
+
tmp = REG_SET_FIELD(tmp,
79
+
MC_VM_MX_L1_TLB_CNTL,
80
+
ECO_BITS,
81
+
0);
82
+
tmp = REG_SET_FIELD(tmp,
83
+
MC_VM_MX_L1_TLB_CNTL,
84
+
MTYPE,
85
+
MTYPE_UC);/* XXX for emulation. */
86
+
tmp = REG_SET_FIELD(tmp,
87
+
MC_VM_MX_L1_TLB_CNTL,
88
+
ATC_EN,
89
+
1);
90
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
91
+
92
+
/* Setup L2 cache */
93
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
94
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
95
+
tmp = REG_SET_FIELD(tmp,
96
+
VM_L2_CNTL,
97
+
ENABLE_L2_FRAGMENT_PROCESSING,
98
+
0);
99
+
tmp = REG_SET_FIELD(tmp,
100
+
VM_L2_CNTL,
101
+
L2_PDE0_CACHE_TAG_GENERATION_MODE,
102
+
0);/* XXX for emulation, Refer to closed source code.*/
103
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
104
+
tmp = REG_SET_FIELD(tmp,
105
+
VM_L2_CNTL,
106
+
CONTEXT1_IDENTITY_ACCESS_MODE,
107
+
1);
108
+
tmp = REG_SET_FIELD(tmp,
109
+
VM_L2_CNTL,
110
+
IDENTITY_MODE_FRAGMENT_SIZE,
111
+
0);
112
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
113
+
114
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
115
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
116
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
117
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
118
+
119
+
tmp = mmVM_L2_CNTL3_DEFAULT;
120
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
121
+
122
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
123
+
tmp = REG_SET_FIELD(tmp,
124
+
VM_L2_CNTL4,
125
+
VMC_TAP_PDE_REQUEST_PHYSICAL,
126
+
0);
127
+
tmp = REG_SET_FIELD(tmp,
128
+
VM_L2_CNTL4,
129
+
VMC_TAP_PTE_REQUEST_PHYSICAL,
130
+
0);
131
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
132
+
133
+
/* setup context0 */
134
+
WREG32(SOC15_REG_OFFSET(GC, 0,
135
+
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
136
+
(u32)(adev->mc.gtt_start >> 12));
137
+
WREG32(SOC15_REG_OFFSET(GC, 0,
138
+
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
139
+
(u32)(adev->mc.gtt_start >> 44));
140
+
141
+
WREG32(SOC15_REG_OFFSET(GC, 0,
142
+
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
143
+
(u32)(adev->mc.gtt_end >> 12));
144
+
WREG32(SOC15_REG_OFFSET(GC, 0,
145
+
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
146
+
(u32)(adev->mc.gtt_end >> 44));
147
+
148
+
BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
149
+
value = adev->gart.table_addr - adev->mc.vram_start
150
+
+ adev->vm_manager.vram_base_offset;
151
+
value &= 0x0000FFFFFFFFF000ULL;
152
+
value |= 0x1; /*valid bit*/
153
+
154
+
WREG32(SOC15_REG_OFFSET(GC, 0,
155
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
156
+
(u32)value);
157
+
WREG32(SOC15_REG_OFFSET(GC, 0,
158
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
159
+
(u32)(value >> 32));
160
+
161
+
WREG32(SOC15_REG_OFFSET(GC, 0,
162
+
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
163
+
(u32)(adev->dummy_page.addr >> 12));
164
+
WREG32(SOC15_REG_OFFSET(GC, 0,
165
+
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
166
+
(u32)(adev->dummy_page.addr >> 44));
167
+
168
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
169
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
170
+
ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,
171
+
1);
172
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
173
+
174
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
175
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
176
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
177
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
178
+
179
+
/* Disable identity aperture.*/
180
+
WREG32(SOC15_REG_OFFSET(GC, 0,
181
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
182
+
WREG32(SOC15_REG_OFFSET(GC, 0,
183
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
184
+
185
+
WREG32(SOC15_REG_OFFSET(GC, 0,
186
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
187
+
WREG32(SOC15_REG_OFFSET(GC, 0,
188
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
189
+
190
+
WREG32(SOC15_REG_OFFSET(GC, 0,
191
+
mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
192
+
WREG32(SOC15_REG_OFFSET(GC, 0,
193
+
mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
194
+
195
+
for (i = 0; i <= 14; i++) {
196
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
197
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
198
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
199
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
200
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
201
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
202
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
203
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
204
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
205
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
206
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
207
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
208
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
209
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
210
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
211
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
212
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
213
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
214
+
PAGE_TABLE_BLOCK_SIZE,
215
+
amdgpu_vm_block_size - 9);
216
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
217
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
218
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
219
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
220
+
adev->vm_manager.max_pfn - 1);
221
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
222
+
}
223
+
224
+
225
+
return 0;
226
+
}
227
+
228
+
void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
229
+
{
230
+
u32 tmp;
231
+
u32 i;
232
+
233
+
/* Disable all tables */
234
+
for (i = 0; i < 16; i++)
235
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
236
+
237
+
/* Setup TLB control */
238
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
239
+
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
240
+
tmp = REG_SET_FIELD(tmp,
241
+
MC_VM_MX_L1_TLB_CNTL,
242
+
ENABLE_ADVANCED_DRIVER_MODEL,
243
+
0);
244
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
245
+
246
+
/* Setup L2 cache */
247
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
248
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
249
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
250
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
251
+
}
252
+
253
+
/**
254
+
* gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
255
+
*
256
+
* @adev: amdgpu_device pointer
257
+
* @value: true redirects VM faults to the default page
258
+
*/
259
+
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
260
+
bool value)
261
+
{
262
+
u32 tmp;
263
+
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
264
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
265
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
266
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
267
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
268
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
269
+
PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
270
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
271
+
PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
272
+
tmp = REG_SET_FIELD(tmp,
273
+
VM_L2_PROTECTION_FAULT_CNTL,
274
+
TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
275
+
value);
276
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
277
+
NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
278
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
279
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
280
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
281
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
282
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
283
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
284
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
285
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
286
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
287
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
288
+
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
289
+
}
290
+
291
+
static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vm_id)
292
+
{
293
+
u32 req = 0;
294
+
295
+
/* invalidate using legacy mode on vm_id*/
296
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
297
+
PER_VMID_INVALIDATE_REQ, 1 << vm_id);
298
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
299
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
300
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
301
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
302
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
303
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
304
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
305
+
CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
306
+
307
+
return req;
308
+
}
309
+
310
+
static uint32_t gfxhub_v1_0_get_vm_protection_bits(void)
311
+
{
312
+
return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
313
+
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
314
+
VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
315
+
VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
316
+
VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
317
+
VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
318
+
VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
319
+
}
320
+
321
+
static int gfxhub_v1_0_early_init(void *handle)
322
+
{
323
+
return 0;
324
+
}
325
+
326
+
static int gfxhub_v1_0_late_init(void *handle)
327
+
{
328
+
return 0;
329
+
}
330
+
331
+
static int gfxhub_v1_0_sw_init(void *handle)
332
+
{
333
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
334
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
335
+
336
+
hub->ctx0_ptb_addr_lo32 =
337
+
SOC15_REG_OFFSET(GC, 0,
338
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
339
+
hub->ctx0_ptb_addr_hi32 =
340
+
SOC15_REG_OFFSET(GC, 0,
341
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
342
+
hub->vm_inv_eng0_req =
343
+
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
344
+
hub->vm_inv_eng0_ack =
345
+
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
346
+
hub->vm_context0_cntl =
347
+
SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
348
+
hub->vm_l2_pro_fault_status =
349
+
SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
350
+
hub->vm_l2_pro_fault_cntl =
351
+
SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
352
+
353
+
hub->get_invalidate_req = gfxhub_v1_0_get_invalidate_req;
354
+
hub->get_vm_protection_bits = gfxhub_v1_0_get_vm_protection_bits;
355
+
356
+
return 0;
357
+
}
358
+
359
+
static int gfxhub_v1_0_sw_fini(void *handle)
360
+
{
361
+
return 0;
362
+
}
363
+
364
+
static int gfxhub_v1_0_hw_init(void *handle)
365
+
{
366
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
367
+
unsigned i;
368
+
369
+
for (i = 0 ; i < 18; ++i) {
370
+
WREG32(SOC15_REG_OFFSET(GC, 0,
371
+
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
372
+
2 * i, 0xffffffff);
373
+
WREG32(SOC15_REG_OFFSET(GC, 0,
374
+
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
375
+
2 * i, 0x1f);
376
+
}
377
+
378
+
return 0;
379
+
}
380
+
381
+
static int gfxhub_v1_0_hw_fini(void *handle)
382
+
{
383
+
return 0;
384
+
}
385
+
386
+
static int gfxhub_v1_0_suspend(void *handle)
387
+
{
388
+
return 0;
389
+
}
390
+
391
+
static int gfxhub_v1_0_resume(void *handle)
392
+
{
393
+
return 0;
394
+
}
395
+
396
+
static bool gfxhub_v1_0_is_idle(void *handle)
397
+
{
398
+
return true;
399
+
}
400
+
401
+
static int gfxhub_v1_0_wait_for_idle(void *handle)
402
+
{
403
+
return 0;
404
+
}
405
+
406
+
static int gfxhub_v1_0_soft_reset(void *handle)
407
+
{
408
+
return 0;
409
+
}
410
+
411
+
static int gfxhub_v1_0_set_clockgating_state(void *handle,
412
+
enum amd_clockgating_state state)
413
+
{
414
+
return 0;
415
+
}
416
+
417
+
static int gfxhub_v1_0_set_powergating_state(void *handle,
418
+
enum amd_powergating_state state)
419
+
{
420
+
return 0;
421
+
}
422
+
423
+
const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
424
+
.name = "gfxhub_v1_0",
425
+
.early_init = gfxhub_v1_0_early_init,
426
+
.late_init = gfxhub_v1_0_late_init,
427
+
.sw_init = gfxhub_v1_0_sw_init,
428
+
.sw_fini = gfxhub_v1_0_sw_fini,
429
+
.hw_init = gfxhub_v1_0_hw_init,
430
+
.hw_fini = gfxhub_v1_0_hw_fini,
431
+
.suspend = gfxhub_v1_0_suspend,
432
+
.resume = gfxhub_v1_0_resume,
433
+
.is_idle = gfxhub_v1_0_is_idle,
434
+
.wait_for_idle = gfxhub_v1_0_wait_for_idle,
435
+
.soft_reset = gfxhub_v1_0_soft_reset,
436
+
.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
437
+
.set_powergating_state = gfxhub_v1_0_set_powergating_state,
438
+
};
439
+
440
+
const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
441
+
{
442
+
.type = AMD_IP_BLOCK_TYPE_GFXHUB,
443
+
.major = 1,
444
+
.minor = 0,
445
+
.rev = 0,
446
+
.funcs = &gfxhub_v1_0_ip_funcs,
447
+
};
+35
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
+35
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __GFXHUB_V1_0_H__
25
+
#define __GFXHUB_V1_0_H__
26
+
27
+
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);
28
+
void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);
29
+
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
30
+
bool value);
31
+
32
+
extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;
33
+
extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;
34
+
35
+
#endif
+825
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+825
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#include <linux/firmware.h>
24
+
#include "amdgpu.h"
25
+
#include "gmc_v9_0.h"
26
+
27
+
#include "vega10/soc15ip.h"
28
+
#include "vega10/HDP/hdp_4_0_offset.h"
29
+
#include "vega10/HDP/hdp_4_0_sh_mask.h"
30
+
#include "vega10/GC/gc_9_0_sh_mask.h"
31
+
#include "vega10/vega10_enum.h"
32
+
33
+
#include "soc15_common.h"
34
+
35
+
#include "nbio_v6_1.h"
36
+
#include "gfxhub_v1_0.h"
37
+
#include "mmhub_v1_0.h"
38
+
39
+
#define mmDF_CS_AON0_DramBaseAddress0 0x0044
40
+
#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
41
+
//DF_CS_AON0_DramBaseAddress0
42
+
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
43
+
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
44
+
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
45
+
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
46
+
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
47
+
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
48
+
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
49
+
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
50
+
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
51
+
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
52
+
53
+
/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
54
+
#define AMDGPU_NUM_OF_VMIDS 8
55
+
56
+
static const u32 golden_settings_vega10_hdp[] =
57
+
{
58
+
0xf64, 0x0fffffff, 0x00000000,
59
+
0xf65, 0x0fffffff, 0x00000000,
60
+
0xf66, 0x0fffffff, 0x00000000,
61
+
0xf67, 0x0fffffff, 0x00000000,
62
+
0xf68, 0x0fffffff, 0x00000000,
63
+
0xf6a, 0x0fffffff, 0x00000000,
64
+
0xf6b, 0x0fffffff, 0x00000000,
65
+
0xf6c, 0x0fffffff, 0x00000000,
66
+
0xf6d, 0x0fffffff, 0x00000000,
67
+
0xf6e, 0x0fffffff, 0x00000000,
68
+
};
69
+
70
+
static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
71
+
struct amdgpu_irq_src *src,
72
+
unsigned type,
73
+
enum amdgpu_interrupt_state state)
74
+
{
75
+
struct amdgpu_vmhub *hub;
76
+
u32 tmp, reg, bits, i;
77
+
78
+
switch (state) {
79
+
case AMDGPU_IRQ_STATE_DISABLE:
80
+
/* MM HUB */
81
+
hub = &adev->vmhub[AMDGPU_MMHUB];
82
+
bits = hub->get_vm_protection_bits();
83
+
for (i = 0; i< 16; i++) {
84
+
reg = hub->vm_context0_cntl + i;
85
+
tmp = RREG32(reg);
86
+
tmp &= ~bits;
87
+
WREG32(reg, tmp);
88
+
}
89
+
90
+
/* GFX HUB */
91
+
hub = &adev->vmhub[AMDGPU_GFXHUB];
92
+
bits = hub->get_vm_protection_bits();
93
+
for (i = 0; i < 16; i++) {
94
+
reg = hub->vm_context0_cntl + i;
95
+
tmp = RREG32(reg);
96
+
tmp &= ~bits;
97
+
WREG32(reg, tmp);
98
+
}
99
+
break;
100
+
case AMDGPU_IRQ_STATE_ENABLE:
101
+
/* MM HUB */
102
+
hub = &adev->vmhub[AMDGPU_MMHUB];
103
+
bits = hub->get_vm_protection_bits();
104
+
for (i = 0; i< 16; i++) {
105
+
reg = hub->vm_context0_cntl + i;
106
+
tmp = RREG32(reg);
107
+
tmp |= bits;
108
+
WREG32(reg, tmp);
109
+
}
110
+
111
+
/* GFX HUB */
112
+
hub = &adev->vmhub[AMDGPU_GFXHUB];
113
+
bits = hub->get_vm_protection_bits();
114
+
for (i = 0; i < 16; i++) {
115
+
reg = hub->vm_context0_cntl + i;
116
+
tmp = RREG32(reg);
117
+
tmp |= bits;
118
+
WREG32(reg, tmp);
119
+
}
120
+
break;
121
+
default:
122
+
break;
123
+
}
124
+
125
+
return 0;
126
+
}
127
+
128
+
static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
129
+
struct amdgpu_irq_src *source,
130
+
struct amdgpu_iv_entry *entry)
131
+
{
132
+
struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB];
133
+
struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB];
134
+
uint32_t status;
135
+
u64 addr;
136
+
137
+
addr = (u64)entry->src_data[0] << 12;
138
+
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
139
+
140
+
if (entry->vm_id_src) {
141
+
status = RREG32(mmhub->vm_l2_pro_fault_status);
142
+
WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1);
143
+
} else {
144
+
status = RREG32(gfxhub->vm_l2_pro_fault_status);
145
+
WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1);
146
+
}
147
+
148
+
DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) "
149
+
"at page 0x%016llx from %d\n"
150
+
"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
151
+
entry->vm_id_src ? "mmhub" : "gfxhub",
152
+
entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id,
153
+
addr, entry->client_id, status);
154
+
155
+
return 0;
156
+
}
157
+
158
+
static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
159
+
.set = gmc_v9_0_vm_fault_interrupt_state,
160
+
.process = gmc_v9_0_process_interrupt,
161
+
};
162
+
163
+
static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
164
+
{
165
+
adev->mc.vm_fault.num_types = 1;
166
+
adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
167
+
}
168
+
169
+
/*
170
+
* GART
171
+
* VMID 0 is the physical GPU addresses as used by the kernel.
172
+
* VMIDs 1-15 are used for userspace clients and are handled
173
+
* by the amdgpu vm/hsa code.
174
+
*/
175
+
176
+
/**
177
+
* gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
178
+
*
179
+
* @adev: amdgpu_device pointer
180
+
* @vmid: vm instance to flush
181
+
*
182
+
* Flush the TLB for the requested page table.
183
+
*/
184
+
static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
185
+
uint32_t vmid)
186
+
{
187
+
/* Use register 17 for GART */
188
+
const unsigned eng = 17;
189
+
unsigned i, j;
190
+
191
+
/* flush hdp cache */
192
+
nbio_v6_1_hdp_flush(adev);
193
+
194
+
spin_lock(&adev->mc.invalidate_lock);
195
+
196
+
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
197
+
struct amdgpu_vmhub *hub = &adev->vmhub[i];
198
+
u32 tmp = hub->get_invalidate_req(vmid);
199
+
200
+
WREG32(hub->vm_inv_eng0_req + eng, tmp);
201
+
202
+
/* Busy wait for ACK.*/
203
+
for (j = 0; j < 100; j++) {
204
+
tmp = RREG32(hub->vm_inv_eng0_ack + eng);
205
+
tmp &= 1 << vmid;
206
+
if (tmp)
207
+
break;
208
+
cpu_relax();
209
+
}
210
+
if (j < 100)
211
+
continue;
212
+
213
+
/* Wait for ACK with a delay.*/
214
+
for (j = 0; j < adev->usec_timeout; j++) {
215
+
tmp = RREG32(hub->vm_inv_eng0_ack + eng);
216
+
tmp &= 1 << vmid;
217
+
if (tmp)
218
+
break;
219
+
udelay(1);
220
+
}
221
+
if (j < adev->usec_timeout)
222
+
continue;
223
+
224
+
DRM_ERROR("Timeout waiting for VM flush ACK!\n");
225
+
}
226
+
227
+
spin_unlock(&adev->mc.invalidate_lock);
228
+
}
229
+
230
+
/**
231
+
* gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
232
+
*
233
+
* @adev: amdgpu_device pointer
234
+
* @cpu_pt_addr: cpu address of the page table
235
+
* @gpu_page_idx: entry in the page table to update
236
+
* @addr: dst addr to write into pte/pde
237
+
* @flags: access flags
238
+
*
239
+
* Update the page tables using the CPU.
240
+
*/
241
+
static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
242
+
void *cpu_pt_addr,
243
+
uint32_t gpu_page_idx,
244
+
uint64_t addr,
245
+
uint64_t flags)
246
+
{
247
+
void __iomem *ptr = (void *)cpu_pt_addr;
248
+
uint64_t value;
249
+
250
+
/*
251
+
* PTE format on VEGA 10:
252
+
* 63:59 reserved
253
+
* 58:57 mtype
254
+
* 56 F
255
+
* 55 L
256
+
* 54 P
257
+
* 53 SW
258
+
* 52 T
259
+
* 50:48 reserved
260
+
* 47:12 4k physical page base address
261
+
* 11:7 fragment
262
+
* 6 write
263
+
* 5 read
264
+
* 4 exe
265
+
* 3 Z
266
+
* 2 snooped
267
+
* 1 system
268
+
* 0 valid
269
+
*
270
+
* PDE format on VEGA 10:
271
+
* 63:59 block fragment size
272
+
* 58:55 reserved
273
+
* 54 P
274
+
* 53:48 reserved
275
+
* 47:6 physical base address of PD or PTE
276
+
* 5:3 reserved
277
+
* 2 C
278
+
* 1 system
279
+
* 0 valid
280
+
*/
281
+
282
+
/*
283
+
* The following is for PTE only. GART does not have PDEs.
284
+
*/
285
+
value = addr & 0x0000FFFFFFFFF000ULL;
286
+
value |= flags;
287
+
writeq(value, ptr + (gpu_page_idx * 8));
288
+
return 0;
289
+
}
290
+
291
+
static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
292
+
uint32_t flags)
293
+
294
+
{
295
+
uint64_t pte_flag = 0;
296
+
297
+
if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
298
+
pte_flag |= AMDGPU_PTE_EXECUTABLE;
299
+
if (flags & AMDGPU_VM_PAGE_READABLE)
300
+
pte_flag |= AMDGPU_PTE_READABLE;
301
+
if (flags & AMDGPU_VM_PAGE_WRITEABLE)
302
+
pte_flag |= AMDGPU_PTE_WRITEABLE;
303
+
304
+
switch (flags & AMDGPU_VM_MTYPE_MASK) {
305
+
case AMDGPU_VM_MTYPE_DEFAULT:
306
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
307
+
break;
308
+
case AMDGPU_VM_MTYPE_NC:
309
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
310
+
break;
311
+
case AMDGPU_VM_MTYPE_WC:
312
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
313
+
break;
314
+
case AMDGPU_VM_MTYPE_CC:
315
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
316
+
break;
317
+
case AMDGPU_VM_MTYPE_UC:
318
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
319
+
break;
320
+
default:
321
+
pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
322
+
break;
323
+
}
324
+
325
+
if (flags & AMDGPU_VM_PAGE_PRT)
326
+
pte_flag |= AMDGPU_PTE_PRT;
327
+
328
+
return pte_flag;
329
+
}
330
+
331
+
static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
332
+
.flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
333
+
.set_pte_pde = gmc_v9_0_gart_set_pte_pde,
334
+
.get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags
335
+
};
336
+
337
+
static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
338
+
{
339
+
if (adev->gart.gart_funcs == NULL)
340
+
adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
341
+
}
342
+
343
+
static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
344
+
{
345
+
return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start;
346
+
}
347
+
348
+
static const struct amdgpu_mc_funcs gmc_v9_0_mc_funcs = {
349
+
.adjust_mc_addr = gmc_v9_0_adjust_mc_addr,
350
+
};
351
+
352
+
static void gmc_v9_0_set_mc_funcs(struct amdgpu_device *adev)
353
+
{
354
+
adev->mc.mc_funcs = &gmc_v9_0_mc_funcs;
355
+
}
356
+
357
+
static int gmc_v9_0_early_init(void *handle)
358
+
{
359
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
360
+
361
+
gmc_v9_0_set_gart_funcs(adev);
362
+
gmc_v9_0_set_mc_funcs(adev);
363
+
gmc_v9_0_set_irq_funcs(adev);
364
+
365
+
return 0;
366
+
}
367
+
368
+
static int gmc_v9_0_late_init(void *handle)
369
+
{
370
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
371
+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
372
+
}
373
+
374
+
static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
375
+
struct amdgpu_mc *mc)
376
+
{
377
+
u64 base = mmhub_v1_0_get_fb_location(adev);
378
+
amdgpu_vram_location(adev, &adev->mc, base);
379
+
adev->mc.gtt_base_align = 0;
380
+
amdgpu_gtt_location(adev, mc);
381
+
}
382
+
383
+
/**
384
+
* gmc_v9_0_mc_init - initialize the memory controller driver params
385
+
*
386
+
* @adev: amdgpu_device pointer
387
+
*
388
+
* Look up the amount of vram, vram width, and decide how to place
389
+
* vram and gart within the GPU's physical address space.
390
+
* Returns 0 for success.
391
+
*/
392
+
static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
393
+
{
394
+
u32 tmp;
395
+
int chansize, numchan;
396
+
397
+
/* hbm memory channel size */
398
+
chansize = 128;
399
+
400
+
tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0));
401
+
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
402
+
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
403
+
switch (tmp) {
404
+
case 0:
405
+
default:
406
+
numchan = 1;
407
+
break;
408
+
case 1:
409
+
numchan = 2;
410
+
break;
411
+
case 2:
412
+
numchan = 0;
413
+
break;
414
+
case 3:
415
+
numchan = 4;
416
+
break;
417
+
case 4:
418
+
numchan = 0;
419
+
break;
420
+
case 5:
421
+
numchan = 8;
422
+
break;
423
+
case 6:
424
+
numchan = 0;
425
+
break;
426
+
case 7:
427
+
numchan = 16;
428
+
break;
429
+
case 8:
430
+
numchan = 2;
431
+
break;
432
+
}
433
+
adev->mc.vram_width = numchan * chansize;
434
+
435
+
/* Could aper size report 0 ? */
436
+
adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
437
+
adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
438
+
/* size in MB on si */
439
+
adev->mc.mc_vram_size =
440
+
nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL;
441
+
adev->mc.real_vram_size = adev->mc.mc_vram_size;
442
+
adev->mc.visible_vram_size = adev->mc.aper_size;
443
+
444
+
/* In case the PCI BAR is larger than the actual amount of vram */
445
+
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
446
+
adev->mc.visible_vram_size = adev->mc.real_vram_size;
447
+
448
+
/* unless the user had overridden it, set the gart
449
+
* size equal to the 1024 or vram, whichever is larger.
450
+
*/
451
+
if (amdgpu_gart_size == -1)
452
+
adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
453
+
else
454
+
adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
455
+
456
+
gmc_v9_0_vram_gtt_location(adev, &adev->mc);
457
+
458
+
return 0;
459
+
}
460
+
461
+
static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
462
+
{
463
+
int r;
464
+
465
+
if (adev->gart.robj) {
466
+
WARN(1, "VEGA10 PCIE GART already initialized\n");
467
+
return 0;
468
+
}
469
+
/* Initialize common gart structure */
470
+
r = amdgpu_gart_init(adev);
471
+
if (r)
472
+
return r;
473
+
adev->gart.table_size = adev->gart.num_gpu_pages * 8;
474
+
adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
475
+
AMDGPU_PTE_EXECUTABLE;
476
+
return amdgpu_gart_table_vram_alloc(adev);
477
+
}
478
+
479
+
/*
480
+
* vm
481
+
* VMID 0 is the physical GPU addresses as used by the kernel.
482
+
* VMIDs 1-15 are used for userspace clients and are handled
483
+
* by the amdgpu vm/hsa code.
484
+
*/
485
+
/**
486
+
* gmc_v9_0_vm_init - vm init callback
487
+
*
488
+
* @adev: amdgpu_device pointer
489
+
*
490
+
* Inits vega10 specific vm parameters (number of VMs, base of vram for
491
+
* VMIDs 1-15) (vega10).
492
+
* Returns 0 for success.
493
+
*/
494
+
static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
495
+
{
496
+
/*
497
+
* number of VMs
498
+
* VMID 0 is reserved for System
499
+
* amdgpu graphics/compute will use VMIDs 1-7
500
+
* amdkfd will use VMIDs 8-15
501
+
*/
502
+
adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
503
+
amdgpu_vm_manager_init(adev);
504
+
505
+
/* base offset of vram pages */
506
+
/*XXX This value is not zero for APU*/
507
+
adev->vm_manager.vram_base_offset = 0;
508
+
509
+
return 0;
510
+
}
511
+
512
+
/**
513
+
* gmc_v9_0_vm_fini - vm fini callback
514
+
*
515
+
* @adev: amdgpu_device pointer
516
+
*
517
+
* Tear down any asic specific VM setup.
518
+
*/
519
+
static void gmc_v9_0_vm_fini(struct amdgpu_device *adev)
520
+
{
521
+
return;
522
+
}
523
+
524
+
static int gmc_v9_0_sw_init(void *handle)
525
+
{
526
+
int r;
527
+
int dma_bits;
528
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
529
+
530
+
spin_lock_init(&adev->mc.invalidate_lock);
531
+
532
+
if (adev->flags & AMD_IS_APU) {
533
+
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
534
+
} else {
535
+
/* XXX Don't know how to get VRAM type yet. */
536
+
adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
537
+
}
538
+
539
+
/* This interrupt is VMC page fault.*/
540
+
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
541
+
&adev->mc.vm_fault);
542
+
543
+
if (r)
544
+
return r;
545
+
546
+
/* Adjust VM size here.
547
+
* Currently default to 64GB ((16 << 20) 4k pages).
548
+
* Max GPUVM size is 48 bits.
549
+
*/
550
+
adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
551
+
552
+
/* Set the internal MC address mask
553
+
* This is the max address of the GPU's
554
+
* internal address space.
555
+
*/
556
+
adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
557
+
558
+
/* set DMA mask + need_dma32 flags.
559
+
* PCIE - can handle 44-bits.
560
+
* IGP - can handle 44-bits
561
+
* PCI - dma32 for legacy pci gart, 44 bits on vega10
562
+
*/
563
+
adev->need_dma32 = false;
564
+
dma_bits = adev->need_dma32 ? 32 : 44;
565
+
r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
566
+
if (r) {
567
+
adev->need_dma32 = true;
568
+
dma_bits = 32;
569
+
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
570
+
}
571
+
r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
572
+
if (r) {
573
+
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
574
+
printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
575
+
}
576
+
577
+
r = gmc_v9_0_mc_init(adev);
578
+
if (r)
579
+
return r;
580
+
581
+
/* Memory manager */
582
+
r = amdgpu_bo_init(adev);
583
+
if (r)
584
+
return r;
585
+
586
+
r = gmc_v9_0_gart_init(adev);
587
+
if (r)
588
+
return r;
589
+
590
+
if (!adev->vm_manager.enabled) {
591
+
r = gmc_v9_0_vm_init(adev);
592
+
if (r) {
593
+
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
594
+
return r;
595
+
}
596
+
adev->vm_manager.enabled = true;
597
+
}
598
+
return r;
599
+
}
600
+
601
+
/**
602
+
* gmc_v8_0_gart_fini - vm fini callback
603
+
*
604
+
* @adev: amdgpu_device pointer
605
+
*
606
+
* Tears down the driver GART/VM setup (CIK).
607
+
*/
608
+
static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
609
+
{
610
+
amdgpu_gart_table_vram_free(adev);
611
+
amdgpu_gart_fini(adev);
612
+
}
613
+
614
+
static int gmc_v9_0_sw_fini(void *handle)
615
+
{
616
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
617
+
618
+
if (adev->vm_manager.enabled) {
619
+
amdgpu_vm_manager_fini(adev);
620
+
gmc_v9_0_vm_fini(adev);
621
+
adev->vm_manager.enabled = false;
622
+
}
623
+
gmc_v9_0_gart_fini(adev);
624
+
amdgpu_gem_force_release(adev);
625
+
amdgpu_bo_fini(adev);
626
+
627
+
return 0;
628
+
}
629
+
630
+
static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
631
+
{
632
+
switch (adev->asic_type) {
633
+
case CHIP_VEGA10:
634
+
break;
635
+
default:
636
+
break;
637
+
}
638
+
}
639
+
640
+
/**
641
+
* gmc_v9_0_gart_enable - gart enable
642
+
*
643
+
* @adev: amdgpu_device pointer
644
+
*/
645
+
static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
646
+
{
647
+
int r;
648
+
bool value;
649
+
u32 tmp;
650
+
651
+
amdgpu_program_register_sequence(adev,
652
+
golden_settings_vega10_hdp,
653
+
(const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
654
+
655
+
if (adev->gart.robj == NULL) {
656
+
dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
657
+
return -EINVAL;
658
+
}
659
+
r = amdgpu_gart_table_vram_pin(adev);
660
+
if (r)
661
+
return r;
662
+
663
+
/* After HDP is initialized, flush HDP.*/
664
+
nbio_v6_1_hdp_flush(adev);
665
+
666
+
r = gfxhub_v1_0_gart_enable(adev);
667
+
if (r)
668
+
return r;
669
+
670
+
r = mmhub_v1_0_gart_enable(adev);
671
+
if (r)
672
+
return r;
673
+
674
+
tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL));
675
+
tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
676
+
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp);
677
+
678
+
tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL));
679
+
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp);
680
+
681
+
682
+
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
683
+
value = false;
684
+
else
685
+
value = true;
686
+
687
+
gfxhub_v1_0_set_fault_enable_default(adev, value);
688
+
mmhub_v1_0_set_fault_enable_default(adev, value);
689
+
690
+
gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
691
+
692
+
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
693
+
(unsigned)(adev->mc.gtt_size >> 20),
694
+
(unsigned long long)adev->gart.table_addr);
695
+
adev->gart.ready = true;
696
+
return 0;
697
+
}
698
+
699
+
static int gmc_v9_0_hw_init(void *handle)
700
+
{
701
+
int r;
702
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
703
+
704
+
/* The sequence of these two function calls matters.*/
705
+
gmc_v9_0_init_golden_registers(adev);
706
+
707
+
r = gmc_v9_0_gart_enable(adev);
708
+
709
+
return r;
710
+
}
711
+
712
+
/**
713
+
* gmc_v9_0_gart_disable - gart disable
714
+
*
715
+
* @adev: amdgpu_device pointer
716
+
*
717
+
* This disables all VM page table.
718
+
*/
719
+
static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
720
+
{
721
+
gfxhub_v1_0_gart_disable(adev);
722
+
mmhub_v1_0_gart_disable(adev);
723
+
amdgpu_gart_table_vram_unpin(adev);
724
+
}
725
+
726
+
static int gmc_v9_0_hw_fini(void *handle)
727
+
{
728
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
729
+
730
+
amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
731
+
gmc_v9_0_gart_disable(adev);
732
+
733
+
return 0;
734
+
}
735
+
736
+
static int gmc_v9_0_suspend(void *handle)
737
+
{
738
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
739
+
740
+
if (adev->vm_manager.enabled) {
741
+
gmc_v9_0_vm_fini(adev);
742
+
adev->vm_manager.enabled = false;
743
+
}
744
+
gmc_v9_0_hw_fini(adev);
745
+
746
+
return 0;
747
+
}
748
+
749
+
static int gmc_v9_0_resume(void *handle)
750
+
{
751
+
int r;
752
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
753
+
754
+
r = gmc_v9_0_hw_init(adev);
755
+
if (r)
756
+
return r;
757
+
758
+
if (!adev->vm_manager.enabled) {
759
+
r = gmc_v9_0_vm_init(adev);
760
+
if (r) {
761
+
dev_err(adev->dev,
762
+
"vm manager initialization failed (%d).\n", r);
763
+
return r;
764
+
}
765
+
adev->vm_manager.enabled = true;
766
+
}
767
+
768
+
return r;
769
+
}
770
+
771
+
static bool gmc_v9_0_is_idle(void *handle)
772
+
{
773
+
/* MC is always ready in GMC v9.*/
774
+
return true;
775
+
}
776
+
777
+
static int gmc_v9_0_wait_for_idle(void *handle)
778
+
{
779
+
/* There is no need to wait for MC idle in GMC v9.*/
780
+
return 0;
781
+
}
782
+
783
+
static int gmc_v9_0_soft_reset(void *handle)
784
+
{
785
+
/* XXX for emulation.*/
786
+
return 0;
787
+
}
788
+
789
+
static int gmc_v9_0_set_clockgating_state(void *handle,
790
+
enum amd_clockgating_state state)
791
+
{
792
+
return 0;
793
+
}
794
+
795
+
static int gmc_v9_0_set_powergating_state(void *handle,
796
+
enum amd_powergating_state state)
797
+
{
798
+
return 0;
799
+
}
800
+
801
+
const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
802
+
.name = "gmc_v9_0",
803
+
.early_init = gmc_v9_0_early_init,
804
+
.late_init = gmc_v9_0_late_init,
805
+
.sw_init = gmc_v9_0_sw_init,
806
+
.sw_fini = gmc_v9_0_sw_fini,
807
+
.hw_init = gmc_v9_0_hw_init,
808
+
.hw_fini = gmc_v9_0_hw_fini,
809
+
.suspend = gmc_v9_0_suspend,
810
+
.resume = gmc_v9_0_resume,
811
+
.is_idle = gmc_v9_0_is_idle,
812
+
.wait_for_idle = gmc_v9_0_wait_for_idle,
813
+
.soft_reset = gmc_v9_0_soft_reset,
814
+
.set_clockgating_state = gmc_v9_0_set_clockgating_state,
815
+
.set_powergating_state = gmc_v9_0_set_powergating_state,
816
+
};
817
+
818
+
const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
819
+
{
820
+
.type = AMD_IP_BLOCK_TYPE_GMC,
821
+
.major = 9,
822
+
.minor = 0,
823
+
.rev = 0,
824
+
.funcs = &gmc_v9_0_ip_funcs,
825
+
};
+30
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+30
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#ifndef __GMC_V9_0_H__
25
+
#define __GMC_V9_0_H__
26
+
27
+
extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
28
+
extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
29
+
30
+
#endif
+585
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+585
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#include "amdgpu.h"
24
+
#include "mmhub_v1_0.h"
25
+
26
+
#include "vega10/soc15ip.h"
27
+
#include "vega10/MMHUB/mmhub_1_0_offset.h"
28
+
#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
29
+
#include "vega10/MMHUB/mmhub_1_0_default.h"
30
+
#include "vega10/ATHUB/athub_1_0_offset.h"
31
+
#include "vega10/ATHUB/athub_1_0_sh_mask.h"
32
+
#include "vega10/ATHUB/athub_1_0_default.h"
33
+
#include "vega10/vega10_enum.h"
34
+
35
+
#include "soc15_common.h"
36
+
37
+
u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
38
+
{
39
+
u64 base = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE));
40
+
41
+
base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
42
+
base <<= 24;
43
+
44
+
return base;
45
+
}
46
+
47
+
int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
48
+
{
49
+
u32 tmp;
50
+
u64 value;
51
+
uint64_t addr;
52
+
u32 i;
53
+
54
+
/* Program MC. */
55
+
/* Update configuration */
56
+
DRM_INFO("%s -- in\n", __func__);
57
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
58
+
adev->mc.vram_start >> 18);
59
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
60
+
adev->mc.vram_end >> 18);
61
+
value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +
62
+
adev->vm_manager.vram_base_offset;
63
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
64
+
mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
65
+
(u32)(value >> 12));
66
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
67
+
mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
68
+
(u32)(value >> 44));
69
+
70
+
/* Disable AGP. */
71
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);
72
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);
73
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF);
74
+
75
+
/* GART Enable. */
76
+
77
+
/* Setup TLB control */
78
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
79
+
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
80
+
tmp = REG_SET_FIELD(tmp,
81
+
MC_VM_MX_L1_TLB_CNTL,
82
+
SYSTEM_ACCESS_MODE,
83
+
3);
84
+
tmp = REG_SET_FIELD(tmp,
85
+
MC_VM_MX_L1_TLB_CNTL,
86
+
ENABLE_ADVANCED_DRIVER_MODEL,
87
+
1);
88
+
tmp = REG_SET_FIELD(tmp,
89
+
MC_VM_MX_L1_TLB_CNTL,
90
+
SYSTEM_APERTURE_UNMAPPED_ACCESS,
91
+
0);
92
+
tmp = REG_SET_FIELD(tmp,
93
+
MC_VM_MX_L1_TLB_CNTL,
94
+
ECO_BITS,
95
+
0);
96
+
tmp = REG_SET_FIELD(tmp,
97
+
MC_VM_MX_L1_TLB_CNTL,
98
+
MTYPE,
99
+
MTYPE_UC);/* XXX for emulation. */
100
+
tmp = REG_SET_FIELD(tmp,
101
+
MC_VM_MX_L1_TLB_CNTL,
102
+
ATC_EN,
103
+
1);
104
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
105
+
106
+
/* Setup L2 cache */
107
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));
108
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
109
+
tmp = REG_SET_FIELD(tmp,
110
+
VM_L2_CNTL,
111
+
ENABLE_L2_FRAGMENT_PROCESSING,
112
+
0);
113
+
tmp = REG_SET_FIELD(tmp,
114
+
VM_L2_CNTL,
115
+
L2_PDE0_CACHE_TAG_GENERATION_MODE,
116
+
0);/* XXX for emulation, Refer to closed source code.*/
117
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
118
+
tmp = REG_SET_FIELD(tmp,
119
+
VM_L2_CNTL,
120
+
CONTEXT1_IDENTITY_ACCESS_MODE,
121
+
1);
122
+
tmp = REG_SET_FIELD(tmp,
123
+
VM_L2_CNTL,
124
+
IDENTITY_MODE_FRAGMENT_SIZE,
125
+
0);
126
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);
127
+
128
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));
129
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
130
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
131
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);
132
+
133
+
tmp = mmVM_L2_CNTL3_DEFAULT;
134
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);
135
+
136
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4));
137
+
tmp = REG_SET_FIELD(tmp,
138
+
VM_L2_CNTL4,
139
+
VMC_TAP_PDE_REQUEST_PHYSICAL,
140
+
0);
141
+
tmp = REG_SET_FIELD(tmp,
142
+
VM_L2_CNTL4,
143
+
VMC_TAP_PTE_REQUEST_PHYSICAL,
144
+
0);
145
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
146
+
147
+
/* setup context0 */
148
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
149
+
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
150
+
(u32)(adev->mc.gtt_start >> 12));
151
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
152
+
mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
153
+
(u32)(adev->mc.gtt_start >> 44));
154
+
155
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
156
+
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
157
+
(u32)(adev->mc.gtt_end >> 12));
158
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
159
+
mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
160
+
(u32)(adev->mc.gtt_end >> 44));
161
+
162
+
BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
163
+
value = adev->gart.table_addr - adev->mc.vram_start +
164
+
adev->vm_manager.vram_base_offset;
165
+
value &= 0x0000FFFFFFFFF000ULL;
166
+
value |= 0x1; /* valid bit */
167
+
168
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
169
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
170
+
(u32)value);
171
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
172
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
173
+
(u32)(value >> 32));
174
+
175
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
176
+
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
177
+
(u32)(adev->dummy_page.addr >> 12));
178
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
179
+
mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
180
+
(u32)(adev->dummy_page.addr >> 44));
181
+
182
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
183
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
184
+
ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,
185
+
1);
186
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
187
+
188
+
addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
189
+
tmp = RREG32(addr);
190
+
191
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
192
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
193
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
194
+
195
+
tmp = RREG32(addr);
196
+
197
+
/* Disable identity aperture.*/
198
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
199
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
200
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
201
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
202
+
203
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
204
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
205
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
206
+
mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
207
+
208
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
209
+
mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
210
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
211
+
mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
212
+
213
+
for (i = 0; i <= 14; i++) {
214
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
215
+
+ i);
216
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
217
+
ENABLE_CONTEXT, 1);
218
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
219
+
PAGE_TABLE_DEPTH, 1);
220
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
221
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
222
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
223
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
224
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
225
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
226
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
227
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
228
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
229
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
230
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
231
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
232
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
233
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
234
+
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
235
+
PAGE_TABLE_BLOCK_SIZE,
236
+
amdgpu_vm_block_size - 9);
237
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
238
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
239
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
240
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
241
+
adev->vm_manager.max_pfn - 1);
242
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
243
+
}
244
+
245
+
return 0;
246
+
}
247
+
248
+
void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
249
+
{
250
+
u32 tmp;
251
+
u32 i;
252
+
253
+
/* Disable all tables */
254
+
for (i = 0; i < 16; i++)
255
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0);
256
+
257
+
/* Setup TLB control */
258
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
259
+
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
260
+
tmp = REG_SET_FIELD(tmp,
261
+
MC_VM_MX_L1_TLB_CNTL,
262
+
ENABLE_ADVANCED_DRIVER_MODEL,
263
+
0);
264
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
265
+
266
+
/* Setup L2 cache */
267
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));
268
+
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
269
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);
270
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), 0);
271
+
}
272
+
273
+
/**
274
+
* mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
275
+
*
276
+
* @adev: amdgpu_device pointer
277
+
* @value: true redirects VM faults to the default page
278
+
*/
279
+
void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
280
+
{
281
+
u32 tmp;
282
+
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
283
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
284
+
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
285
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
286
+
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
287
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
288
+
PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
289
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
290
+
PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
291
+
tmp = REG_SET_FIELD(tmp,
292
+
VM_L2_PROTECTION_FAULT_CNTL,
293
+
TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
294
+
value);
295
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
296
+
NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
297
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
298
+
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
299
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
300
+
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
301
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
302
+
READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
303
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
304
+
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
305
+
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
306
+
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
307
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
308
+
}
309
+
310
+
static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vm_id)
311
+
{
312
+
u32 req = 0;
313
+
314
+
/* invalidate using legacy mode on vm_id*/
315
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
316
+
PER_VMID_INVALIDATE_REQ, 1 << vm_id);
317
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
318
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
319
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
320
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
321
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
322
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
323
+
req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
324
+
CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
325
+
326
+
return req;
327
+
}
328
+
329
+
static uint32_t mmhub_v1_0_get_vm_protection_bits(void)
330
+
{
331
+
return (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
332
+
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
333
+
VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
334
+
VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
335
+
VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
336
+
VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
337
+
VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
338
+
}
339
+
340
+
static int mmhub_v1_0_early_init(void *handle)
341
+
{
342
+
return 0;
343
+
}
344
+
345
+
static int mmhub_v1_0_late_init(void *handle)
346
+
{
347
+
return 0;
348
+
}
349
+
350
+
static int mmhub_v1_0_sw_init(void *handle)
351
+
{
352
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353
+
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
354
+
355
+
hub->ctx0_ptb_addr_lo32 =
356
+
SOC15_REG_OFFSET(MMHUB, 0,
357
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
358
+
hub->ctx0_ptb_addr_hi32 =
359
+
SOC15_REG_OFFSET(MMHUB, 0,
360
+
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
361
+
hub->vm_inv_eng0_req =
362
+
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
363
+
hub->vm_inv_eng0_ack =
364
+
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
365
+
hub->vm_context0_cntl =
366
+
SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
367
+
hub->vm_l2_pro_fault_status =
368
+
SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
369
+
hub->vm_l2_pro_fault_cntl =
370
+
SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
371
+
372
+
hub->get_invalidate_req = mmhub_v1_0_get_invalidate_req;
373
+
hub->get_vm_protection_bits = mmhub_v1_0_get_vm_protection_bits;
374
+
375
+
return 0;
376
+
}
377
+
378
+
static int mmhub_v1_0_sw_fini(void *handle)
379
+
{
380
+
return 0;
381
+
}
382
+
383
+
static int mmhub_v1_0_hw_init(void *handle)
384
+
{
385
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
386
+
unsigned i;
387
+
388
+
for (i = 0; i < 18; ++i) {
389
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
390
+
mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
391
+
2 * i, 0xffffffff);
392
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0,
393
+
mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
394
+
2 * i, 0x1f);
395
+
}
396
+
397
+
return 0;
398
+
}
399
+
400
+
static int mmhub_v1_0_hw_fini(void *handle)
401
+
{
402
+
return 0;
403
+
}
404
+
405
+
static int mmhub_v1_0_suspend(void *handle)
406
+
{
407
+
return 0;
408
+
}
409
+
410
+
static int mmhub_v1_0_resume(void *handle)
411
+
{
412
+
return 0;
413
+
}
414
+
415
+
static bool mmhub_v1_0_is_idle(void *handle)
416
+
{
417
+
return true;
418
+
}
419
+
420
+
static int mmhub_v1_0_wait_for_idle(void *handle)
421
+
{
422
+
return 0;
423
+
}
424
+
425
+
static int mmhub_v1_0_soft_reset(void *handle)
426
+
{
427
+
return 0;
428
+
}
429
+
430
+
static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
431
+
bool enable)
432
+
{
433
+
uint32_t def, data, def1, data1, def2, data2;
434
+
435
+
def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));
436
+
def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2));
437
+
def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2));
438
+
439
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
440
+
data |= ATC_L2_MISC_CG__ENABLE_MASK;
441
+
442
+
data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
443
+
DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
444
+
DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
445
+
DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
446
+
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
447
+
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
448
+
449
+
data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
450
+
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
451
+
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
452
+
DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
453
+
DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
454
+
DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
455
+
} else {
456
+
data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
457
+
458
+
data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
459
+
DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
460
+
DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
461
+
DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
462
+
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
463
+
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
464
+
465
+
data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
466
+
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
467
+
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
468
+
DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
469
+
DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
470
+
DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
471
+
}
472
+
473
+
if (def != data)
474
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data);
475
+
476
+
if (def1 != data1)
477
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1);
478
+
479
+
if (def2 != data2)
480
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2), data2);
481
+
}
482
+
483
+
static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
484
+
bool enable)
485
+
{
486
+
uint32_t def, data;
487
+
488
+
def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));
489
+
490
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
491
+
data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
492
+
else
493
+
data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
494
+
495
+
if (def != data)
496
+
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);
497
+
}
498
+
499
+
static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
500
+
bool enable)
501
+
{
502
+
uint32_t def, data;
503
+
504
+
def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));
505
+
506
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
507
+
data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
508
+
else
509
+
data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
510
+
511
+
if (def != data)
512
+
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data);
513
+
}
514
+
515
+
static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
516
+
bool enable)
517
+
{
518
+
uint32_t def, data;
519
+
520
+
def = data = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL));
521
+
522
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
523
+
(adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
524
+
data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
525
+
else
526
+
data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
527
+
528
+
if(def != data)
529
+
WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);
530
+
}
531
+
532
+
static int mmhub_v1_0_set_clockgating_state(void *handle,
533
+
enum amd_clockgating_state state)
534
+
{
535
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
536
+
537
+
switch (adev->asic_type) {
538
+
case CHIP_VEGA10:
539
+
mmhub_v1_0_update_medium_grain_clock_gating(adev,
540
+
state == AMD_CG_STATE_GATE ? true : false);
541
+
athub_update_medium_grain_clock_gating(adev,
542
+
state == AMD_CG_STATE_GATE ? true : false);
543
+
mmhub_v1_0_update_medium_grain_light_sleep(adev,
544
+
state == AMD_CG_STATE_GATE ? true : false);
545
+
athub_update_medium_grain_light_sleep(adev,
546
+
state == AMD_CG_STATE_GATE ? true : false);
547
+
break;
548
+
default:
549
+
break;
550
+
}
551
+
552
+
return 0;
553
+
}
554
+
555
+
static int mmhub_v1_0_set_powergating_state(void *handle,
556
+
enum amd_powergating_state state)
557
+
{
558
+
return 0;
559
+
}
560
+
561
+
const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
562
+
.name = "mmhub_v1_0",
563
+
.early_init = mmhub_v1_0_early_init,
564
+
.late_init = mmhub_v1_0_late_init,
565
+
.sw_init = mmhub_v1_0_sw_init,
566
+
.sw_fini = mmhub_v1_0_sw_fini,
567
+
.hw_init = mmhub_v1_0_hw_init,
568
+
.hw_fini = mmhub_v1_0_hw_fini,
569
+
.suspend = mmhub_v1_0_suspend,
570
+
.resume = mmhub_v1_0_resume,
571
+
.is_idle = mmhub_v1_0_is_idle,
572
+
.wait_for_idle = mmhub_v1_0_wait_for_idle,
573
+
.soft_reset = mmhub_v1_0_soft_reset,
574
+
.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
575
+
.set_powergating_state = mmhub_v1_0_set_powergating_state,
576
+
};
577
+
578
+
const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
579
+
{
580
+
.type = AMD_IP_BLOCK_TYPE_MMHUB,
581
+
.major = 1,
582
+
.minor = 0,
583
+
.rev = 0,
584
+
.funcs = &mmhub_v1_0_ip_funcs,
585
+
};
+35
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+35
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __MMHUB_V1_0_H__
24
+
#define __MMHUB_V1_0_H__
25
+
26
+
u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);
27
+
int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
28
+
void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
29
+
void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
30
+
bool value);
31
+
32
+
extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
33
+
extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
34
+
35
+
#endif