Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Fixing hubp programming of 3dlut fast load
[why]
HUBP needs to know the size of the lut's destination in MPC.
This is currently defaulted to 17, and needs to be set for specific
lut size.
[how]
Define and apply the missing hubp field. Taking this opportunity
to consolidate the programming of 3dlut into a hubp and mpc function.
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com>
Signed-off-by: Reza Amini <reza.amini@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Reza Amini
and committed by
Alex Deucher
e63e9f8b
3df95751
+148
-15
+26
drivers/gpu/drm/amd/display/dc/dc.h
+26
drivers/gpu/drm/amd/display/dc/dc.h
···
1311
1311
};
1312
1312
1313
1313
1314
+
#define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0
1315
+
#define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0
1316
+
#define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0
1317
+
1318
+
struct lut_rgb {
1319
+
uint16_t b;
1320
+
uint16_t g;
1321
+
uint16_t r;
1322
+
uint16_t padding;
1323
+
};
1324
+
1325
+
//this structure maps directly to how the lut will read it from memory
1326
+
struct lut_mem_mapping {
1327
+
union {
1328
+
//NATIVE MODE 1, 2
1329
+
//RGB layout [b][g][r] //red is 128 byte aligned
1330
+
//BGR layout [r][g][b] //blue is 128 byte aligned
1331
+
struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN];
1332
+
struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN];
1333
+
1334
+
//TRANSFORMED
1335
+
uint16_t linear_rgb[(33*33*33*4/128+1)*128];
1336
+
};
1337
+
uint16_t size;
1338
+
};
1339
+
1314
1340
struct dc_rmcm_3dlut {
1315
1341
bool isInUse;
1316
1342
const struct dc_stream_state *stream;
+1
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
+1
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h
+1
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+1
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h
+38
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+38
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
···
127
127
REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format);
128
128
}
129
129
130
+
void hubp401_program_3dlut_fl_config(
131
+
struct hubp *hubp,
132
+
struct hubp_fl_3dlut_config *cfg)
133
+
{
134
+
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
135
+
136
+
uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1};
137
+
uint32_t width = {cfg->width};
138
+
139
+
if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR)
140
+
width = (cfg->width == 17) ? 4916 : 35940;
141
+
142
+
REG_UPDATE_2(_3DLUT_FL_CONFIG,
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+
HUBP0_3DLUT_FL_MODE, cfg->mode,
144
+
HUBP0_3DLUT_FL_FORMAT, cfg->format);
145
+
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+
REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE,
147
+
HUBP0_3DLUT_FL_BIAS, cfg->bias,
148
+
HUBP0_3DLUT_FL_SCALE, cfg->scale);
149
+
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+
REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH,
151
+
HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part);
152
+
REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW,
153
+
HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part);
154
+
155
+
//cross bar
156
+
REG_UPDATE_8(HUBP_3DLUT_CONTROL,
157
+
HUBP_3DLUT_MPC_WIDTH, mpc_width,
158
+
HUBP_3DLUT_WIDTH, width,
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+
HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r,
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+
HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g,
161
+
HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b,
162
+
HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode,
163
+
HUBP_3DLUT_TMZ, cfg->protection_bits,
164
+
HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0);
165
+
}
166
+
130
167
void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)
131
168
{
132
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struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
···
1070
1033
.hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,
1071
1034
.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,
1072
1035
.hubp_clear_tiling = hubp401_clear_tiling,
1036
+
.hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,
1073
1037
};
1074
1038
1075
1039
bool hubp401_construct(
+4
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
+4
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h
···
349
349
350
350
void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);
351
351
352
+
void hubp401_program_3dlut_fl_config(
353
+
struct hubp *hubp,
354
+
struct hubp_fl_3dlut_config *cfg);
355
+
352
356
void hubp401_clear_tiling(struct hubp *hubp);
353
357
354
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void hubp401_vready_at_or_After_vsync(struct hubp *hubp,
+49
-14
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+49
-14
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
···
328
328
}
329
329
330
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DTN_INFO("\n=======HUBP FL======\n");
331
-
DTN_INFO(
332
-
"HUBP FL: Enabled Done adr_mode width tmz xbar_sel_R xbar_sel_G xbar_sel_B adr_hi adr_low REFCYC Bias Scale Mode Format\n");
331
+
char pLabels[18][50] = {
332
+
"inst", "Enabled ", "Done ", "adr_mode ", "width ", "mpc_width ",
333
+
"tmz", "xbar_sel_R", "xbar_sel_G", "xbar_sel_B", "adr_hi ",
334
+
"adr_low", "REFCYC", "Bias", "Scale", "Mode",
335
+
"Format", "prefetch"};
336
+
333
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for (i = 0; i < pool->pipe_count; i++) {
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struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
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struct dcn_fl_regs_st *fl_regs = &s->fl_regs;
340
+
struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
336
341
337
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if (!s->blank_en) {
338
-
DTN_INFO("[%2d]: %5xh %6xh %5d %6d %8xh %2xh %6xh %6d %8d %8d %7d %8xh %5x %5x %5x",
343
+
uint32_t values[] = {
339
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pool->hubps[i]->inst,
340
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fl_regs->lut_enable,
341
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fl_regs->lut_done,
342
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fl_regs->lut_addr_mode,
343
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fl_regs->lut_width,
349
+
fl_regs->lut_mpc_width,
344
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fl_regs->lut_tmz,
345
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fl_regs->lut_crossbar_sel_r,
346
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fl_regs->lut_crossbar_sel_g,
···
357
351
fl_regs->lut_fl_bias,
358
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fl_regs->lut_fl_scale,
359
353
fl_regs->lut_fl_mode,
360
-
fl_regs->lut_fl_format);
361
-
DTN_INFO("\n");
354
+
fl_regs->lut_fl_format,
355
+
dlg_regs->dst_y_prefetch};
356
+
357
+
int num_elements = 18;
358
+
359
+
for (int j = 0; j < num_elements; j++)
360
+
DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]);
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}
363
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}
364
363
···
552
541
dc->caps.color.mpc.ogam_ram,
553
542
dc->caps.color.mpc.ocsc);
554
543
DTN_INFO("===== MPC RMCM 3DLUT =====\n");
555
-
DTN_INFO("MPCC: SIZE MODE MODE_CUR RD_SEL 30BIT_EN WR_EN_MASK RAM_SEL OUT_NORM_FACTOR FL_SEL OUT_OFFSET OUT_SCALE FL_DONE SOFT_UNDERFLOW HARD_UNDERFLOW MEM_PWR_ST FORCE DIS MODE\n");
544
+
char pLabels[19][50] = {
545
+
"MPCC", "SIZE", "MODE", "MODE_CUR", "RD_SEL",
546
+
"30BIT_EN", "WR_EN_MASK", "RAM_SEL", "OUT_NORM_FACTOR", "FL_SEL",
547
+
"OUT_OFFSET", "OUT_SCALE", "FL_DONE", "SOFT_UNDERFLOW", "HARD_UNDERFLOW",
548
+
"MEM_PWR_ST", "FORCE", "DIS", "MODE"};
549
+
556
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for (i = 0; i < pool->mpcc_count; i++) {
557
551
struct mpcc_state s = {0};
558
552
559
553
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
560
-
if (s.opp_id != 0xf)
561
-
DTN_INFO("[%2d]: %4xh %4xh %6xh %4x %4x %4x %4x %4x %4xh %4xh %6xh %4x %4x %4x %4x %4x %4x %4x\n",
562
-
i, s.rmcm_regs.rmcm_3dlut_size, s.rmcm_regs.rmcm_3dlut_mode, s.rmcm_regs.rmcm_3dlut_mode_cur,
563
-
s.rmcm_regs.rmcm_3dlut_read_sel, s.rmcm_regs.rmcm_3dlut_30bit_en, s.rmcm_regs.rmcm_3dlut_wr_en_mask,
564
-
s.rmcm_regs.rmcm_3dlut_ram_sel, s.rmcm_regs.rmcm_3dlut_out_norm_factor, s.rmcm_regs.rmcm_3dlut_fl_sel,
565
-
s.rmcm_regs.rmcm_3dlut_out_offset_r, s.rmcm_regs.rmcm_3dlut_out_scale_r, s.rmcm_regs.rmcm_3dlut_fl_done,
566
-
s.rmcm_regs.rmcm_3dlut_fl_soft_underflow, s.rmcm_regs.rmcm_3dlut_fl_hard_underflow, s.rmcm_regs.rmcm_3dlut_mem_pwr_state,
567
-
s.rmcm_regs.rmcm_3dlut_mem_pwr_force, s.rmcm_regs.rmcm_3dlut_mem_pwr_dis, s.rmcm_regs.rmcm_3dlut_mem_pwr_mode);
554
+
if (s.opp_id != 0xf) {
555
+
uint32_t values[] = {
556
+
i,
557
+
s.rmcm_regs.rmcm_3dlut_size,
558
+
s.rmcm_regs.rmcm_3dlut_mode,
559
+
s.rmcm_regs.rmcm_3dlut_mode_cur,
560
+
s.rmcm_regs.rmcm_3dlut_read_sel,
561
+
s.rmcm_regs.rmcm_3dlut_30bit_en,
562
+
s.rmcm_regs.rmcm_3dlut_wr_en_mask,
563
+
s.rmcm_regs.rmcm_3dlut_ram_sel,
564
+
s.rmcm_regs.rmcm_3dlut_out_norm_factor,
565
+
s.rmcm_regs.rmcm_3dlut_fl_sel,
566
+
s.rmcm_regs.rmcm_3dlut_out_offset_r,
567
+
s.rmcm_regs.rmcm_3dlut_out_scale_r,
568
+
s.rmcm_regs.rmcm_3dlut_fl_done,
569
+
s.rmcm_regs.rmcm_3dlut_fl_soft_underflow,
570
+
s.rmcm_regs.rmcm_3dlut_fl_hard_underflow,
571
+
s.rmcm_regs.rmcm_3dlut_mem_pwr_state,
572
+
s.rmcm_regs.rmcm_3dlut_mem_pwr_force,
573
+
s.rmcm_regs.rmcm_3dlut_mem_pwr_dis,
574
+
s.rmcm_regs.rmcm_3dlut_mem_pwr_mode};
575
+
576
+
int num_elements = 19;
577
+
578
+
for (int j = 0; j < num_elements; j++)
579
+
DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]);
580
+
}
568
581
}
569
582
DTN_INFO("\n");
570
583
DTN_INFO("===== MPC RMCM Shaper =====\n");
+18
-1
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+18
-1
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
···
89
89
enum hubp_3dlut_fl_width {
90
90
hubp_3dlut_fl_width_17 = 17,
91
91
hubp_3dlut_fl_width_33 = 33,
92
-
hubp_3dlut_fl_width_transformed = 4916
92
+
hubp_3dlut_fl_width_transformed = 4916, //mpc default
93
93
};
94
94
95
95
enum hubp_3dlut_fl_crossbar_bit_slice {
···
97
97
hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1,
98
98
hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2,
99
99
hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3
100
+
};
101
+
102
+
struct hubp_fl_3dlut_config {
103
+
bool enabled;
104
+
enum hubp_3dlut_fl_width width;
105
+
enum hubp_3dlut_fl_mode mode;
106
+
enum hubp_3dlut_fl_format format;
107
+
uint16_t bias;
108
+
uint16_t scale;
109
+
struct dc_plane_address address;
110
+
enum hubp_3dlut_fl_addressing_mode addr_mode;
111
+
enum dc_cm2_gpu_mem_layout layout;
112
+
uint8_t protection_bits;
113
+
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g;
114
+
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b;
115
+
enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r;
100
116
};
101
117
102
118
struct hubp {
···
304
288
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
305
289
enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
306
290
int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
291
+
void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
307
292
void (*hubp_clear_tiling)(struct hubp *hubp);
308
293
};
309
294
+11
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+11
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
···
115
115
MCM_LUT_SHAPER
116
116
};
117
117
118
+
struct mpc_fl_3dlut_config {
119
+
bool enabled;
120
+
uint16_t width;
121
+
bool select_lut_bank_a;
122
+
uint16_t bit_depth;
123
+
int hubp_index;
124
+
uint16_t bias;
125
+
uint16_t scale;
126
+
};
127
+
118
128
union mcm_lut_params {
119
129
const struct pwl_params *pwl;
120
130
const struct tetrahedral_params *lut3d;
···
1108
1098
* MPC RMCM new HW sequential programming functions
1109
1099
*/
1110
1100
struct {
1101
+
void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id);
1111
1102
void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id);
1112
1103
void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx);
1113
1104
void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id,