Merge tag 'i2c-for-6.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+2 -2

Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml

··· 16 16 compatible: 17 17 items: 18 18 - enum: 19 - - renesas,i2c-r9a09g011 # RZ/V2M 19 + - renesas,r9a09g011-i2c # RZ/V2M 20 20 - const: renesas,rzv2m-i2c 21 21 22 22 reg: ··· 66 66 #include <dt-bindings/interrupt-controller/arm-gic.h> 67 67 68 68 i2c0: i2c@a4030000 { 69 - compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; 69 + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; 70 70 reg = <0xa4030000 0x80>; 71 71 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 72 72 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;

+1 -1

drivers/i2c/busses/i2c-axxia.c

··· 118 118 #define SDA_HOLD_TIME 0x90 119 119 120 120 /** 121 - * axxia_i2c_dev - I2C device context 121 + * struct axxia_i2c_dev - I2C device context 122 122 * @base: pointer to register struct 123 123 * @msg: pointer to current message 124 124 * @msg_r: pointer to current read message (sequence transfer)

+6 -3

drivers/i2c/busses/i2c-designware-common.c

··· 351 351 * 352 352 * If your hardware is free from tHD;STA issue, try this one. 353 353 */ 354 - return DIV_ROUND_CLOSEST(ic_clk * tSYMBOL, MICRO) - 8 + offset; 354 + return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) - 355 + 8 + offset; 355 356 else 356 357 /* 357 358 * Conditional expression: ··· 368 367 * The reason why we need to take into account "tf" here, 369 368 * is the same as described in i2c_dw_scl_lcnt(). 370 369 */ 371 - return DIV_ROUND_CLOSEST(ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset; 370 + return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 371 + 3 + offset; 372 372 } 373 373 374 374 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) ··· 385 383 * account the fall time of SCL signal (tf). Default tf value 386 384 * should be 0.3 us, for safety. 387 385 */ 388 - return DIV_ROUND_CLOSEST(ic_clk * (tLOW + tf), MICRO) - 1 + offset; 386 + return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 387 + 1 + offset; 389 388 } 390 389 391 390 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)

+2

drivers/i2c/busses/i2c-designware-pcidrv.c

··· 396 396 { PCI_VDEVICE(ATI, 0x73a4), navi_amd }, 397 397 { PCI_VDEVICE(ATI, 0x73e4), navi_amd }, 398 398 { PCI_VDEVICE(ATI, 0x73c4), navi_amd }, 399 + { PCI_VDEVICE(ATI, 0x7444), navi_amd }, 400 + { PCI_VDEVICE(ATI, 0x7464), navi_amd }, 399 401 { 0,} 400 402 }; 401 403 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);

+2 -18

drivers/i2c/busses/i2c-designware-platdrv.c

··· 351 351 352 352 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { 353 353 dev_pm_set_driver_flags(&pdev->dev, 354 - DPM_FLAG_SMART_PREPARE | 355 - DPM_FLAG_MAY_SKIP_RESUME); 354 + DPM_FLAG_SMART_PREPARE); 356 355 } else { 357 356 dev_pm_set_driver_flags(&pdev->dev, 358 357 DPM_FLAG_SMART_PREPARE | 359 - DPM_FLAG_SMART_SUSPEND | 360 - DPM_FLAG_MAY_SKIP_RESUME); 358 + DPM_FLAG_SMART_SUSPEND); 361 359 } 362 360 363 361 device_enable_async_suspend(&pdev->dev); ··· 417 419 */ 418 420 return !has_acpi_companion(dev); 419 421 } 420 - 421 - static void dw_i2c_plat_complete(struct device *dev) 422 - { 423 - /* 424 - * The device can only be in runtime suspend at this point if it has not 425 - * been resumed throughout the ending system suspend/resume cycle, so if 426 - * the platform firmware might mess up with it, request the runtime PM 427 - * framework to resume it. 428 - */ 429 - if (pm_runtime_suspended(dev) && pm_resume_via_firmware()) 430 - pm_request_resume(dev); 431 - } 432 422 #else 433 423 #define dw_i2c_plat_prepare NULL 434 - #define dw_i2c_plat_complete NULL 435 424 #endif 436 425 437 426 #ifdef CONFIG_PM ··· 468 483 469 484 static const struct dev_pm_ops dw_i2c_dev_pm_ops = { 470 485 .prepare = dw_i2c_plat_prepare, 471 - .complete = dw_i2c_plat_complete, 472 486 SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume) 473 487 SET_RUNTIME_PM_OPS(dw_i2c_plat_runtime_suspend, dw_i2c_plat_runtime_resume, NULL) 474 488 };

+2 -2

drivers/i2c/busses/i2c-mxs.c

··· 826 826 /* Setup the DMA */ 827 827 i2c->dmach = dma_request_chan(dev, "rx-tx"); 828 828 if (IS_ERR(i2c->dmach)) { 829 - dev_err(dev, "Failed to request dma\n"); 830 - return PTR_ERR(i2c->dmach); 829 + return dev_err_probe(dev, PTR_ERR(i2c->dmach), 830 + "Failed to request dma\n"); 831 831 } 832 832 833 833 platform_set_drvdata(pdev, i2c);

+22 -22

drivers/i2c/busses/i2c-rk3x.c

··· 80 80 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 81 81 82 82 /** 83 - * struct i2c_spec_values: 83 + * struct i2c_spec_values - I2C specification values for various modes 84 84 * @min_hold_start_ns: min hold time (repeated) START condition 85 85 * @min_low_ns: min LOW period of the SCL clock 86 86 * @min_high_ns: min HIGH period of the SCL cloc ··· 136 136 }; 137 137 138 138 /** 139 - * struct rk3x_i2c_calced_timings: 139 + * struct rk3x_i2c_calced_timings - calculated V1 timings 140 140 * @div_low: Divider output for low 141 141 * @div_high: Divider output for high 142 142 * @tuning: Used to adjust setup/hold data time, ··· 159 159 }; 160 160 161 161 /** 162 - * struct rk3x_i2c_soc_data: 162 + * struct rk3x_i2c_soc_data - SOC-specific data 163 163 * @grf_offset: offset inside the grf regmap for setting the i2c type 164 164 * @calc_timings: Callback function for i2c timing information calculated 165 165 */ ··· 239 239 } 240 240 241 241 /** 242 - * Generate a START condition, which triggers a REG_INT_START interrupt. 242 + * rk3x_i2c_start - Generate a START condition, which triggers a REG_INT_START interrupt. 243 + * @i2c: target controller data 243 244 */ 244 245 static void rk3x_i2c_start(struct rk3x_i2c *i2c) 245 246 { ··· 259 258 } 260 259 261 260 /** 262 - * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 263 - * 261 + * rk3x_i2c_stop - Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 262 + * @i2c: target controller data 264 263 * @error: Error code to return in rk3x_i2c_xfer 265 264 */ 266 265 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) ··· 299 298 } 300 299 301 300 /** 302 - * Setup a read according to i2c->msg 301 + * rk3x_i2c_prepare_read - Setup a read according to i2c->msg 302 + * @i2c: target controller data 303 303 */ 304 304 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 305 305 { ··· 331 329 } 332 330 333 331 /** 334 - * Fill the transmit buffer with data from i2c->msg 332 + * rk3x_i2c_fill_transmit_buf - Fill the transmit buffer with data from i2c->msg 333 + * @i2c: target controller data 335 334 */ 336 335 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 337 336 { ··· 535 532 } 536 533 537 534 /** 538 - * Get timing values of I2C specification 539 - * 535 + * rk3x_i2c_get_spec - Get timing values of I2C specification 540 536 * @speed: Desired SCL frequency 541 537 * 542 - * Returns: Matched i2c spec values. 538 + * Return: Matched i2c_spec_values. 543 539 */ 544 540 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed) 545 541 { ··· 551 549 } 552 550 553 551 /** 554 - * Calculate divider values for desired SCL frequency 555 - * 552 + * rk3x_i2c_v0_calc_timings - Calculate divider values for desired SCL frequency 556 553 * @clk_rate: I2C input clock rate 557 554 * @t: Known I2C timing information 558 555 * @t_calc: Caculated rk3x private timings that would be written into regs 559 556 * 560 - * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 557 + * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case 561 558 * a best-effort divider value is returned in divs. If the target rate is 562 559 * too high, we silently use the highest possible rate. 563 560 */ ··· 711 710 } 712 711 713 712 /** 714 - * Calculate timing values for desired SCL frequency 715 - * 713 + * rk3x_i2c_v1_calc_timings - Calculate timing values for desired SCL frequency 716 714 * @clk_rate: I2C input clock rate 717 715 * @t: Known I2C timing information 718 716 * @t_calc: Caculated rk3x private timings that would be written into regs 719 717 * 720 - * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 718 + * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case 721 719 * a best-effort divider value is returned in divs. If the target rate is 722 720 * too high, we silently use the highest possible rate. 723 721 * The following formulas are v1's method to calculate timings. ··· 960 960 } 961 961 962 962 /** 963 - * Setup I2C registers for an I2C operation specified by msgs, num. 964 - * 965 - * Must be called with i2c->lock held. 966 - * 963 + * rk3x_i2c_setup - Setup I2C registers for an I2C operation specified by msgs, num. 964 + * @i2c: target controller data 967 965 * @msgs: I2C msgs to process 968 966 * @num: Number of msgs 969 967 * 970 - * returns: Number of I2C msgs processed or negative in case of error 968 + * Must be called with i2c->lock held. 969 + * 970 + * Return: Number of I2C msgs processed or negative in case of error 971 971 */ 972 972 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 973 973 {

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