Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (48 commits)
LIB82596: correct data types for hardware addresses
via-velocity: don't oops on MTU change (resend)
Stop phy code from returning success to unknown ioctls.
SET_NETDEV_DEV() in fec_mpc52xx.c
net: smc911x: only enable for mpr2 on sh.
e1000: Fix NAPI state bug when Rx complete
sky2: turn of dynamic Tx watermark workaround (FE+ only)
sky2: don't use AER routines
sky2: revert to access PCI config via device space
cxgb - fix stats
cxgb - fix NAPI
cxgb - fix T2 GSO
ucc_geth: handle passing of RX-only and TX-only internal delay PHY connection type parameters
phylib: marvell: add support for TX-only and RX-only Internal Delay
phylib: add PHY interface modes for internal delay for tx and rx only
skge: MTU changing fix
skge: serial mode register values
skge version 1.13
skge: increase TX threshold for Jumbo
skge: fiber link up/down fix
...
+443
-414
+2
-2
drivers/net/Kconfig
+2
-2
drivers/net/Kconfig
···
888
888
tristate "SMC 91C9x/91C1xxx support"
889
889
select CRC32
890
890
select MII
891
-
depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00 || BFIN
891
+
depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00 || BLACKFIN
892
892
help
893
893
This is a driver for SMC's 91x series of Ethernet chipsets,
894
894
including the SMC91C94 and the SMC91C111. Say Y if you want it
···
926
926
tristate "SMSC LAN911[5678] support"
927
927
select CRC32
928
928
select MII
929
-
depends on ARCH_PXA || SUPERH
929
+
depends on ARCH_PXA || SH_MAGIC_PANEL_R2
930
930
help
931
931
This is a driver for SMSC's LAN911x series of Ethernet chipsets
932
932
including the new LAN9115, LAN9116, LAN9117, and LAN9118.
+6
drivers/net/amd8111e.c
+6
drivers/net/amd8111e.c
···
1340
1340
struct amd8111e_priv *lp = netdev_priv(dev);
1341
1341
netif_stop_queue(dev);
1342
1342
1343
+
#ifdef CONFIG_AMD8111E_NAPI
1343
1344
napi_disable(&lp->napi);
1345
+
#endif
1344
1346
1345
1347
spin_lock_irq(&lp->lock);
1346
1348
···
1374
1372
dev->name, dev))
1375
1373
return -EAGAIN;
1376
1374
1375
+
#ifdef CONFIG_AMD8111E_NAPI
1377
1376
napi_enable(&lp->napi);
1377
+
#endif
1378
1378
1379
1379
spin_lock_irq(&lp->lock);
1380
1380
···
1384
1380
1385
1381
if(amd8111e_restart(dev)){
1386
1382
spin_unlock_irq(&lp->lock);
1383
+
#ifdef CONFIG_AMD8111E_NAPI
1387
1384
napi_disable(&lp->napi);
1385
+
#endif
1388
1386
if (dev->irq)
1389
1387
free_irq(dev->irq, dev);
1390
1388
return -ENOMEM;
+1
-1
drivers/net/bfin_mac.c
+1
-1
drivers/net/bfin_mac.c
+54
-18
drivers/net/chelsio/cxgb2.c
+54
-18
drivers/net/chelsio/cxgb2.c
···
374
374
"TxInternalMACXmitError",
375
375
"TxFramesWithExcessiveDeferral",
376
376
"TxFCSErrors",
377
-
377
+
"TxJumboFramesOk",
378
+
"TxJumboOctetsOk",
379
+
378
380
"RxOctetsOK",
379
381
"RxOctetsBad",
380
382
"RxUnicastFramesOK",
···
394
392
"RxInRangeLengthErrors",
395
393
"RxOutOfRangeLengthField",
396
394
"RxFrameTooLongErrors",
395
+
"RxJumboFramesOk",
396
+
"RxJumboOctetsOk",
397
397
398
398
/* Port stats */
399
-
"RxPackets",
400
399
"RxCsumGood",
401
-
"TxPackets",
402
400
"TxCsumOffload",
403
401
"TxTso",
404
402
"RxVlan",
405
403
"TxVlan",
406
-
404
+
"TxNeedHeadroom",
405
+
407
406
/* Interrupt stats */
408
407
"rx drops",
409
408
"pure_rsps",
···
466
463
const struct cmac_statistics *s;
467
464
const struct sge_intr_counts *t;
468
465
struct sge_port_stats ss;
469
-
unsigned int len;
470
466
471
467
s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL);
472
-
473
-
len = sizeof(u64)*(&s->TxFCSErrors + 1 - &s->TxOctetsOK);
474
-
memcpy(data, &s->TxOctetsOK, len);
475
-
data += len;
476
-
477
-
len = sizeof(u64)*(&s->RxFrameTooLongErrors + 1 - &s->RxOctetsOK);
478
-
memcpy(data, &s->RxOctetsOK, len);
479
-
data += len;
480
-
481
-
t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss);
482
-
memcpy(data, &ss, sizeof(ss));
483
-
data += sizeof(ss);
484
-
485
468
t = t1_sge_get_intr_counts(adapter->sge);
469
+
t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss);
470
+
471
+
*data++ = s->TxOctetsOK;
472
+
*data++ = s->TxOctetsBad;
473
+
*data++ = s->TxUnicastFramesOK;
474
+
*data++ = s->TxMulticastFramesOK;
475
+
*data++ = s->TxBroadcastFramesOK;
476
+
*data++ = s->TxPauseFrames;
477
+
*data++ = s->TxFramesWithDeferredXmissions;
478
+
*data++ = s->TxLateCollisions;
479
+
*data++ = s->TxTotalCollisions;
480
+
*data++ = s->TxFramesAbortedDueToXSCollisions;
481
+
*data++ = s->TxUnderrun;
482
+
*data++ = s->TxLengthErrors;
483
+
*data++ = s->TxInternalMACXmitError;
484
+
*data++ = s->TxFramesWithExcessiveDeferral;
485
+
*data++ = s->TxFCSErrors;
486
+
*data++ = s->TxJumboFramesOK;
487
+
*data++ = s->TxJumboOctetsOK;
488
+
489
+
*data++ = s->RxOctetsOK;
490
+
*data++ = s->RxOctetsBad;
491
+
*data++ = s->RxUnicastFramesOK;
492
+
*data++ = s->RxMulticastFramesOK;
493
+
*data++ = s->RxBroadcastFramesOK;
494
+
*data++ = s->RxPauseFrames;
495
+
*data++ = s->RxFCSErrors;
496
+
*data++ = s->RxAlignErrors;
497
+
*data++ = s->RxSymbolErrors;
498
+
*data++ = s->RxDataErrors;
499
+
*data++ = s->RxSequenceErrors;
500
+
*data++ = s->RxRuntErrors;
501
+
*data++ = s->RxJabberErrors;
502
+
*data++ = s->RxInternalMACRcvError;
503
+
*data++ = s->RxInRangeLengthErrors;
504
+
*data++ = s->RxOutOfRangeLengthField;
505
+
*data++ = s->RxFrameTooLongErrors;
506
+
*data++ = s->RxJumboFramesOK;
507
+
*data++ = s->RxJumboOctetsOK;
508
+
509
+
*data++ = ss.rx_cso_good;
510
+
*data++ = ss.tx_cso;
511
+
*data++ = ss.tx_tso;
512
+
*data++ = ss.vlan_xtract;
513
+
*data++ = ss.vlan_insert;
514
+
*data++ = ss.tx_need_hdrroom;
515
+
486
516
*data++ = t->rx_drops;
487
517
*data++ = t->pure_rsps;
488
518
*data++ = t->unhandled_irqs;
+44
-66
drivers/net/chelsio/pm3393.c
+44
-66
drivers/net/chelsio/pm3393.c
···
45
45
46
46
#include <linux/crc32.h>
47
47
48
-
#define OFFSET(REG_ADDR) (REG_ADDR << 2)
48
+
#define OFFSET(REG_ADDR) ((REG_ADDR) << 2)
49
49
50
50
/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
51
51
#define MAX_FRAME_SIZE 9600
···
428
428
return 0;
429
429
}
430
430
431
-
static void pm3393_rmon_update(struct adapter *adapter, u32 offs, u64 *val,
432
-
int over)
433
-
{
434
-
u32 val0, val1, val2;
435
-
436
-
t1_tpi_read(adapter, offs, &val0);
437
-
t1_tpi_read(adapter, offs + 4, &val1);
438
-
t1_tpi_read(adapter, offs + 8, &val2);
439
-
440
-
*val &= ~0ull << 40;
441
-
*val |= val0 & 0xffff;
442
-
*val |= (val1 & 0xffff) << 16;
443
-
*val |= (u64)(val2 & 0xff) << 32;
444
-
445
-
if (over)
446
-
*val += 1ull << 40;
431
+
#define RMON_UPDATE(mac, name, stat_name) \
432
+
{ \
433
+
t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
434
+
t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
435
+
t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
436
+
(mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
437
+
((u64)(val1 & 0xffff) << 16) | \
438
+
((u64)(val2 & 0xff) << 32) | \
439
+
((mac)->stats.stat_name & \
440
+
0xffffff0000000000ULL); \
441
+
if (ro & \
442
+
(1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \
443
+
(mac)->stats.stat_name += 1ULL << 40; \
447
444
}
448
445
449
446
static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
450
447
int flag)
451
448
{
452
-
static struct {
453
-
unsigned int reg;
454
-
unsigned int offset;
455
-
} hw_stats [] = {
456
-
457
-
#define HW_STAT(name, stat_name) \
458
-
{ name, (&((struct cmac_statistics *)NULL)->stat_name) - (u64 *)NULL }
459
-
460
-
/* Rx stats */
461
-
HW_STAT(RxOctetsReceivedOK, RxOctetsOK),
462
-
HW_STAT(RxUnicastFramesReceivedOK, RxUnicastFramesOK),
463
-
HW_STAT(RxMulticastFramesReceivedOK, RxMulticastFramesOK),
464
-
HW_STAT(RxBroadcastFramesReceivedOK, RxBroadcastFramesOK),
465
-
HW_STAT(RxPAUSEMACCtrlFramesReceived, RxPauseFrames),
466
-
HW_STAT(RxFrameCheckSequenceErrors, RxFCSErrors),
467
-
HW_STAT(RxFramesLostDueToInternalMACErrors,
468
-
RxInternalMACRcvError),
469
-
HW_STAT(RxSymbolErrors, RxSymbolErrors),
470
-
HW_STAT(RxInRangeLengthErrors, RxInRangeLengthErrors),
471
-
HW_STAT(RxFramesTooLongErrors , RxFrameTooLongErrors),
472
-
HW_STAT(RxJabbers, RxJabberErrors),
473
-
HW_STAT(RxFragments, RxRuntErrors),
474
-
HW_STAT(RxUndersizedFrames, RxRuntErrors),
475
-
HW_STAT(RxJumboFramesReceivedOK, RxJumboFramesOK),
476
-
HW_STAT(RxJumboOctetsReceivedOK, RxJumboOctetsOK),
477
-
478
-
/* Tx stats */
479
-
HW_STAT(TxOctetsTransmittedOK, TxOctetsOK),
480
-
HW_STAT(TxFramesLostDueToInternalMACTransmissionError,
481
-
TxInternalMACXmitError),
482
-
HW_STAT(TxTransmitSystemError, TxFCSErrors),
483
-
HW_STAT(TxUnicastFramesTransmittedOK, TxUnicastFramesOK),
484
-
HW_STAT(TxMulticastFramesTransmittedOK, TxMulticastFramesOK),
485
-
HW_STAT(TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK),
486
-
HW_STAT(TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames),
487
-
HW_STAT(TxJumboFramesReceivedOK, TxJumboFramesOK),
488
-
HW_STAT(TxJumboOctetsReceivedOK, TxJumboOctetsOK)
489
-
}, *p = hw_stats;
490
-
u64 ro;
491
-
u32 val0, val1, val2, val3;
492
-
u64 *stats = (u64 *) &mac->stats;
493
-
unsigned int i;
449
+
u64 ro;
450
+
u32 val0, val1, val2, val3;
494
451
495
452
/* Snap the counters */
496
453
pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
···
461
504
ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
462
505
(((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
463
506
464
-
for (i = 0; i < ARRAY_SIZE(hw_stats); i++) {
465
-
unsigned reg = p->reg - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW;
507
+
/* Rx stats */
508
+
RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
509
+
RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
510
+
RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
511
+
RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
512
+
RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
513
+
RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
514
+
RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
515
+
RxInternalMACRcvError);
516
+
RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
517
+
RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
518
+
RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
519
+
RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
520
+
RMON_UPDATE(mac, RxFragments, RxRuntErrors);
521
+
RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
522
+
RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
523
+
RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
466
524
467
-
pm3393_rmon_update((mac)->adapter, OFFSET(p->reg),
468
-
stats + p->offset, ro & (reg >> 2));
469
-
}
470
-
471
-
525
+
/* Tx stats */
526
+
RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
527
+
RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
528
+
TxInternalMACXmitError);
529
+
RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
530
+
RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
531
+
RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
532
+
RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
533
+
RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
534
+
RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
535
+
RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
472
536
473
537
return &mac->stats;
474
538
}
+17
-27
drivers/net/chelsio/sge.c
+17
-27
drivers/net/chelsio/sge.c
···
986
986
for_each_possible_cpu(cpu) {
987
987
struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
988
988
989
-
ss->rx_packets += st->rx_packets;
990
989
ss->rx_cso_good += st->rx_cso_good;
991
-
ss->tx_packets += st->tx_packets;
992
990
ss->tx_cso += st->tx_cso;
993
991
ss->tx_tso += st->tx_tso;
992
+
ss->tx_need_hdrroom += st->tx_need_hdrroom;
994
993
ss->vlan_xtract += st->vlan_xtract;
995
994
ss->vlan_insert += st->vlan_insert;
996
995
}
···
1379
1380
__skb_pull(skb, sizeof(*p));
1380
1381
1381
1382
st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id());
1382
-
st->rx_packets++;
1383
1383
1384
1384
skb->protocol = eth_type_trans(skb, adapter->port[p->iff].dev);
1385
1385
skb->dev->last_rx = jiffies;
···
1622
1624
{
1623
1625
struct adapter *adapter = container_of(napi, struct adapter, napi);
1624
1626
struct net_device *dev = adapter->port[0].dev;
1625
-
int work_done;
1627
+
int work_done = process_responses(adapter, budget);
1626
1628
1627
-
work_done = process_responses(adapter, budget);
1628
-
1629
-
if (likely(!responses_pending(adapter))) {
1629
+
if (likely(work_done < budget)) {
1630
1630
netif_rx_complete(dev, napi);
1631
1631
writel(adapter->sge->respQ.cidx,
1632
1632
adapter->regs + A_SG_SLEEPING);
···
1844
1848
{
1845
1849
struct adapter *adapter = dev->priv;
1846
1850
struct sge *sge = adapter->sge;
1847
-
struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port], smp_processor_id());
1851
+
struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port],
1852
+
smp_processor_id());
1848
1853
struct cpl_tx_pkt *cpl;
1849
1854
struct sk_buff *orig_skb = skb;
1850
1855
int ret;
1851
1856
1852
1857
if (skb->protocol == htons(ETH_P_CPL5))
1853
1858
goto send;
1859
+
1860
+
/*
1861
+
* We are using a non-standard hard_header_len.
1862
+
* Allocate more header room in the rare cases it is not big enough.
1863
+
*/
1864
+
if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1865
+
skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1866
+
++st->tx_need_hdrroom;
1867
+
dev_kfree_skb_any(orig_skb);
1868
+
if (!skb)
1869
+
return NETDEV_TX_OK;
1870
+
}
1854
1871
1855
1872
if (skb_shinfo(skb)->gso_size) {
1856
1873
int eth_type;
···
1896
1887
skb->len, eth_hdr_len(skb->data), dev->mtu);
1897
1888
dev_kfree_skb_any(skb);
1898
1889
return NETDEV_TX_OK;
1899
-
}
1900
-
1901
-
/*
1902
-
* We are using a non-standard hard_header_len and some kernel
1903
-
* components, such as pktgen, do not handle it right.
1904
-
* Complain when this happens but try to fix things up.
1905
-
*/
1906
-
if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1907
-
pr_debug("%s: headroom %d header_len %d\n", dev->name,
1908
-
skb_headroom(skb), dev->hard_header_len);
1909
-
1910
-
if (net_ratelimit())
1911
-
printk(KERN_ERR "%s: inadequate headroom in "
1912
-
"Tx packet\n", dev->name);
1913
-
skb = skb_realloc_headroom(skb, sizeof(*cpl));
1914
-
dev_kfree_skb_any(orig_skb);
1915
-
if (!skb)
1916
-
return NETDEV_TX_OK;
1917
1890
}
1918
1891
1919
1892
if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
···
1943
1952
cpl->vlan_valid = 0;
1944
1953
1945
1954
send:
1946
-
st->tx_packets++;
1947
1955
dev->trans_start = jiffies;
1948
1956
ret = t1_sge_tx(skb, adapter, 0, dev);
1949
1957
+1
-2
drivers/net/chelsio/sge.h
+1
-2
drivers/net/chelsio/sge.h
···
57
57
};
58
58
59
59
struct sge_port_stats {
60
-
u64 rx_packets; /* # of Ethernet packets received */
61
60
u64 rx_cso_good; /* # of successful RX csum offloads */
62
-
u64 tx_packets; /* # of TX packets */
63
61
u64 tx_cso; /* # of TX checksum offloads */
64
62
u64 tx_tso; /* # of TSO requests */
65
63
u64 vlan_xtract; /* # of VLAN tag extractions */
66
64
u64 vlan_insert; /* # of VLAN tag insertions */
65
+
u64 tx_need_hdrroom; /* # of TX skbs in need of more header room */
67
66
};
68
67
69
68
struct sk_buff;
+1
-1
drivers/net/e1000/e1000_main.c
+1
-1
drivers/net/e1000/e1000_main.c
···
3942
3942
&work_done, budget);
3943
3943
3944
3944
/* If no Tx and not enough Rx work done, exit the polling mode */
3945
-
if ((!tx_cleaned && (work_done < budget)) ||
3945
+
if ((!tx_cleaned && (work_done == 0)) ||
3946
3946
!netif_running(poll_dev)) {
3947
3947
quit_polling:
3948
3948
if (likely(adapter->itr_setting & 3))
+1
-1
drivers/net/ehea/ehea.h
+1
-1
drivers/net/ehea/ehea.h
+12
-8
drivers/net/ehea/ehea_main.c
+12
-8
drivers/net/ehea/ehea_main.c
···
136
136
struct ehea_port *port = netdev_priv(dev);
137
137
struct net_device_stats *stats = &port->stats;
138
138
struct hcp_ehea_port_cb2 *cb2;
139
-
u64 hret, rx_packets;
139
+
u64 hret, rx_packets, tx_packets;
140
140
int i;
141
141
142
142
memset(stats, 0, sizeof(*stats));
···
162
162
for (i = 0; i < port->num_def_qps; i++)
163
163
rx_packets += port->port_res[i].rx_packets;
164
164
165
-
stats->tx_packets = cb2->txucp + cb2->txmcp + cb2->txbcp;
165
+
tx_packets = 0;
166
+
for (i = 0; i < port->num_def_qps + port->num_add_tx_qps; i++)
167
+
tx_packets += port->port_res[i].tx_packets;
168
+
169
+
stats->tx_packets = tx_packets;
166
170
stats->multicast = cb2->rxmcp;
167
171
stats->rx_errors = cb2->rxuerr;
168
172
stats->rx_bytes = cb2->rxo;
···
410
406
if (cqe->status & EHEA_CQE_STAT_ERR_CRC)
411
407
pr->p_stats.err_frame_crc++;
412
408
413
-
if (netif_msg_rx_err(pr->port)) {
414
-
ehea_error("CQE Error for QP %d", pr->qp->init_attr.qp_nr);
415
-
ehea_dump(cqe, sizeof(*cqe), "CQE");
416
-
}
417
-
418
409
if (rq == 2) {
419
410
*processed_rq2 += 1;
420
411
skb = get_skb_by_index(pr->rq2_skba.arr, pr->rq2_skba.len, cqe);
···
421
422
}
422
423
423
424
if (cqe->status & EHEA_CQE_STAT_FAT_ERR_MASK) {
424
-
ehea_error("Critical receive error. Resetting port.");
425
+
if (netif_msg_rx_err(pr->port)) {
426
+
ehea_error("Critical receive error for QP %d. "
427
+
"Resetting port.", pr->qp->init_attr.qp_nr);
428
+
ehea_dump(cqe, sizeof(*cqe), "CQE");
429
+
}
425
430
schedule_work(&pr->port->reset_task);
426
431
return 1;
427
432
}
···
2003
2000
}
2004
2001
2005
2002
ehea_post_swqe(pr->qp, swqe);
2003
+
pr->tx_packets++;
2006
2004
2007
2005
if (unlikely(atomic_read(&pr->swqe_avail) <= 1)) {
2008
2006
spin_lock_irqsave(&pr->netif_queue, flags);
+2
-2
drivers/net/ehea/ehea_qmr.h
+2
-2
drivers/net/ehea/ehea_qmr.h
···
145
145
#define EHEA_CQE_VLAN_TAG_XTRACT 0x0400
146
146
147
147
#define EHEA_CQE_TYPE_RQ 0x60
148
-
#define EHEA_CQE_STAT_ERR_MASK 0x720F
149
-
#define EHEA_CQE_STAT_FAT_ERR_MASK 0x1F
148
+
#define EHEA_CQE_STAT_ERR_MASK 0x700F
149
+
#define EHEA_CQE_STAT_FAT_ERR_MASK 0xF
150
150
#define EHEA_CQE_STAT_ERR_TCP 0x4000
151
151
#define EHEA_CQE_STAT_ERR_IP 0x2000
152
152
#define EHEA_CQE_STAT_ERR_CRC 0x1000
+2
drivers/net/fec_mpc52xx.c
+2
drivers/net/fec_mpc52xx.c
+25
-13
drivers/net/forcedeth.c
+25
-13
drivers/net/forcedeth.c
···
5286
5286
if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5287
5287
np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5288
5288
dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5289
-
for (i = 0; i < 5000; i++) {
5290
-
msleep(1);
5291
-
if (nv_mgmt_acquire_sema(dev)) {
5292
-
/* management unit setup the phy already? */
5293
-
if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5294
-
NVREG_XMITCTL_SYNC_PHY_INIT) {
5295
-
/* phy is inited by mgmt unit */
5296
-
phyinitialized = 1;
5297
-
dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5298
-
} else {
5299
-
/* we need to init the phy */
5300
-
}
5301
-
break;
5289
+
if (nv_mgmt_acquire_sema(dev)) {
5290
+
/* management unit setup the phy already? */
5291
+
if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5292
+
NVREG_XMITCTL_SYNC_PHY_INIT) {
5293
+
/* phy is inited by mgmt unit */
5294
+
phyinitialized = 1;
5295
+
dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5296
+
} else {
5297
+
/* we need to init the phy */
5302
5298
}
5303
5299
}
5304
5300
}
···
5607
5611
},
5608
5612
{ /* MCP77 Ethernet Controller */
5609
5613
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5614
+
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5615
+
},
5616
+
{ /* MCP79 Ethernet Controller */
5617
+
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5618
+
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5619
+
},
5620
+
{ /* MCP79 Ethernet Controller */
5621
+
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5622
+
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5623
+
},
5624
+
{ /* MCP79 Ethernet Controller */
5625
+
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5626
+
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5627
+
},
5628
+
{ /* MCP79 Ethernet Controller */
5629
+
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5610
5630
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5611
5631
},
5612
5632
{0,},
+20
-11
drivers/net/ibm_newemac/core.c
+20
-11
drivers/net/ibm_newemac/core.c
···
642
642
DBG(dev, "reset_work" NL);
643
643
644
644
mutex_lock(&dev->link_lock);
645
-
emac_netif_stop(dev);
646
-
emac_full_tx_reset(dev);
647
-
emac_netif_start(dev);
645
+
if (dev->opened) {
646
+
emac_netif_stop(dev);
647
+
emac_full_tx_reset(dev);
648
+
emac_netif_start(dev);
649
+
}
648
650
mutex_unlock(&dev->link_lock);
649
651
}
650
652
···
1065
1063
dev->rx_sg_skb = NULL;
1066
1064
1067
1065
mutex_lock(&dev->link_lock);
1066
+
dev->opened = 1;
1068
1067
1069
-
/* XXX Start PHY polling now. Shouldn't wr do like sungem instead and
1070
-
* always poll the PHY even when the iface is down ? That would allow
1071
-
* things like laptop-net to work. --BenH
1068
+
/* Start PHY polling now.
1072
1069
*/
1073
1070
if (dev->phy.address >= 0) {
1074
1071
int link_poll_interval;
···
1146
1145
int link_poll_interval;
1147
1146
1148
1147
mutex_lock(&dev->link_lock);
1149
-
1150
1148
DBG2(dev, "link timer" NL);
1149
+
1150
+
if (!dev->opened)
1151
+
goto bail;
1151
1152
1152
1153
if (dev->phy.def->ops->poll_link(&dev->phy)) {
1153
1154
if (!netif_carrier_ok(dev->ndev)) {
···
1173
1170
link_poll_interval = PHY_POLL_LINK_OFF;
1174
1171
}
1175
1172
schedule_delayed_work(&dev->link_work, link_poll_interval);
1176
-
1173
+
bail:
1177
1174
mutex_unlock(&dev->link_lock);
1178
1175
}
1179
1176
1180
1177
static void emac_force_link_update(struct emac_instance *dev)
1181
1178
{
1182
1179
netif_carrier_off(dev->ndev);
1180
+
smp_rmb();
1183
1181
if (dev->link_polling) {
1184
1182
cancel_rearming_delayed_work(&dev->link_work);
1185
1183
if (dev->link_polling)
···
1195
1191
1196
1192
DBG(dev, "close" NL);
1197
1193
1198
-
if (dev->phy.address >= 0)
1194
+
if (dev->phy.address >= 0) {
1195
+
dev->link_polling = 0;
1199
1196
cancel_rearming_delayed_work(&dev->link_work);
1200
-
1197
+
}
1198
+
mutex_lock(&dev->link_lock);
1201
1199
emac_netif_stop(dev);
1202
-
flush_scheduled_work();
1200
+
dev->opened = 0;
1201
+
mutex_unlock(&dev->link_lock);
1203
1202
1204
1203
emac_rx_disable(dev);
1205
1204
emac_tx_disable(dev);
···
2762
2755
dev_set_drvdata(&ofdev->dev, NULL);
2763
2756
2764
2757
unregister_netdev(dev->ndev);
2758
+
2759
+
flush_scheduled_work();
2765
2760
2766
2761
if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2767
2762
tah_detach(dev->tah_dev, dev->tah_port);
+1
drivers/net/ibm_newemac/core.h
+1
drivers/net/ibm_newemac/core.h
+25
-25
drivers/net/lib82596.c
+25
-25
drivers/net/lib82596.c
···
176
176
struct i596_tbd {
177
177
unsigned short size;
178
178
unsigned short pad;
179
-
dma_addr_t next;
180
-
dma_addr_t data;
179
+
u32 next;
180
+
u32 data;
181
181
u32 cache_pad[5]; /* Total 32 bytes... */
182
182
};
183
183
···
195
195
struct i596_cmd *v_next; /* Address from CPUs viewpoint */
196
196
unsigned short status;
197
197
unsigned short command;
198
-
dma_addr_t b_next; /* Address from i596 viewpoint */
198
+
u32 b_next; /* Address from i596 viewpoint */
199
199
};
200
200
201
201
struct tx_cmd {
202
202
struct i596_cmd cmd;
203
-
dma_addr_t tbd;
203
+
u32 tbd;
204
204
unsigned short size;
205
205
unsigned short pad;
206
206
struct sk_buff *skb; /* So we can free it after tx */
···
237
237
struct i596_rfd {
238
238
unsigned short stat;
239
239
unsigned short cmd;
240
-
dma_addr_t b_next; /* Address from i596 viewpoint */
241
-
dma_addr_t rbd;
240
+
u32 b_next; /* Address from i596 viewpoint */
241
+
u32 rbd;
242
242
unsigned short count;
243
243
unsigned short size;
244
244
struct i596_rfd *v_next; /* Address from CPUs viewpoint */
···
249
249
};
250
250
251
251
struct i596_rbd {
252
-
/* hardware data */
253
-
unsigned short count;
254
-
unsigned short zero1;
255
-
dma_addr_t b_next;
256
-
dma_addr_t b_data; /* Address from i596 viewpoint */
257
-
unsigned short size;
258
-
unsigned short zero2;
259
-
/* driver data */
260
-
struct sk_buff *skb;
261
-
struct i596_rbd *v_next;
262
-
dma_addr_t b_addr; /* This rbd addr from i596 view */
263
-
unsigned char *v_data; /* Address from CPUs viewpoint */
252
+
/* hardware data */
253
+
unsigned short count;
254
+
unsigned short zero1;
255
+
u32 b_next;
256
+
u32 b_data; /* Address from i596 viewpoint */
257
+
unsigned short size;
258
+
unsigned short zero2;
259
+
/* driver data */
260
+
struct sk_buff *skb;
261
+
struct i596_rbd *v_next;
262
+
u32 b_addr; /* This rbd addr from i596 view */
263
+
unsigned char *v_data; /* Address from CPUs viewpoint */
264
264
/* Total 32 bytes... */
265
265
#ifdef __LP64__
266
266
u32 cache_pad[4];
···
275
275
struct i596_scb {
276
276
unsigned short status;
277
277
unsigned short command;
278
-
dma_addr_t cmd;
279
-
dma_addr_t rfd;
278
+
u32 cmd;
279
+
u32 rfd;
280
280
u32 crc_err;
281
281
u32 align_err;
282
282
u32 resource_err;
···
288
288
};
289
289
290
290
struct i596_iscp {
291
-
u32 stat;
292
-
dma_addr_t scb;
291
+
u32 stat;
292
+
u32 scb;
293
293
};
294
294
295
295
struct i596_scp {
296
-
u32 sysbus;
297
-
u32 pad;
298
-
dma_addr_t iscp;
296
+
u32 sysbus;
297
+
u32 pad;
298
+
u32 iscp;
299
299
};
300
300
301
301
struct i596_dma {
+17
-9
drivers/net/phy/marvell.c
+17
-9
drivers/net/phy/marvell.c
···
143
143
int err;
144
144
145
145
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
146
-
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
146
+
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
147
+
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
148
+
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
147
149
int temp;
148
150
151
+
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
152
+
if (temp < 0)
153
+
return temp;
154
+
149
155
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
150
-
temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
151
-
if (temp < 0)
152
-
return temp;
153
-
154
156
temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
155
-
156
-
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
157
-
if (err < 0)
158
-
return err;
157
+
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
158
+
temp &= ~MII_M1111_TX_DELAY;
159
+
temp |= MII_M1111_RX_DELAY;
160
+
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
161
+
temp &= ~MII_M1111_RX_DELAY;
162
+
temp |= MII_M1111_TX_DELAY;
159
163
}
164
+
165
+
err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
166
+
if (err < 0)
167
+
return err;
160
168
161
169
temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
162
170
if (temp < 0)
+3
drivers/net/phy/phy.c
+3
drivers/net/phy/phy.c
+23
-9
drivers/net/s2io.c
+23
-9
drivers/net/s2io.c
···
1081
1081
/* to set the swapper controle on the card */
1082
1082
if(s2io_set_swapper(nic)) {
1083
1083
DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1084
-
return -1;
1084
+
return -EIO;
1085
1085
}
1086
1086
1087
1087
/*
···
1503
1503
DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1504
1504
dev->name);
1505
1505
DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1506
-
return FAILURE;
1506
+
return -ENODEV;
1507
1507
}
1508
1508
}
1509
1509
···
1570
1570
if (time > 10) {
1571
1571
DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1572
1572
dev->name);
1573
-
return -1;
1573
+
return -ENODEV;
1574
1574
}
1575
1575
msleep(50);
1576
1576
time++;
···
1623
1623
if (time > 10) {
1624
1624
DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1625
1625
dev->name);
1626
-
return -1;
1626
+
return -ENODEV;
1627
1627
}
1628
1628
time++;
1629
1629
msleep(50);
···
3913
3913
static int s2io_close(struct net_device *dev)
3914
3914
{
3915
3915
struct s2io_nic *sp = dev->priv;
3916
+
3917
+
/* Return if the device is already closed *
3918
+
* Can happen when s2io_card_up failed in change_mtu *
3919
+
*/
3920
+
if (!is_s2io_card_up(sp))
3921
+
return 0;
3916
3922
3917
3923
netif_stop_queue(dev);
3918
3924
napi_disable(&sp->napi);
···
6361
6355
static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6362
6356
{
6363
6357
struct s2io_nic *sp = dev->priv;
6358
+
int ret = 0;
6364
6359
6365
6360
if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6366
6361
DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
···
6373
6366
if (netif_running(dev)) {
6374
6367
s2io_card_down(sp);
6375
6368
netif_stop_queue(dev);
6376
-
if (s2io_card_up(sp)) {
6369
+
ret = s2io_card_up(sp);
6370
+
if (ret) {
6377
6371
DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6378
6372
__FUNCTION__);
6373
+
return ret;
6379
6374
}
6380
6375
if (netif_queue_stopped(dev))
6381
6376
netif_wake_queue(dev);
···
6388
6379
writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6389
6380
}
6390
6381
6391
-
return 0;
6382
+
return ret;
6392
6383
}
6393
6384
6394
6385
/**
···
6786
6777
unsigned long flags;
6787
6778
register u64 val64 = 0;
6788
6779
6780
+
if (!is_s2io_card_up(sp))
6781
+
return;
6782
+
6789
6783
del_timer_sync(&sp->alarm_timer);
6790
6784
/* If s2io_set_link task is executing, wait till it completes. */
6791
6785
while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
···
6862
6850
u16 interruptible;
6863
6851
6864
6852
/* Initialize the H/W I/O registers */
6865
-
if (init_nic(sp) != 0) {
6853
+
ret = init_nic(sp);
6854
+
if (ret != 0) {
6866
6855
DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6867
6856
dev->name);
6868
-
s2io_reset(sp);
6869
-
return -ENODEV;
6857
+
if (ret != -EIO)
6858
+
s2io_reset(sp);
6859
+
return ret;
6870
6860
}
6871
6861
6872
6862
/*
+38
-70
drivers/net/skge.c
+38
-70
drivers/net/skge.c
···
44
44
#include "skge.h"
45
45
46
46
#define DRV_NAME "skge"
47
-
#define DRV_VERSION "1.12"
47
+
#define DRV_VERSION "1.13"
48
48
#define PFX DRV_NAME " "
49
49
50
50
#define DEFAULT_TX_RING_SIZE 128
···
1095
1095
{
1096
1096
struct net_device *dev = hw->dev[port];
1097
1097
struct skge_port *skge = netdev_priv(dev);
1098
-
u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1099
1098
1100
1099
xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1101
-
1102
-
cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1103
-
xm_write16(hw, port, XM_MMU_CMD, cmd);
1104
-
1105
-
/* dummy read to ensure writing */
1106
-
xm_read16(hw, port, XM_MMU_CMD);
1107
1100
1108
1101
if (netif_carrier_ok(dev))
1109
1102
skge_link_down(skge);
···
1187
1194
static void genesis_reset(struct skge_hw *hw, int port)
1188
1195
{
1189
1196
const u8 zero[8] = { 0 };
1197
+
u32 reg;
1190
1198
1191
1199
skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1192
1200
···
1203
1209
xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1204
1210
1205
1211
xm_outhash(hw, port, XM_HSM, zero);
1212
+
1213
+
/* Flush TX and RX fifo */
1214
+
reg = xm_read32(hw, port, XM_MODE);
1215
+
xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1216
+
xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1206
1217
}
1207
1218
1208
1219
···
1633
1634
}
1634
1635
xm_write16(hw, port, XM_RX_CMD, r);
1635
1636
1636
-
1637
1637
/* We want short frames padded to 60 bytes. */
1638
1638
xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1639
1639
1640
-
/*
1641
-
* Bump up the transmit threshold. This helps hold off transmit
1642
-
* underruns when we're blasting traffic from both ports at once.
1643
-
*/
1644
-
xm_write16(hw, port, XM_TX_THR, 512);
1640
+
/* Increase threshold for jumbo frames on dual port */
1641
+
if (hw->ports > 1 && jumbo)
1642
+
xm_write16(hw, port, XM_TX_THR, 1020);
1643
+
else
1644
+
xm_write16(hw, port, XM_TX_THR, 512);
1645
1645
1646
1646
/*
1647
1647
* Enable the reception of all error frames. This is is
···
1711
1713
{
1712
1714
struct skge_hw *hw = skge->hw;
1713
1715
int port = skge->port;
1714
-
u32 reg;
1716
+
unsigned retries = 1000;
1717
+
u16 cmd;
1718
+
1719
+
/* Disable Tx and Rx */
1720
+
cmd = xm_read16(hw, port, XM_MMU_CMD);
1721
+
cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1722
+
xm_write16(hw, port, XM_MMU_CMD, cmd);
1715
1723
1716
1724
genesis_reset(hw, port);
1717
1725
···
1725
1721
skge_write16(hw, B3_PA_CTRL,
1726
1722
port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1727
1723
1728
-
/*
1729
-
* If the transfer sticks at the MAC the STOP command will not
1730
-
* terminate if we don't flush the XMAC's transmit FIFO !
1731
-
*/
1732
-
xm_write32(hw, port, XM_MODE,
1733
-
xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1734
-
1735
-
1736
1724
/* Reset the MAC */
1737
-
skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1725
+
skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1726
+
do {
1727
+
skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1728
+
if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1729
+
break;
1730
+
} while (--retries > 0);
1738
1731
1739
1732
/* For external PHYs there must be special handling */
1740
1733
if (hw->phy_type != SK_PHY_XMAC) {
1741
-
reg = skge_read32(hw, B2_GP_IO);
1734
+
u32 reg = skge_read32(hw, B2_GP_IO);
1742
1735
if (port == 0) {
1743
1736
reg |= GP_DIR_0;
1744
1737
reg &= ~GP_IO_0;
···
1802
1801
xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1803
1802
++dev->stats.tx_fifo_errors;
1804
1803
}
1805
-
1806
-
if (status & XM_IS_RXF_OV) {
1807
-
xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1808
-
++dev->stats.rx_fifo_errors;
1809
-
}
1810
1804
}
1811
1805
1812
1806
static void genesis_link_up(struct skge_port *skge)
···
1858
1862
1859
1863
xm_write32(hw, port, XM_MODE, mode);
1860
1864
1861
-
/* Turn on detection of Tx underrun, Rx overrun */
1865
+
/* Turn on detection of Tx underrun */
1862
1866
msk = xm_read16(hw, port, XM_IMSK);
1863
-
msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
1867
+
msk &= ~XM_IS_TXF_UR;
1864
1868
xm_write16(hw, port, XM_IMSK, msk);
1865
1869
1866
1870
xm_read16(hw, port, XM_ISRC);
···
2190
2194
TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2191
2195
TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2192
2196
2193
-
/* serial mode register */
2194
-
reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2195
-
if (hw->dev[port]->mtu > 1500)
2197
+
/* configure the Serial Mode Register */
2198
+
reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2199
+
| GM_SMOD_VLAN_ENA
2200
+
| IPG_DATA_VAL(IPG_DATA_DEF);
2201
+
2202
+
if (hw->dev[port]->mtu > ETH_DATA_LEN)
2196
2203
reg |= GM_SMOD_JUMBO_ENA;
2197
2204
2198
2205
gma_write16(hw, port, GM_SERIAL_MODE, reg);
···
2618
2619
yukon_mac_init(hw, port);
2619
2620
spin_unlock_bh(&hw->phy_lock);
2620
2621
2621
-
/* Configure RAMbuffers */
2622
-
chunk = hw->ram_size / ((hw->ports + 1)*2);
2622
+
/* Configure RAMbuffers - equally between ports and tx/rx */
2623
+
chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2623
2624
ram_addr = hw->ram_offset + 2 * chunk * port;
2624
2625
2625
2626
skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
···
2896
2897
2897
2898
static int skge_change_mtu(struct net_device *dev, int new_mtu)
2898
2899
{
2899
-
struct skge_port *skge = netdev_priv(dev);
2900
-
struct skge_hw *hw = skge->hw;
2901
-
int port = skge->port;
2902
2900
int err;
2903
-
u16 ctl, reg;
2904
2901
2905
2902
if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2906
2903
return -EINVAL;
···
2906
2911
return 0;
2907
2912
}
2908
2913
2909
-
skge_write32(hw, B0_IMSK, 0);
2910
-
dev->trans_start = jiffies; /* prevent tx timeout */
2911
-
netif_stop_queue(dev);
2912
-
napi_disable(&skge->napi);
2913
-
2914
-
ctl = gma_read16(hw, port, GM_GP_CTRL);
2915
-
gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2916
-
2917
-
skge_rx_clean(skge);
2918
-
skge_rx_stop(hw, port);
2914
+
skge_down(dev);
2919
2915
2920
2916
dev->mtu = new_mtu;
2921
2917
2922
-
reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2923
-
if (new_mtu > 1500)
2924
-
reg |= GM_SMOD_JUMBO_ENA;
2925
-
gma_write16(hw, port, GM_SERIAL_MODE, reg);
2926
-
2927
-
skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2928
-
2929
-
err = skge_rx_fill(dev);
2930
-
wmb();
2931
-
if (!err)
2932
-
skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2933
-
skge_write32(hw, B0_IMSK, hw->intr_mask);
2934
-
2918
+
err = skge_up(dev);
2935
2919
if (err)
2936
2920
dev_close(dev);
2937
-
else {
2938
-
gma_write16(hw, port, GM_GP_CTRL, ctl);
2939
-
2940
-
napi_enable(&skge->napi);
2941
-
netif_wake_queue(dev);
2942
-
}
2943
2921
2944
2922
return err;
2945
2923
}
+49
-72
drivers/net/sky2.c
+49
-72
drivers/net/sky2.c
···
31
31
#include <linux/etherdevice.h>
32
32
#include <linux/ethtool.h>
33
33
#include <linux/pci.h>
34
-
#include <linux/aer.h>
35
34
#include <linux/ip.h>
36
35
#include <net/ip.h>
37
36
#include <linux/tcp.h>
···
239
240
sky2_write8(hw, B2_Y2_CLK_GATE, 0);
240
241
241
242
if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
242
-
struct pci_dev *pdev = hw->pdev;
243
243
u32 reg;
244
244
245
-
pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
245
+
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246
246
247
-
pci_read_config_dword(pdev, PCI_DEV_REG4, ®);
247
+
reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248
248
/* set all bits to 0 except bits 15..12 and 8 */
249
249
reg &= P_ASPM_CONTROL_MSK;
250
-
pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
250
+
sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251
251
252
-
pci_read_config_dword(pdev, PCI_DEV_REG5, ®);
252
+
reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253
253
/* set all bits to 0 except bits 28 & 27 */
254
254
reg &= P_CTL_TIM_VMAIN_AV_MSK;
255
-
pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
255
+
sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256
256
257
-
pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
257
+
sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258
258
259
259
/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260
260
reg = sky2_read32(hw, B2_GP_IO);
···
617
619
618
620
static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
619
621
{
620
-
struct pci_dev *pdev = hw->pdev;
621
622
u32 reg1;
622
623
static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
623
624
static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
624
625
625
-
pci_read_config_dword(pdev, PCI_DEV_REG1, ®1);
626
+
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
626
627
/* Turn on/off phy power saving */
627
628
if (onoff)
628
629
reg1 &= ~phy_power[port];
···
631
634
if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
632
635
reg1 |= coma_mode[port];
633
636
634
-
pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
635
-
pci_read_config_dword(pdev, PCI_DEV_REG1, ®1);
637
+
sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
638
+
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
636
639
637
640
udelay(100);
638
641
}
···
701
704
sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
702
705
703
706
/* Turn on legacy PCI-Express PME mode */
704
-
pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
707
+
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
705
708
reg1 |= PCI_Y2_PME_LEGACY;
706
-
pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
709
+
sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
707
710
708
711
/* block receiver */
709
712
sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
···
845
848
sky2_set_tx_stfwd(hw, port);
846
849
}
847
850
851
+
if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
852
+
hw->chip_rev == CHIP_REV_YU_FE2_A0) {
853
+
/* disable dynamic watermark */
854
+
reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
855
+
reg &= ~TX_DYN_WM_ENA;
856
+
sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
857
+
}
848
858
}
849
859
850
860
/* Assign Ram Buffer allocation to queue */
···
1324
1320
*/
1325
1321
if (otherdev && netif_running(otherdev) &&
1326
1322
(cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1327
-
struct sky2_port *osky2 = netdev_priv(otherdev);
1328
1323
u16 cmd;
1329
1324
1330
-
pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
1325
+
cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1331
1326
cmd &= ~PCI_X_CMD_MAX_SPLIT;
1332
-
pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
1327
+
sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1333
1328
1334
-
sky2->rx_csum = 0;
1335
-
osky2->rx_csum = 0;
1336
1329
}
1337
1330
1338
1331
if (netif_msg_ifup(sky2))
···
2427
2426
if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2428
2427
u16 pci_err;
2429
2428
2430
-
pci_read_config_word(pdev, PCI_STATUS, &pci_err);
2429
+
pci_err = sky2_pci_read16(hw, PCI_STATUS);
2431
2430
if (net_ratelimit())
2432
2431
dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2433
2432
pci_err);
2434
2433
2435
-
pci_write_config_word(pdev, PCI_STATUS,
2434
+
sky2_pci_write16(hw, PCI_STATUS,
2436
2435
pci_err | PCI_STATUS_ERROR_BITS);
2437
2436
}
2438
2437
2439
2438
if (status & Y2_IS_PCI_EXP) {
2440
2439
/* PCI-Express uncorrectable Error occurred */
2441
-
int aer = pci_find_aer_capability(hw->pdev);
2442
2440
u32 err;
2443
2441
2444
-
if (aer) {
2445
-
pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS,
2446
-
&err);
2447
-
pci_cleanup_aer_uncorrect_error_status(pdev);
2448
-
} else {
2449
-
/* Either AER not configured, or not working
2450
-
* because of bad MMCONFIG, so just do recover
2451
-
* manually.
2452
-
*/
2453
-
err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2454
-
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2455
-
0xfffffffful);
2456
-
}
2457
-
2442
+
err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2443
+
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2444
+
0xfffffffful);
2458
2445
if (net_ratelimit())
2459
2446
dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2460
2447
2448
+
sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2461
2449
}
2462
2450
2463
2451
if (status & Y2_HWE_L1_MASK)
···
2693
2703
2694
2704
static int __devinit sky2_init(struct sky2_hw *hw)
2695
2705
{
2696
-
int rc;
2697
2706
u8 t8;
2698
2707
2699
2708
/* Enable all clocks and check for bad PCI access */
2700
-
rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2701
-
if (rc)
2702
-
return rc;
2709
+
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2703
2710
2704
2711
sky2_write8(hw, B0_CTST, CS_RST_CLR);
2705
2712
···
2793
2806
sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2794
2807
2795
2808
/* clear PCI errors, if any */
2796
-
pci_read_config_word(pdev, PCI_STATUS, &status);
2809
+
status = sky2_pci_read16(hw, PCI_STATUS);
2797
2810
status |= PCI_STATUS_ERROR_BITS;
2798
-
pci_write_config_word(pdev, PCI_STATUS, status);
2811
+
sky2_pci_write16(hw, PCI_STATUS, status);
2799
2812
2800
2813
sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2801
2814
2802
2815
cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2803
2816
if (cap) {
2804
-
if (pci_find_aer_capability(pdev)) {
2805
-
/* Check for advanced error reporting */
2806
-
pci_cleanup_aer_uncorrect_error_status(pdev);
2807
-
pci_cleanup_aer_correct_error_status(pdev);
2808
-
} else {
2809
-
dev_warn(&pdev->dev,
2810
-
"PCI Express Advanced Error Reporting"
2811
-
" not configured or MMCONFIG problem?\n");
2812
-
2813
-
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2814
-
0xfffffffful);
2815
-
}
2817
+
sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2818
+
0xfffffffful);
2816
2819
2817
2820
/* If error bit is stuck on ignore it */
2818
2821
if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2819
2822
dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2820
-
2821
-
else if (pci_enable_pcie_error_reporting(pdev))
2823
+
else
2822
2824
hwe_mask |= Y2_IS_PCI_EXP;
2823
2825
}
2824
2826
···
3648
3672
static int sky2_get_eeprom_len(struct net_device *dev)
3649
3673
{
3650
3674
struct sky2_port *sky2 = netdev_priv(dev);
3675
+
struct sky2_hw *hw = sky2->hw;
3651
3676
u16 reg2;
3652
3677
3653
-
pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, ®2);
3678
+
reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3654
3679
return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3655
3680
}
3656
3681
3657
-
static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
3682
+
static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3658
3683
{
3659
3684
u32 val;
3660
3685
3661
-
pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3686
+
sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3662
3687
3663
3688
do {
3664
-
pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3689
+
offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3665
3690
} while (!(offset & PCI_VPD_ADDR_F));
3666
3691
3667
-
pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3692
+
val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3668
3693
return val;
3669
3694
}
3670
3695
3671
-
static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
3696
+
static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3672
3697
{
3673
-
pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3674
-
pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3698
+
sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3699
+
sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3675
3700
do {
3676
-
pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3701
+
offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3677
3702
} while (offset & PCI_VPD_ADDR_F);
3678
3703
}
3679
3704
···
3692
3715
eeprom->magic = SKY2_EEPROM_MAGIC;
3693
3716
3694
3717
while (length > 0) {
3695
-
u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3718
+
u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3696
3719
int n = min_t(int, length, sizeof(val));
3697
3720
3698
3721
memcpy(data, &val, n);
···
3722
3745
int n = min_t(int, length, sizeof(val));
3723
3746
3724
3747
if (n < sizeof(val))
3725
-
val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3748
+
val = sky2_vpd_read(sky2->hw, cap, offset);
3726
3749
memcpy(&val, data, n);
3727
3750
3728
-
sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
3751
+
sky2_vpd_write(sky2->hw, cap, offset, val);
3729
3752
3730
3753
length -= n;
3731
3754
data += n;
···
3990
4013
sky2->duplex = -1;
3991
4014
sky2->speed = -1;
3992
4015
sky2->advertising = sky2_supported_modes(hw);
3993
-
sky2->rx_csum = 1;
4016
+
sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3994
4017
sky2->wol = wol;
3995
4018
3996
4019
spin_lock_init(&sky2->phy_lock);
···
4161
4184
*/
4162
4185
{
4163
4186
u32 reg;
4164
-
pci_read_config_dword(pdev,PCI_DEV_REG2, ®);
4187
+
reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4165
4188
reg &= ~PCI_REV_DESC;
4166
-
pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4189
+
sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4167
4190
}
4168
4191
#endif
4169
4192
···
4354
4377
if (hw->chip_id == CHIP_ID_YUKON_EX ||
4355
4378
hw->chip_id == CHIP_ID_YUKON_EC_U ||
4356
4379
hw->chip_id == CHIP_ID_YUKON_FE_P)
4357
-
pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4380
+
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4358
4381
4359
4382
sky2_reset(hw);
4360
4383
sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
+21
drivers/net/sky2.h
+21
drivers/net/sky2.h
···
2128
2128
gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2129
2129
gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2130
2130
}
2131
+
2132
+
/* PCI config space access */
2133
+
static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2134
+
{
2135
+
return sky2_read32(hw, Y2_CFG_SPC + reg);
2136
+
}
2137
+
2138
+
static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2139
+
{
2140
+
return sky2_read16(hw, Y2_CFG_SPC + reg);
2141
+
}
2142
+
2143
+
static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2144
+
{
2145
+
sky2_write32(hw, Y2_CFG_SPC + reg, val);
2146
+
}
2147
+
2148
+
static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2149
+
{
2150
+
sky2_write16(hw, Y2_CFG_SPC + reg, val);
2151
+
}
2131
2152
#endif
+5
-14
drivers/net/smc911x.c
+5
-14
drivers/net/smc911x.c
···
428
428
*/
429
429
static inline void smc911x_rcv(struct net_device *dev)
430
430
{
431
-
struct smc911x_local *lp = netdev_priv(dev);
432
431
unsigned long ioaddr = dev->base_addr;
433
432
unsigned int pkt_len, status;
434
433
struct sk_buff *skb;
···
472
473
skb_put(skb,pkt_len-4);
473
474
#ifdef SMC_USE_DMA
474
475
{
476
+
struct smc911x_local *lp = netdev_priv(dev);
475
477
unsigned int fifo;
476
478
/* Lower the FIFO threshold if possible */
477
479
fifo = SMC_GET_FIFO_INT();
···
1379
1379
unsigned int multicast_table[2];
1380
1380
unsigned int mcr, update_multicast = 0;
1381
1381
unsigned long flags;
1382
-
/* table for flipping the order of 5 bits */
1383
-
static const unsigned char invert5[] =
1384
-
{0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0C, 0x1C,
1385
-
0x02, 0x12, 0x0A, 0x1A, 0x06, 0x16, 0x0E, 0x1E,
1386
-
0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0D, 0x1D,
1387
-
0x03, 0x13, 0x0B, 0x1B, 0x07, 0x17, 0x0F, 0x1F};
1388
-
1389
1382
1390
1383
DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1391
1384
···
1425
1432
1426
1433
cur_addr = dev->mc_list;
1427
1434
for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1428
-
int position;
1435
+
u32 position;
1429
1436
1430
1437
/* do we have a pointer here? */
1431
1438
if (!cur_addr)
···
1435
1442
if (!(*cur_addr->dmi_addr & 1))
1436
1443
continue;
1437
1444
1438
-
/* only use the low order bits */
1439
-
position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f;
1445
+
/* upper 6 bits are used as hash index */
1446
+
position = ether_crc(ETH_ALEN, cur_addr->dmi_addr)>>26;
1440
1447
1441
-
/* do some messy swapping to put the bit in the right spot */
1442
-
multicast_table[invert5[position&0x1F]&0x1] |=
1443
-
(1<<invert5[(position>>1)&0x1F]);
1448
+
multicast_table[position>>5] |= 1 << (position&0x1f);
1444
1449
}
1445
1450
1446
1451
/* be sure I get rid of flags I might have set */
+1
-1
drivers/net/smc911x.h
+1
-1
drivers/net/smc911x.h
+1
-1
drivers/net/smc91x.h
+1
-1
drivers/net/smc91x.h
+2
-2
drivers/net/tulip/dmfe.c
+2
-2
drivers/net/tulip/dmfe.c
···
2118
2118
pci_enable_wake(pci_dev, PCI_D3cold, 1);
2119
2119
2120
2120
/* Power down device*/
2121
-
pci_set_power_state(pci_dev, pci_choose_state (pci_dev,state));
2122
2121
pci_save_state(pci_dev);
2122
+
pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2123
2123
2124
2124
return 0;
2125
2125
}
···
2129
2129
struct net_device *dev = pci_get_drvdata(pci_dev);
2130
2130
u32 tmp;
2131
2131
2132
-
pci_restore_state(pci_dev);
2133
2132
pci_set_power_state(pci_dev, PCI_D0);
2133
+
pci_restore_state(pci_dev);
2134
2134
2135
2135
/* Re-initilize DM910X board */
2136
2136
dmfe_init_dm910x(dev);
+10
drivers/net/ucc_geth.c
+10
drivers/net/ucc_geth.c
···
1460
1460
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1461
1461
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1462
1462
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1463
+
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1464
+
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1463
1465
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1464
1466
upsmr |= UPSMR_RPM;
1465
1467
switch (ugeth->max_speed) {
···
1559
1557
if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1560
1558
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1561
1559
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1560
+
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1561
+
(ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1562
1562
(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1563
1563
if (phydev->speed == SPEED_10)
1564
1564
upsmr |= UPSMR_R10M;
···
3799
3795
return PHY_INTERFACE_MODE_RGMII;
3800
3796
if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3801
3797
return PHY_INTERFACE_MODE_RGMII_ID;
3798
+
if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3799
+
return PHY_INTERFACE_MODE_RGMII_TXID;
3800
+
if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3801
+
return PHY_INTERFACE_MODE_RGMII_RXID;
3802
3802
if (strcasecmp(phy_connection_type, "rtbi") == 0)
3803
3803
return PHY_INTERFACE_MODE_RTBI;
3804
3804
···
3897
3889
case PHY_INTERFACE_MODE_GMII:
3898
3890
case PHY_INTERFACE_MODE_RGMII:
3899
3891
case PHY_INTERFACE_MODE_RGMII_ID:
3892
+
case PHY_INTERFACE_MODE_RGMII_RXID:
3893
+
case PHY_INTERFACE_MODE_RGMII_TXID:
3900
3894
case PHY_INTERFACE_MODE_TBI:
3901
3895
case PHY_INTERFACE_MODE_RTBI:
3902
3896
max_speed = SPEED_1000;
+1
-1
drivers/net/usb/dm9601.c
+1
-1
drivers/net/usb/dm9601.c
+3
-8
drivers/net/via-velocity.c
+3
-8
drivers/net/via-velocity.c
···
1242
1242
static int velocity_init_rd_ring(struct velocity_info *vptr)
1243
1243
{
1244
1244
int ret;
1245
+
int mtu = vptr->dev->mtu;
1246
+
1247
+
vptr->rx_buf_sz = (mtu <= ETH_DATA_LEN) ? PKT_BUF_SZ : mtu + 32;
1245
1248
1246
1249
vptr->rd_info = kcalloc(vptr->options.numrx,
1247
1250
sizeof(struct velocity_rd_info), GFP_KERNEL);
···
1901
1898
struct velocity_info *vptr = netdev_priv(dev);
1902
1899
int ret;
1903
1900
1904
-
vptr->rx_buf_sz = (dev->mtu <= 1504 ? PKT_BUF_SZ : dev->mtu + 32);
1905
-
1906
1901
ret = velocity_init_rings(vptr);
1907
1902
if (ret < 0)
1908
1903
goto out;
···
1979
1978
velocity_free_rd_ring(vptr);
1980
1979
1981
1980
dev->mtu = new_mtu;
1982
-
if (new_mtu > 8192)
1983
-
vptr->rx_buf_sz = 9 * 1024;
1984
-
else if (new_mtu > 4096)
1985
-
vptr->rx_buf_sz = 8192;
1986
-
else
1987
-
vptr->rx_buf_sz = 4 * 1024;
1988
1981
1989
1982
ret = velocity_init_rd_ring(vptr);
1990
1983
if (ret < 0)
+1
-1
drivers/net/wireless/b43/main.c
+1
-1
drivers/net/wireless/b43/main.c
···
1566
1566
static void b43_print_fw_helptext(struct b43_wl *wl)
1567
1567
{
1568
1568
b43err(wl, "You must go to "
1569
-
"http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1569
+
"http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1570
1570
"and download the correct firmware (version 4).\n");
1571
1571
}
1572
1572
+1
-1
drivers/net/wireless/b43/phy.c
+1
-1
drivers/net/wireless/b43/phy.c
+1
-1
drivers/net/wireless/b43legacy/dma.c
+1
-1
drivers/net/wireless/b43legacy/dma.c
+1
-1
drivers/net/wireless/b43legacy/main.c
+1
-1
drivers/net/wireless/b43legacy/main.c
···
1419
1419
static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1420
1420
{
1421
1421
b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1422
-
"Drivers/bcm43xx#devicefirmware "
1422
+
"Drivers/b43#devicefirmware "
1423
1423
"and download the correct firmware (version 3).\n");
1424
1424
}
1425
1425
+1
-1
drivers/net/wireless/b43legacy/phy.c
+1
-1
drivers/net/wireless/b43legacy/phy.c
···
2020
2020
phy->idle_tssi = 62;
2021
2021
dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2022
2022
if (dyn_tssi2dbm == NULL) {
2023
-
b43legacyerr(dev->wl, "Could not allocate memory"
2023
+
b43legacyerr(dev->wl, "Could not allocate memory "
2024
2024
"for tssi2dbm table\n");
2025
2025
return -ENOMEM;
2026
2026
}
+1
-1
drivers/net/wireless/bcm43xx/bcm43xx_phy.c
+1
-1
drivers/net/wireless/bcm43xx/bcm43xx_phy.c
+12
-4
drivers/net/wireless/iwlwifi/iwl3945-base.c
+12
-4
drivers/net/wireless/iwlwifi/iwl3945-base.c
···
2915
2915
int i;
2916
2916
2917
2917
hw = iwl_get_hw_mode(priv, priv->phymode);
2918
+
if (!hw) {
2919
+
IWL_ERROR("Failed to set rate: unable to get hw mode\n");
2920
+
return;
2921
+
}
2918
2922
2919
2923
priv->active_rate = 0;
2920
2924
priv->active_rate_basic = 0;
···
6940
6936
DECLARE_MAC_BUF(mac);
6941
6937
6942
6938
IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
6943
-
if (conf->mac_addr)
6944
-
IWL_DEBUG_MAC80211("enter: MAC %s\n",
6945
-
print_mac(mac, conf->mac_addr));
6946
6939
6947
6940
if (priv->interface_id) {
6948
6941
IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
6949
-
return 0;
6942
+
return -EOPNOTSUPP;
6950
6943
}
6951
6944
6952
6945
spin_lock_irqsave(&priv->lock, flags);
···
6952
6951
spin_unlock_irqrestore(&priv->lock, flags);
6953
6952
6954
6953
mutex_lock(&priv->mutex);
6954
+
6955
+
if (conf->mac_addr) {
6956
+
IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
6957
+
memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
6958
+
}
6959
+
6955
6960
iwl_set_mode(priv, conf->type);
6956
6961
6957
6962
IWL_DEBUG_MAC80211("leave\n");
···
8277
8270
{
8278
8271
iwl_hw_cancel_deferred_work(priv);
8279
8272
8273
+
cancel_delayed_work_sync(&priv->init_alive_start);
8280
8274
cancel_delayed_work(&priv->scan_check);
8281
8275
cancel_delayed_work(&priv->alive_start);
8282
8276
cancel_delayed_work(&priv->post_associate);
+10
-3
drivers/net/wireless/iwlwifi/iwl4965-base.c
+10
-3
drivers/net/wireless/iwlwifi/iwl4965-base.c
···
3003
3003
int i;
3004
3004
3005
3005
hw = iwl_get_hw_mode(priv, priv->phymode);
3006
+
if (!hw) {
3007
+
IWL_ERROR("Failed to set rate: unable to get hw mode\n");
3008
+
return;
3009
+
}
3006
3010
3007
3011
priv->active_rate = 0;
3008
3012
priv->active_rate_basic = 0;
···
7330
7326
DECLARE_MAC_BUF(mac);
7331
7327
7332
7328
IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
7333
-
if (conf->mac_addr)
7334
-
IWL_DEBUG_MAC80211("enter: MAC %s\n",
7335
-
print_mac(mac, conf->mac_addr));
7336
7329
7337
7330
if (priv->interface_id) {
7338
7331
IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
···
7342
7341
spin_unlock_irqrestore(&priv->lock, flags);
7343
7342
7344
7343
mutex_lock(&priv->mutex);
7344
+
7345
+
if (conf->mac_addr) {
7346
+
IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr));
7347
+
memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
7348
+
}
7345
7349
iwl_set_mode(priv, conf->type);
7346
7350
7347
7351
IWL_DEBUG_MAC80211("leave\n");
···
8870
8864
{
8871
8865
iwl_hw_cancel_deferred_work(priv);
8872
8866
8867
+
cancel_delayed_work_sync(&priv->init_alive_start);
8873
8868
cancel_delayed_work(&priv->scan_check);
8874
8869
cancel_delayed_work(&priv->alive_start);
8875
8870
cancel_delayed_work(&priv->post_associate);
+2
-1
drivers/net/wireless/libertas/if_cs.c
+2
-1
drivers/net/wireless/libertas/if_cs.c
···
170
170
#define IF_CS_H_IC_TX_OVER 0x0001
171
171
#define IF_CS_H_IC_RX_OVER 0x0002
172
172
#define IF_CS_H_IC_DNLD_OVER 0x0004
173
-
#define IF_CS_H_IC_HOST_EVENT 0x0008
173
+
#define IF_CS_H_IC_POWER_DOWN 0x0008
174
+
#define IF_CS_H_IC_HOST_EVENT 0x0010
174
175
#define IF_CS_H_IC_MASK 0x001f
175
176
176
177
#define IF_CS_H_INT_MASK 0x00000004
-4
drivers/net/wireless/libertas/main.c
-4
drivers/net/wireless/libertas/main.c
···
1165
1165
#ifdef WIRELESS_EXT
1166
1166
dev->wireless_handlers = (struct iw_handler_def *)&libertas_handler_def;
1167
1167
#endif
1168
-
#define NETIF_F_DYNALLOC 16
1169
-
dev->features |= NETIF_F_DYNALLOC;
1170
1168
dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
1171
1169
dev->set_multicast_list = libertas_set_multicast_list;
1172
1170
···
1346
1348
#ifdef WIRELESS_EXT
1347
1349
mesh_dev->wireless_handlers = (struct iw_handler_def *)&mesh_handler_def;
1348
1350
#endif
1349
-
#define NETIF_F_DYNALLOC 16
1350
-
1351
1351
/* Register virtual mesh interface */
1352
1352
ret = register_netdev(mesh_dev);
1353
1353
if (ret) {
+1
-1
drivers/net/wireless/libertas/wext.c
+1
-1
drivers/net/wireless/libertas/wext.c
···
1528
1528
&& (ext->key_len != KEY_LEN_WPA_TKIP))
1529
1529
|| ((alg == IW_ENCODE_ALG_CCMP)
1530
1530
&& (ext->key_len != KEY_LEN_WPA_AES))) {
1531
-
lbs_deb_wext("invalid size %d for key of alg"
1531
+
lbs_deb_wext("invalid size %d for key of alg "
1532
1532
"type %d\n",
1533
1533
ext->key_len,
1534
1534
alg);
+1
-1
drivers/net/wireless/netwave_cs.c
+1
-1
drivers/net/wireless/netwave_cs.c
···
806
806
for (i = 0; i < 6; i++)
807
807
dev->dev_addr[i] = readb(ramBase + NETWAVE_EREG_PA + i);
808
808
809
-
printk(KERN_INFO "%s: Netwave: port %#3lx, irq %d, mem %lx"
809
+
printk(KERN_INFO "%s: Netwave: port %#3lx, irq %d, mem %lx, "
810
810
"id %c%c, hw_addr %s\n",
811
811
dev->name, dev->base_addr, dev->irq,
812
812
(u_long) ramBase,
+1
-1
drivers/net/wireless/p54usb.c
+1
-1
drivers/net/wireless/p54usb.c
+16
-29
drivers/s390/net/ctcmain.c
+16
-29
drivers/s390/net/ctcmain.c
···
2782
2782
}
2783
2783
2784
2784
/**
2785
-
* Initialize everything of the net device except the name and the
2786
-
* channel structs.
2785
+
* Device setup function called by alloc_netdev().
2786
+
*
2787
+
* @param dev Device to be setup.
2787
2788
*/
2788
-
static struct net_device *
2789
-
ctc_init_netdevice(struct net_device * dev, int alloc_device,
2790
-
struct ctc_priv *privptr)
2789
+
void ctc_init_netdevice(struct net_device * dev)
2791
2790
{
2792
-
if (!privptr)
2793
-
return NULL;
2794
-
2795
2791
DBF_TEXT(setup, 3, __FUNCTION__);
2796
2792
2797
-
if (alloc_device) {
2798
-
dev = kzalloc(sizeof(struct net_device), GFP_KERNEL);
2799
-
if (!dev)
2800
-
return NULL;
2801
-
}
2802
-
2803
-
dev->priv = privptr;
2804
-
privptr->fsm = init_fsm("ctcdev", dev_state_names,
2805
-
dev_event_names, CTC_NR_DEV_STATES, CTC_NR_DEV_EVENTS,
2806
-
dev_fsm, DEV_FSM_LEN, GFP_KERNEL);
2807
-
if (privptr->fsm == NULL) {
2808
-
if (alloc_device)
2809
-
kfree(dev);
2810
-
return NULL;
2811
-
}
2812
-
fsm_newstate(privptr->fsm, DEV_STATE_STOPPED);
2813
-
fsm_settimer(privptr->fsm, &privptr->restart_timer);
2814
2793
if (dev->mtu == 0)
2815
2794
dev->mtu = CTC_BUFSIZE_DEFAULT - LL_HEADER_LENGTH - 2;
2816
2795
dev->hard_start_xmit = ctc_tx;
···
2802
2823
dev->type = ARPHRD_SLIP;
2803
2824
dev->tx_queue_len = 100;
2804
2825
dev->flags = IFF_POINTOPOINT | IFF_NOARP;
2805
-
return dev;
2826
+
SET_MODULE_OWNER(dev);
2806
2827
}
2807
2828
2808
2829
···
2858
2879
"ccw_device_set_online (cdev[1]) failed with ret = %d\n", ret);
2859
2880
}
2860
2881
2861
-
dev = ctc_init_netdevice(NULL, 1, privptr);
2862
-
2882
+
dev = alloc_netdev(0, "ctc%d", ctc_init_netdevice);
2863
2883
if (!dev) {
2864
2884
ctc_pr_warn("ctc_init_netdevice failed\n");
2865
2885
goto out;
2866
2886
}
2887
+
dev->priv = privptr;
2867
2888
2868
-
strlcpy(dev->name, "ctc%d", IFNAMSIZ);
2889
+
privptr->fsm = init_fsm("ctcdev", dev_state_names,
2890
+
dev_event_names, CTC_NR_DEV_STATES, CTC_NR_DEV_EVENTS,
2891
+
dev_fsm, DEV_FSM_LEN, GFP_KERNEL);
2892
+
if (privptr->fsm == NULL) {
2893
+
free_netdev(dev);
2894
+
goto out;
2895
+
}
2896
+
fsm_newstate(privptr->fsm, DEV_STATE_STOPPED);
2897
+
fsm_settimer(privptr->fsm, &privptr->restart_timer);
2869
2898
2870
2899
for (direction = READ; direction <= WRITE; direction++) {
2871
2900
privptr->channel[direction] =
+4
include/linux/pci_ids.h
+4
include/linux/pci_ids.h
···
1237
1237
#define PCI_DEVICE_ID_NVIDIA_NVENET_33 0x0761
1238
1238
#define PCI_DEVICE_ID_NVIDIA_NVENET_34 0x0762
1239
1239
#define PCI_DEVICE_ID_NVIDIA_NVENET_35 0x0763
1240
+
#define PCI_DEVICE_ID_NVIDIA_NVENET_36 0x0AB0
1241
+
#define PCI_DEVICE_ID_NVIDIA_NVENET_37 0x0AB1
1242
+
#define PCI_DEVICE_ID_NVIDIA_NVENET_38 0x0AB2
1243
+
#define PCI_DEVICE_ID_NVIDIA_NVENET_39 0x0AB3
1240
1244
1241
1245
#define PCI_VENDOR_ID_IMS 0x10e0
1242
1246
#define PCI_DEVICE_ID_IMS_TT128 0x9128