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amdgpu/jpeg: fix deepsleep register for jpeg 5_0_0 and 5_0_2

PCTL0__MMHUB_DEEPSLEEP_IB is 0x69004 on MMHUB 4,1,0 and
and 0x60804 on MMHUB 4,2,0. 0x62a04 is on MMHUB 1,8,0/1.

The DS bits are adjusted to cover more JPEG engines and MMHUB
version.

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

authored by

David (Ming Qiang) Wu and committed by
Alex Deucher e90dc3b2 ddda81c4

+46 -6
+46 -6
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
··· 736 736 */ 737 737 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 738 738 { 739 - if (!amdgpu_sriov_vf(ring->adev)) { 739 + struct amdgpu_device *adev = ring->adev; 740 + 741 + if (!amdgpu_sriov_vf(adev)) { 742 + int jpeg_inst = GET_INST(JPEG, ring->me); 743 + uint32_t value = 0x80004000; /* default DS14 */ 744 + 740 745 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 741 746 0, 0, PACKETJ_TYPE0)); 742 - amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 747 + 748 + /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ 749 + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 750 + case IP_VERSION(4, 1, 0): 751 + amdgpu_ring_write(ring, 0x69004); 752 + value = 0x80010000; 753 + break; 754 + case IP_VERSION(4, 2, 0): 755 + amdgpu_ring_write(ring, 0x60804); 756 + if (jpeg_inst & 1) 757 + value = 0x80010000; 758 + break; 759 + default: 760 + amdgpu_ring_write(ring, 0x62a04); 761 + break; 762 + } 743 763 744 764 amdgpu_ring_write(ring, 745 765 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 746 766 0, PACKETJ_TYPE0)); 747 - amdgpu_ring_write(ring, 0x80004000); 767 + amdgpu_ring_write(ring, value); 748 768 } 749 769 } 750 770 ··· 777 757 */ 778 758 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 779 759 { 780 - if (!amdgpu_sriov_vf(ring->adev)) { 760 + struct amdgpu_device *adev = ring->adev; 761 + 762 + if (!amdgpu_sriov_vf(adev)) { 763 + int jpeg_inst = GET_INST(JPEG, ring->me); 764 + uint32_t value = 0x00004000; /* default DS14 */ 765 + 781 766 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 782 767 0, 0, PACKETJ_TYPE0)); 783 - amdgpu_ring_write(ring, 0x62a04); 768 + 769 + /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ 770 + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 771 + case IP_VERSION(4, 1, 0): 772 + amdgpu_ring_write(ring, 0x69004); 773 + value = 0x00010000; 774 + break; 775 + case IP_VERSION(4, 2, 0): 776 + amdgpu_ring_write(ring, 0x60804); 777 + if (jpeg_inst & 1) 778 + value = 0x00010000; 779 + break; 780 + default: 781 + amdgpu_ring_write(ring, 0x62a04); 782 + break; 783 + } 784 784 785 785 amdgpu_ring_write(ring, 786 786 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 787 787 0, PACKETJ_TYPE0)); 788 - amdgpu_ring_write(ring, 0x00004000); 788 + amdgpu_ring_write(ring, value); 789 789 } 790 790 } 791 791