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dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml
Convert the mediatek,audsys binding to YAML, together with the associated
binding bindings/sound/mt2701-afe-pcm.yaml .
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
authored by
Eugen Hristev
and committed by
AngeloGioacchino Del Regno
e97c6182
5710462a
+269
-185
-39
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
-39
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
···
1
-
MediaTek AUDSYS controller
2
-
============================
3
-
4
-
The MediaTek AUDSYS controller provides various clocks to the system.
5
-
6
-
Required Properties:
7
-
8
-
- compatible: Should be one of:
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-
- "mediatek,mt2701-audsys", "syscon"
10
-
- "mediatek,mt6765-audsys", "syscon"
11
-
- "mediatek,mt6779-audio", "syscon"
12
-
- "mediatek,mt7622-audsys", "syscon"
13
-
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
14
-
- "mediatek,mt8167-audiosys", "syscon"
15
-
- "mediatek,mt8183-audiosys", "syscon"
16
-
- "mediatek,mt8192-audsys", "syscon"
17
-
- "mediatek,mt8516-audsys", "syscon"
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- #clock-cells: Must be 1
19
-
20
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The AUDSYS controller uses the common clk binding from
21
-
Documentation/devicetree/bindings/clock/clock-bindings.txt
22
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
23
-
24
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Required sub-nodes:
25
-
-------
26
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For common binding part and usage, refer to
27
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../sonud/mt2701-afe-pcm.txt.
28
-
29
-
Example:
30
-
31
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt7622-audsys", "syscon";
33
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reg = <0 0x11220000 0 0x2000>;
34
-
#clock-cells = <1>;
35
-
36
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afe: audio-controller {
37
-
...
38
-
};
39
-
};
+153
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
+153
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek AUDSYS controller
8
+
9
+
maintainers:
10
+
- Eugen Hristev <eugen.hristev@collabora.com>
11
+
12
+
description:
13
+
The MediaTek AUDSYS controller provides various clocks to the system.
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- mediatek,mt2701-audsys
21
+
- mediatek,mt6765-audsys
22
+
- mediatek,mt6779-audsys
23
+
- mediatek,mt7622-audsys
24
+
- mediatek,mt8167-audsys
25
+
- mediatek,mt8173-audsys
26
+
- mediatek,mt8183-audsys
27
+
- mediatek,mt8186-audsys
28
+
- mediatek,mt8192-audsys
29
+
- mediatek,mt8516-audsys
30
+
- const: syscon
31
+
- items:
32
+
# Special case for mt7623 for backward compatibility
33
+
- const: mediatek,mt7623-audsys
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+
- const: mediatek,mt2701-audsys
35
+
- const: syscon
36
+
37
+
reg:
38
+
maxItems: 1
39
+
40
+
'#clock-cells':
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+
const: 1
42
+
43
+
audio-controller:
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$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
45
+
type: object
46
+
47
+
required:
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+
- compatible
49
+
- '#clock-cells'
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
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+
- |
55
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
56
+
#include <dt-bindings/interrupt-controller/irq.h>
57
+
#include <dt-bindings/power/mt2701-power.h>
58
+
#include <dt-bindings/clock/mt2701-clk.h>
59
+
soc {
60
+
#address-cells = <2>;
61
+
#size-cells = <2>;
62
+
audsys: clock-controller@11220000 {
63
+
compatible = "mediatek,mt7622-audsys", "syscon";
64
+
reg = <0 0x11220000 0 0x2000>;
65
+
#clock-cells = <1>;
66
+
67
+
afe: audio-controller {
68
+
compatible = "mediatek,mt2701-audio";
69
+
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
70
+
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
71
+
interrupt-names = "afe", "asys";
72
+
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
73
+
74
+
clocks = <&infracfg CLK_INFRA_AUDIO>,
75
+
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
76
+
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
77
+
<&topckgen CLK_TOP_AUD_48K_TIMING>,
78
+
<&topckgen CLK_TOP_AUD_44K_TIMING>,
79
+
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
80
+
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
81
+
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
82
+
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
83
+
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
84
+
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
85
+
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
86
+
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
87
+
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
88
+
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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+
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
90
+
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
91
+
<&audsys CLK_AUD_I2SO1>,
92
+
<&audsys CLK_AUD_I2SO2>,
93
+
<&audsys CLK_AUD_I2SO3>,
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+
<&audsys CLK_AUD_I2SO4>,
95
+
<&audsys CLK_AUD_I2SIN1>,
96
+
<&audsys CLK_AUD_I2SIN2>,
97
+
<&audsys CLK_AUD_I2SIN3>,
98
+
<&audsys CLK_AUD_I2SIN4>,
99
+
<&audsys CLK_AUD_ASRCO1>,
100
+
<&audsys CLK_AUD_ASRCO2>,
101
+
<&audsys CLK_AUD_ASRCO3>,
102
+
<&audsys CLK_AUD_ASRCO4>,
103
+
<&audsys CLK_AUD_AFE>,
104
+
<&audsys CLK_AUD_AFE_CONN>,
105
+
<&audsys CLK_AUD_A1SYS>,
106
+
<&audsys CLK_AUD_A2SYS>,
107
+
<&audsys CLK_AUD_AFE_MRGIF>;
108
+
109
+
clock-names = "infra_sys_audio_clk",
110
+
"top_audio_mux1_sel",
111
+
"top_audio_mux2_sel",
112
+
"top_audio_a1sys_hp",
113
+
"top_audio_a2sys_hp",
114
+
"i2s0_src_sel",
115
+
"i2s1_src_sel",
116
+
"i2s2_src_sel",
117
+
"i2s3_src_sel",
118
+
"i2s0_src_div",
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+
"i2s1_src_div",
120
+
"i2s2_src_div",
121
+
"i2s3_src_div",
122
+
"i2s0_mclk_en",
123
+
"i2s1_mclk_en",
124
+
"i2s2_mclk_en",
125
+
"i2s3_mclk_en",
126
+
"i2so0_hop_ck",
127
+
"i2so1_hop_ck",
128
+
"i2so2_hop_ck",
129
+
"i2so3_hop_ck",
130
+
"i2si0_hop_ck",
131
+
"i2si1_hop_ck",
132
+
"i2si2_hop_ck",
133
+
"i2si3_hop_ck",
134
+
"asrc0_out_ck",
135
+
"asrc1_out_ck",
136
+
"asrc2_out_ck",
137
+
"asrc3_out_ck",
138
+
"audio_afe_pd",
139
+
"audio_afe_conn_pd",
140
+
"audio_a1sys_pd",
141
+
"audio_a2sys_pd",
142
+
"audio_mrgif_pd";
143
+
144
+
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
145
+
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
146
+
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
147
+
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
148
+
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
149
+
<&topckgen CLK_TOP_AUD2PLL_90M>;
150
+
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
151
+
};
152
+
};
153
+
};
+116
Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml
+116
Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek Audio Front End (AFE) PCM controller for mt2701
8
+
9
+
description:
10
+
The AFE PCM node must be a subnode of the MediaTek audsys device tree node.
11
+
12
+
maintainers:
13
+
- Eugen Hristev <eugen.hristev@collabora.com>
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- mediatek,mt2701-audio
19
+
- mediatek,mt7622-audio
20
+
21
+
interrupts:
22
+
items:
23
+
- description: AFE interrupt
24
+
- description: ASYS interrupt
25
+
26
+
interrupt-names:
27
+
items:
28
+
- const: afe
29
+
- const: asys
30
+
31
+
power-domains:
32
+
maxItems: 1
33
+
34
+
clocks:
35
+
items:
36
+
- description: audio infra sys clock
37
+
- description: top audio mux 1
38
+
- description: top audio mux 2
39
+
- description: top audio sys a1 clock
40
+
- description: top audio sys a2 clock
41
+
- description: i2s0 source selection
42
+
- description: i2s1 source selection
43
+
- description: i2s2 source selection
44
+
- description: i2s3 source selection
45
+
- description: i2s0 source divider
46
+
- description: i2s1 source divider
47
+
- description: i2s2 source divider
48
+
- description: i2s3 source divider
49
+
- description: i2s0 master clock
50
+
- description: i2s1 master clock
51
+
- description: i2s2 master clock
52
+
- description: i2s3 master clock
53
+
- description: i2so0 hopping clock
54
+
- description: i2so1 hopping clock
55
+
- description: i2so2 hopping clock
56
+
- description: i2so3 hopping clock
57
+
- description: i2si0 hopping clock
58
+
- description: i2si1 hopping clock
59
+
- description: i2si2 hopping clock
60
+
- description: i2si3 hopping clock
61
+
- description: asrc0 output clock
62
+
- description: asrc1 output clock
63
+
- description: asrc2 output clock
64
+
- description: asrc3 output clock
65
+
- description: audio front end pd clock
66
+
- description: audio front end conn pd clock
67
+
- description: top audio a1 sys pd
68
+
- description: top audio a2 sys pd
69
+
- description: audio merge interface pd
70
+
71
+
clock-names:
72
+
items:
73
+
- const: infra_sys_audio_clk
74
+
- const: top_audio_mux1_sel
75
+
- const: top_audio_mux2_sel
76
+
- const: top_audio_a1sys_hp
77
+
- const: top_audio_a2sys_hp
78
+
- const: i2s0_src_sel
79
+
- const: i2s1_src_sel
80
+
- const: i2s2_src_sel
81
+
- const: i2s3_src_sel
82
+
- const: i2s0_src_div
83
+
- const: i2s1_src_div
84
+
- const: i2s2_src_div
85
+
- const: i2s3_src_div
86
+
- const: i2s0_mclk_en
87
+
- const: i2s1_mclk_en
88
+
- const: i2s2_mclk_en
89
+
- const: i2s3_mclk_en
90
+
- const: i2so0_hop_ck
91
+
- const: i2so1_hop_ck
92
+
- const: i2so2_hop_ck
93
+
- const: i2so3_hop_ck
94
+
- const: i2si0_hop_ck
95
+
- const: i2si1_hop_ck
96
+
- const: i2si2_hop_ck
97
+
- const: i2si3_hop_ck
98
+
- const: asrc0_out_ck
99
+
- const: asrc1_out_ck
100
+
- const: asrc2_out_ck
101
+
- const: asrc3_out_ck
102
+
- const: audio_afe_pd
103
+
- const: audio_afe_conn_pd
104
+
- const: audio_a1sys_pd
105
+
- const: audio_a2sys_pd
106
+
- const: audio_mrgif_pd
107
+
108
+
required:
109
+
- compatible
110
+
- interrupts
111
+
- interrupt-names
112
+
- power-domains
113
+
- clocks
114
+
- clock-names
115
+
116
+
additionalProperties: false
-146
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
-146
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
···
1
-
Mediatek AFE PCM controller for mt2701
2
-
3
-
Required properties:
4
-
- compatible: should be one of the following.
5
-
- "mediatek,mt2701-audio"
6
-
- "mediatek,mt7622-audio"
7
-
- interrupts: should contain AFE and ASYS interrupts
8
-
- interrupt-names: should be "afe" and "asys"
9
-
- power-domains: should define the power domain
10
-
- clocks: Must contain an entry for each entry in clock-names
11
-
See ../clocks/clock-bindings.txt for details
12
-
- clock-names: should have these clock names:
13
-
"infra_sys_audio_clk",
14
-
"top_audio_mux1_sel",
15
-
"top_audio_mux2_sel",
16
-
"top_audio_a1sys_hp",
17
-
"top_audio_a2sys_hp",
18
-
"i2s0_src_sel",
19
-
"i2s1_src_sel",
20
-
"i2s2_src_sel",
21
-
"i2s3_src_sel",
22
-
"i2s0_src_div",
23
-
"i2s1_src_div",
24
-
"i2s2_src_div",
25
-
"i2s3_src_div",
26
-
"i2s0_mclk_en",
27
-
"i2s1_mclk_en",
28
-
"i2s2_mclk_en",
29
-
"i2s3_mclk_en",
30
-
"i2so0_hop_ck",
31
-
"i2so1_hop_ck",
32
-
"i2so2_hop_ck",
33
-
"i2so3_hop_ck",
34
-
"i2si0_hop_ck",
35
-
"i2si1_hop_ck",
36
-
"i2si2_hop_ck",
37
-
"i2si3_hop_ck",
38
-
"asrc0_out_ck",
39
-
"asrc1_out_ck",
40
-
"asrc2_out_ck",
41
-
"asrc3_out_ck",
42
-
"audio_afe_pd",
43
-
"audio_afe_conn_pd",
44
-
"audio_a1sys_pd",
45
-
"audio_a2sys_pd",
46
-
"audio_mrgif_pd";
47
-
- assigned-clocks: list of input clocks and dividers for the audio system.
48
-
See ../clocks/clock-bindings.txt for details.
49
-
- assigned-clocks-parents: parent of input clocks of assigned clocks.
50
-
- assigned-clock-rates: list of clock frequencies of assigned clocks.
51
-
52
-
Must be a subnode of MediaTek audsys device tree node.
53
-
See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
54
-
55
-
Example:
56
-
57
-
audsys: audio-subsystem@11220000 {
58
-
compatible = "mediatek,mt2701-audsys", "syscon";
59
-
...
60
-
61
-
afe: audio-controller {
62
-
compatible = "mediatek,mt2701-audio";
63
-
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
64
-
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
65
-
interrupt-names = "afe", "asys";
66
-
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
67
-
68
-
clocks = <&infracfg CLK_INFRA_AUDIO>,
69
-
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
70
-
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
71
-
<&topckgen CLK_TOP_AUD_48K_TIMING>,
72
-
<&topckgen CLK_TOP_AUD_44K_TIMING>,
73
-
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74
-
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75
-
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76
-
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77
-
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78
-
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
79
-
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
80
-
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
81
-
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
82
-
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
83
-
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
84
-
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
85
-
<&audsys CLK_AUD_I2SO1>,
86
-
<&audsys CLK_AUD_I2SO2>,
87
-
<&audsys CLK_AUD_I2SO3>,
88
-
<&audsys CLK_AUD_I2SO4>,
89
-
<&audsys CLK_AUD_I2SIN1>,
90
-
<&audsys CLK_AUD_I2SIN2>,
91
-
<&audsys CLK_AUD_I2SIN3>,
92
-
<&audsys CLK_AUD_I2SIN4>,
93
-
<&audsys CLK_AUD_ASRCO1>,
94
-
<&audsys CLK_AUD_ASRCO2>,
95
-
<&audsys CLK_AUD_ASRCO3>,
96
-
<&audsys CLK_AUD_ASRCO4>,
97
-
<&audsys CLK_AUD_AFE>,
98
-
<&audsys CLK_AUD_AFE_CONN>,
99
-
<&audsys CLK_AUD_A1SYS>,
100
-
<&audsys CLK_AUD_A2SYS>,
101
-
<&audsys CLK_AUD_AFE_MRGIF>;
102
-
103
-
clock-names = "infra_sys_audio_clk",
104
-
"top_audio_mux1_sel",
105
-
"top_audio_mux2_sel",
106
-
"top_audio_a1sys_hp",
107
-
"top_audio_a2sys_hp",
108
-
"i2s0_src_sel",
109
-
"i2s1_src_sel",
110
-
"i2s2_src_sel",
111
-
"i2s3_src_sel",
112
-
"i2s0_src_div",
113
-
"i2s1_src_div",
114
-
"i2s2_src_div",
115
-
"i2s3_src_div",
116
-
"i2s0_mclk_en",
117
-
"i2s1_mclk_en",
118
-
"i2s2_mclk_en",
119
-
"i2s3_mclk_en",
120
-
"i2so0_hop_ck",
121
-
"i2so1_hop_ck",
122
-
"i2so2_hop_ck",
123
-
"i2so3_hop_ck",
124
-
"i2si0_hop_ck",
125
-
"i2si1_hop_ck",
126
-
"i2si2_hop_ck",
127
-
"i2si3_hop_ck",
128
-
"asrc0_out_ck",
129
-
"asrc1_out_ck",
130
-
"asrc2_out_ck",
131
-
"asrc3_out_ck",
132
-
"audio_afe_pd",
133
-
"audio_afe_conn_pd",
134
-
"audio_a1sys_pd",
135
-
"audio_a2sys_pd",
136
-
"audio_mrgif_pd";
137
-
138
-
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
139
-
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
140
-
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
141
-
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
142
-
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
143
-
<&topckgen CLK_TOP_AUD2PLL_90M>;
144
-
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
145
-
};
146
-
};