tjh.dev / kernel
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crypto: qat - add get_svc_slice_cnt() in device data structure

Enhance the adf_hw_device_data structure by introducing a new callback
function get_svc_slice_cnt(), which provides a mechanism to query the
total number of accelerator available on the device for a specific
service.

Implement adf_gen4_get_svc_slice_cnt() for QAT GEN4 devices to support this
new interface. This function returns the total accelerator count for a
specific service.

Co-developed-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: George Abraham P <george.abraham.p@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Suman Kumar Chakraborty and committed by
Herbert Xu e983946d a9552153

+26 -14
+1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
··· 468 468 hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE; 469 469 hw_data->clock_frequency = ADF_420XX_AE_FREQ; 470 470 hw_data->services_supported = adf_gen4_services_supported; 471 + hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt; 471 472 472 473 adf_gen4_set_err_mask(&hw_data->dev_err_mask); 473 474 adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
+1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
··· 462 462 hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE; 463 463 hw_data->clock_frequency = ADF_4XXX_AE_FREQ; 464 464 hw_data->services_supported = adf_gen4_services_supported; 465 + hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt; 465 466 466 467 adf_gen4_set_err_mask(&hw_data->dev_err_mask); 467 468 adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
+2
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
··· 319 319 u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num); 320 320 int (*dev_config)(struct adf_accel_dev *accel_dev); 321 321 bool (*services_supported)(unsigned long mask); 322 + u32 (*get_svc_slice_cnt)(struct adf_accel_dev *accel_dev, 323 + enum adf_base_services svc); 322 324 struct adf_pfvf_ops pfvf_ops; 323 325 struct adf_hw_csr_ops csr_ops; 324 326 struct adf_dc_ops dc_ops;
+18
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
··· 580 580 device_data->svc_ae_mask[SVC_DECOMP] = 0; 581 581 } 582 582 EXPORT_SYMBOL_GPL(adf_gen4_init_num_svc_aes); 583 + 584 + u32 adf_gen4_get_svc_slice_cnt(struct adf_accel_dev *accel_dev, 585 + enum adf_base_services svc) 586 + { 587 + struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data; 588 + 589 + switch (svc) { 590 + case SVC_SYM: 591 + return device_data->slices.cph_cnt; 592 + case SVC_ASYM: 593 + return device_data->slices.pke_cnt; 594 + case SVC_DC: 595 + return device_data->slices.dcpr_cnt; 596 + default: 597 + return 0; 598 + } 599 + } 600 + EXPORT_SYMBOL_GPL(adf_gen4_get_svc_slice_cnt);
+2
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
··· 176 176 bool adf_gen4_services_supported(unsigned long service_mask); 177 177 void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops); 178 178 void adf_gen4_init_num_svc_aes(struct adf_rl_hw_data *device_data); 179 + u32 adf_gen4_get_svc_slice_cnt(struct adf_accel_dev *accel_dev, 180 + enum adf_base_services svc); 179 181 180 182 #endif
+2 -14
drivers/crypto/intel/qat/qat_common/adf_rl.c
··· 529 529 if (!sla_val) 530 530 return 0; 531 531 532 + /* Handle generation specific slice count adjustment */ 532 533 avail_slice_cycles = hw_data->clock_frequency; 533 - 534 - switch (svc_type) { 535 - case SVC_ASYM: 536 - avail_slice_cycles *= device_data->slices.pke_cnt; 537 - break; 538 - case SVC_SYM: 539 - avail_slice_cycles *= device_data->slices.cph_cnt; 540 - break; 541 - case SVC_DC: 542 - avail_slice_cycles *= device_data->slices.dcpr_cnt; 543 - break; 544 - default: 545 - break; 546 - } 534 + avail_slice_cycles *= hw_data->get_svc_slice_cnt(accel_dev, svc_type); 547 535 548 536 do_div(avail_slice_cycles, device_data->scan_interval); 549 537 allocated_tokens = avail_slice_cycles * sla_val;