tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents

Don't rely on the programmer to enter the name of array elements, since the
computer can compute it with much less chance of making a mistake.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-9-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Konrad Dybcio and committed by
Stephen Boyd eb2d5058 c09b8023

+48 -48
+48 -48
drivers/clk/qcom/gcc-msm8994.c
··· 162 162 .clkr.hw.init = &(struct clk_init_data){ 163 163 .name = "ufs_axi_clk_src", 164 164 .parent_data = gcc_xo_gpll0, 165 - .num_parents = 2, 165 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 166 166 .ops = &clk_rcg2_ops, 167 167 }, 168 168 }; ··· 182 182 .clkr.hw.init = &(struct clk_init_data){ 183 183 .name = "usb30_master_clk_src", 184 184 .parent_data = gcc_xo_gpll0, 185 - .num_parents = 2, 185 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 186 186 .ops = &clk_rcg2_ops, 187 187 }, 188 188 }; ··· 201 201 .clkr.hw.init = &(struct clk_init_data){ 202 202 .name = "blsp1_qup1_i2c_apps_clk_src", 203 203 .parent_data = gcc_xo_gpll0, 204 - .num_parents = 2, 204 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 205 205 .ops = &clk_rcg2_ops, 206 206 }, 207 207 }; ··· 239 239 .clkr.hw.init = &(struct clk_init_data){ 240 240 .name = "blsp1_qup1_spi_apps_clk_src", 241 241 .parent_data = gcc_xo_gpll0, 242 - .num_parents = 2, 242 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 243 243 .ops = &clk_rcg2_ops, 244 244 }, 245 245 }; ··· 252 252 .clkr.hw.init = &(struct clk_init_data){ 253 253 .name = "blsp1_qup2_i2c_apps_clk_src", 254 254 .parent_data = gcc_xo_gpll0, 255 - .num_parents = 2, 255 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 256 256 .ops = &clk_rcg2_ops, 257 257 }, 258 258 }; ··· 279 279 .clkr.hw.init = &(struct clk_init_data){ 280 280 .name = "blsp1_qup2_spi_apps_clk_src", 281 281 .parent_data = gcc_xo_gpll0, 282 - .num_parents = 2, 282 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 283 283 .ops = &clk_rcg2_ops, 284 284 }, 285 285 }; ··· 292 292 .clkr.hw.init = &(struct clk_init_data){ 293 293 .name = "blsp1_qup3_i2c_apps_clk_src", 294 294 .parent_data = gcc_xo_gpll0, 295 - .num_parents = 2, 295 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 296 296 .ops = &clk_rcg2_ops, 297 297 }, 298 298 }; ··· 319 319 .clkr.hw.init = &(struct clk_init_data){ 320 320 .name = "blsp1_qup3_spi_apps_clk_src", 321 321 .parent_data = gcc_xo_gpll0, 322 - .num_parents = 2, 322 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 323 323 .ops = &clk_rcg2_ops, 324 324 }, 325 325 }; ··· 332 332 .clkr.hw.init = &(struct clk_init_data){ 333 333 .name = "blsp1_qup4_i2c_apps_clk_src", 334 334 .parent_data = gcc_xo_gpll0, 335 - .num_parents = 2, 335 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 336 336 .ops = &clk_rcg2_ops, 337 337 }, 338 338 }; ··· 346 346 .clkr.hw.init = &(struct clk_init_data){ 347 347 .name = "blsp1_qup4_spi_apps_clk_src", 348 348 .parent_data = gcc_xo_gpll0, 349 - .num_parents = 2, 349 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 350 350 .ops = &clk_rcg2_ops, 351 351 }, 352 352 }; ··· 359 359 .clkr.hw.init = &(struct clk_init_data){ 360 360 .name = "blsp1_qup5_i2c_apps_clk_src", 361 361 .parent_data = gcc_xo_gpll0, 362 - .num_parents = 2, 362 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 363 363 .ops = &clk_rcg2_ops, 364 364 }, 365 365 }; ··· 386 386 .clkr.hw.init = &(struct clk_init_data){ 387 387 .name = "blsp1_qup5_spi_apps_clk_src", 388 388 .parent_data = gcc_xo_gpll0, 389 - .num_parents = 2, 389 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 390 390 .ops = &clk_rcg2_ops, 391 391 }, 392 392 }; ··· 399 399 .clkr.hw.init = &(struct clk_init_data){ 400 400 .name = "blsp1_qup6_i2c_apps_clk_src", 401 401 .parent_data = gcc_xo_gpll0, 402 - .num_parents = 2, 402 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 403 403 .ops = &clk_rcg2_ops, 404 404 }, 405 405 }; ··· 426 426 .clkr.hw.init = &(struct clk_init_data){ 427 427 .name = "blsp1_qup6_spi_apps_clk_src", 428 428 .parent_data = gcc_xo_gpll0, 429 - .num_parents = 2, 429 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 430 430 .ops = &clk_rcg2_ops, 431 431 }, 432 432 }; ··· 459 459 .clkr.hw.init = &(struct clk_init_data){ 460 460 .name = "blsp1_uart1_apps_clk_src", 461 461 .parent_data = gcc_xo_gpll0, 462 - .num_parents = 2, 462 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 463 463 .ops = &clk_rcg2_ops, 464 464 }, 465 465 }; ··· 473 473 .clkr.hw.init = &(struct clk_init_data){ 474 474 .name = "blsp1_uart2_apps_clk_src", 475 475 .parent_data = gcc_xo_gpll0, 476 - .num_parents = 2, 476 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 477 477 .ops = &clk_rcg2_ops, 478 478 }, 479 479 }; ··· 487 487 .clkr.hw.init = &(struct clk_init_data){ 488 488 .name = "blsp1_uart3_apps_clk_src", 489 489 .parent_data = gcc_xo_gpll0, 490 - .num_parents = 2, 490 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 491 491 .ops = &clk_rcg2_ops, 492 492 }, 493 493 }; ··· 501 501 .clkr.hw.init = &(struct clk_init_data){ 502 502 .name = "blsp1_uart4_apps_clk_src", 503 503 .parent_data = gcc_xo_gpll0, 504 - .num_parents = 2, 504 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 505 505 .ops = &clk_rcg2_ops, 506 506 }, 507 507 }; ··· 515 515 .clkr.hw.init = &(struct clk_init_data){ 516 516 .name = "blsp1_uart5_apps_clk_src", 517 517 .parent_data = gcc_xo_gpll0, 518 - .num_parents = 2, 518 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 519 519 .ops = &clk_rcg2_ops, 520 520 }, 521 521 }; ··· 529 529 .clkr.hw.init = &(struct clk_init_data){ 530 530 .name = "blsp1_uart6_apps_clk_src", 531 531 .parent_data = gcc_xo_gpll0, 532 - .num_parents = 2, 532 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 533 533 .ops = &clk_rcg2_ops, 534 534 }, 535 535 }; ··· 542 542 .clkr.hw.init = &(struct clk_init_data){ 543 543 .name = "blsp2_qup1_i2c_apps_clk_src", 544 544 .parent_data = gcc_xo_gpll0, 545 - .num_parents = 2, 545 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 546 546 .ops = &clk_rcg2_ops, 547 547 }, 548 548 }; ··· 569 569 .clkr.hw.init = &(struct clk_init_data){ 570 570 .name = "blsp2_qup1_spi_apps_clk_src", 571 571 .parent_data = gcc_xo_gpll0, 572 - .num_parents = 2, 572 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 573 573 .ops = &clk_rcg2_ops, 574 574 }, 575 575 }; ··· 582 582 .clkr.hw.init = &(struct clk_init_data){ 583 583 .name = "blsp2_qup2_i2c_apps_clk_src", 584 584 .parent_data = gcc_xo_gpll0, 585 - .num_parents = 2, 585 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 586 586 .ops = &clk_rcg2_ops, 587 587 }, 588 588 }; ··· 596 596 .clkr.hw.init = &(struct clk_init_data){ 597 597 .name = "blsp2_qup2_spi_apps_clk_src", 598 598 .parent_data = gcc_xo_gpll0, 599 - .num_parents = 2, 599 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 600 600 .ops = &clk_rcg2_ops, 601 601 }, 602 602 }; ··· 622 622 .clkr.hw.init = &(struct clk_init_data){ 623 623 .name = "blsp2_qup3_i2c_apps_clk_src", 624 624 .parent_data = gcc_xo_gpll0, 625 - .num_parents = 2, 625 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 626 626 .ops = &clk_rcg2_ops, 627 627 }, 628 628 }; ··· 636 636 .clkr.hw.init = &(struct clk_init_data){ 637 637 .name = "blsp2_qup3_spi_apps_clk_src", 638 638 .parent_data = gcc_xo_gpll0, 639 - .num_parents = 2, 639 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 640 640 .ops = &clk_rcg2_ops, 641 641 }, 642 642 }; ··· 649 649 .clkr.hw.init = &(struct clk_init_data){ 650 650 .name = "blsp2_qup4_i2c_apps_clk_src", 651 651 .parent_data = gcc_xo_gpll0, 652 - .num_parents = 2, 652 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 653 653 .ops = &clk_rcg2_ops, 654 654 }, 655 655 }; ··· 663 663 .clkr.hw.init = &(struct clk_init_data){ 664 664 .name = "blsp2_qup4_spi_apps_clk_src", 665 665 .parent_data = gcc_xo_gpll0, 666 - .num_parents = 2, 666 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 667 667 .ops = &clk_rcg2_ops, 668 668 }, 669 669 }; ··· 676 676 .clkr.hw.init = &(struct clk_init_data){ 677 677 .name = "blsp2_qup5_i2c_apps_clk_src", 678 678 .parent_data = gcc_xo_gpll0, 679 - .num_parents = 2, 679 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 680 680 .ops = &clk_rcg2_ops, 681 681 }, 682 682 }; ··· 691 691 .clkr.hw.init = &(struct clk_init_data){ 692 692 .name = "blsp2_qup5_spi_apps_clk_src", 693 693 .parent_data = gcc_xo_gpll0, 694 - .num_parents = 2, 694 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 695 695 .ops = &clk_rcg2_ops, 696 696 }, 697 697 }; ··· 704 704 .clkr.hw.init = &(struct clk_init_data){ 705 705 .name = "blsp2_qup6_i2c_apps_clk_src", 706 706 .parent_data = gcc_xo_gpll0, 707 - .num_parents = 2, 707 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 708 708 .ops = &clk_rcg2_ops, 709 709 }, 710 710 }; ··· 731 731 .clkr.hw.init = &(struct clk_init_data){ 732 732 .name = "blsp2_qup6_spi_apps_clk_src", 733 733 .parent_data = gcc_xo_gpll0, 734 - .num_parents = 2, 734 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 735 735 .ops = &clk_rcg2_ops, 736 736 }, 737 737 }; ··· 745 745 .clkr.hw.init = &(struct clk_init_data){ 746 746 .name = "blsp2_uart1_apps_clk_src", 747 747 .parent_data = gcc_xo_gpll0, 748 - .num_parents = 2, 748 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 749 749 .ops = &clk_rcg2_ops, 750 750 }, 751 751 }; ··· 759 759 .clkr.hw.init = &(struct clk_init_data){ 760 760 .name = "blsp2_uart2_apps_clk_src", 761 761 .parent_data = gcc_xo_gpll0, 762 - .num_parents = 2, 762 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 763 763 .ops = &clk_rcg2_ops, 764 764 }, 765 765 }; ··· 773 773 .clkr.hw.init = &(struct clk_init_data){ 774 774 .name = "blsp2_uart3_apps_clk_src", 775 775 .parent_data = gcc_xo_gpll0, 776 - .num_parents = 2, 776 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 777 777 .ops = &clk_rcg2_ops, 778 778 }, 779 779 }; ··· 787 787 .clkr.hw.init = &(struct clk_init_data){ 788 788 .name = "blsp2_uart4_apps_clk_src", 789 789 .parent_data = gcc_xo_gpll0, 790 - .num_parents = 2, 790 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 791 791 .ops = &clk_rcg2_ops, 792 792 }, 793 793 }; ··· 801 801 .clkr.hw.init = &(struct clk_init_data){ 802 802 .name = "blsp2_uart5_apps_clk_src", 803 803 .parent_data = gcc_xo_gpll0, 804 - .num_parents = 2, 804 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 805 805 .ops = &clk_rcg2_ops, 806 806 }, 807 807 }; ··· 815 815 .clkr.hw.init = &(struct clk_init_data){ 816 816 .name = "blsp2_uart6_apps_clk_src", 817 817 .parent_data = gcc_xo_gpll0, 818 - .num_parents = 2, 818 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 819 819 .ops = &clk_rcg2_ops, 820 820 }, 821 821 }; ··· 836 836 .clkr.hw.init = &(struct clk_init_data){ 837 837 .name = "gp1_clk_src", 838 838 .parent_data = gcc_xo_gpll0, 839 - .num_parents = 2, 839 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 840 840 .ops = &clk_rcg2_ops, 841 841 }, 842 842 }; ··· 857 857 .clkr.hw.init = &(struct clk_init_data){ 858 858 .name = "gp2_clk_src", 859 859 .parent_data = gcc_xo_gpll0, 860 - .num_parents = 2, 860 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 861 861 .ops = &clk_rcg2_ops, 862 862 }, 863 863 }; ··· 878 878 .clkr.hw.init = &(struct clk_init_data){ 879 879 .name = "gp3_clk_src", 880 880 .parent_data = gcc_xo_gpll0, 881 - .num_parents = 2, 881 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 882 882 .ops = &clk_rcg2_ops, 883 883 }, 884 884 }; ··· 969 969 .clkr.hw.init = &(struct clk_init_data){ 970 970 .name = "pdm2_clk_src", 971 971 .parent_data = gcc_xo_gpll0, 972 - .num_parents = 2, 972 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 973 973 .ops = &clk_rcg2_ops, 974 974 }, 975 975 }; ··· 1007 1007 .clkr.hw.init = &(struct clk_init_data){ 1008 1008 .name = "sdcc1_apps_clk_src", 1009 1009 .parent_data = gcc_xo_gpll0_gpll4, 1010 - .num_parents = 3, 1010 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), 1011 1011 .ops = &clk_rcg2_floor_ops, 1012 1012 }, 1013 1013 }; ··· 1032 1032 .clkr.hw.init = &(struct clk_init_data){ 1033 1033 .name = "sdcc2_apps_clk_src", 1034 1034 .parent_data = gcc_xo_gpll0, 1035 - .num_parents = 2, 1035 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1036 1036 .ops = &clk_rcg2_floor_ops, 1037 1037 }, 1038 1038 }; ··· 1046 1046 .clkr.hw.init = &(struct clk_init_data){ 1047 1047 .name = "sdcc3_apps_clk_src", 1048 1048 .parent_data = gcc_xo_gpll0, 1049 - .num_parents = 2, 1049 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1050 1050 .ops = &clk_rcg2_floor_ops, 1051 1051 }, 1052 1052 }; ··· 1060 1060 .clkr.hw.init = &(struct clk_init_data){ 1061 1061 .name = "sdcc4_apps_clk_src", 1062 1062 .parent_data = gcc_xo_gpll0, 1063 - .num_parents = 2, 1063 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1064 1064 .ops = &clk_rcg2_floor_ops, 1065 1065 }, 1066 1066 }; ··· 1099 1099 .clkr.hw.init = &(struct clk_init_data){ 1100 1100 .name = "usb30_mock_utmi_clk_src", 1101 1101 .parent_data = gcc_xo_gpll0, 1102 - .num_parents = 2, 1102 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1103 1103 .ops = &clk_rcg2_ops, 1104 1104 }, 1105 1105 }; ··· 1136 1136 .clkr.hw.init = &(struct clk_init_data){ 1137 1137 .name = "usb_hs_system_clk_src", 1138 1138 .parent_data = gcc_xo_gpll0, 1139 - .num_parents = 2, 1139 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1140 1140 .ops = &clk_rcg2_ops, 1141 1141 }, 1142 1142 };