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cxl/pci: Remove unnecessary CXL RCH handling helper functions

cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific
to Restricted CXL Host (RCH) handling. Improve readability and
maintainability by replacing these and instead using the common
cxl_handle_cor_ras() and cxl_handle_ras() functions.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20260114182055.46029-6-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Terry Bowman and committed by
Dave Jiang eb78ef4d ca3d1a53

+2 -14
+2 -14
drivers/cxl/core/pci.c
··· 779 779 } 780 780 EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); 781 781 782 - static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, 783 - struct cxl_dport *dport) 784 - { 785 - return cxl_handle_cor_ras(cxlds, dport->regs.ras); 786 - } 787 - 788 - static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, 789 - struct cxl_dport *dport) 790 - { 791 - return cxl_handle_ras(cxlds, dport->regs.ras); 792 - } 793 - 794 782 /* 795 783 * Copy the AER capability registers using 32 bit read accesses. 796 784 * This is necessary because RCRB AER capability is MMIO mapped. Clear the ··· 848 860 pci_print_aer(pdev, severity, &aer_regs); 849 861 850 862 if (severity == AER_CORRECTABLE) 851 - cxl_handle_rdport_cor_ras(cxlds, dport); 863 + cxl_handle_cor_ras(cxlds, dport->regs.ras); 852 864 else 853 - cxl_handle_rdport_ras(cxlds, dport); 865 + cxl_handle_ras(cxlds, dport->regs.ras); 854 866 } 855 867 856 868 #else