drm/amd/pm: do not expose the smu_context structure used internally in power

-6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 99 99 #include "amdgpu_gem.h" 100 100 #include "amdgpu_doorbell.h" 101 101 #include "amdgpu_amdkfd.h" 102 - #include "amdgpu_smu.h" 103 102 #include "amdgpu_discovery.h" 104 103 #include "amdgpu_mes.h" 105 104 #include "amdgpu_umc.h" ··· 948 949 949 950 /* powerplay */ 950 951 struct amd_powerplay powerplay; 951 - 952 - /* smu */ 953 - struct smu_context smu; 954 - 955 - /* dpm */ 956 952 struct amdgpu_pm pm; 957 953 u32 cg_flags; 958 954 u32 pg_flags;

+3

drivers/gpu/drm/amd/include/kgd_pp_interface.h

··· 25 25 #define __KGD_PP_INTERFACE_H__ 26 26 27 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 + extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 + extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 + extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 28 31 29 32 enum smu_event_type { 30 33 SMU_EVENT_RESET_COMPLETE = 0,

+34 -16

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

··· 31 31 #include "amdgpu_display.h" 32 32 #include "hwmgr.h" 33 33 #include <linux/power_supply.h> 34 + #include "amdgpu_smu.h" 34 35 35 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 36 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) ··· 214 213 215 214 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 216 215 { 217 - struct smu_context *smu = &adev->smu; 216 + struct smu_context *smu = adev->powerplay.pp_handle; 218 217 219 218 if (is_support_sw_smu(adev)) 220 219 return smu_mode1_reset_is_support(smu); ··· 224 223 225 224 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 226 225 { 227 - struct smu_context *smu = &adev->smu; 226 + struct smu_context *smu = adev->powerplay.pp_handle; 228 227 229 228 if (is_support_sw_smu(adev)) 230 229 return smu_mode1_reset(smu); ··· 277 276 278 277 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 279 278 { 280 - struct smu_context *smu = &adev->smu; 279 + struct smu_context *smu = adev->powerplay.pp_handle; 281 280 282 281 if (is_support_sw_smu(adev)) 283 282 return smu_allow_xgmi_power_down(smu, en); ··· 342 341 mutex_unlock(&adev->pm.mutex); 343 342 344 343 if (is_support_sw_smu(adev)) 345 - smu_set_ac_dc(&adev->smu); 344 + smu_set_ac_dc(adev->powerplay.pp_handle); 346 345 } 347 346 } 348 347 ··· 427 426 428 427 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 429 428 { 430 - return smu_handle_passthrough_sbr(&adev->smu, enable); 429 + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); 431 430 } 432 431 433 432 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 434 433 { 435 - return smu_send_hbm_bad_pages_num(&adev->smu, size); 434 + struct smu_context *smu = adev->powerplay.pp_handle; 435 + 436 + return smu_send_hbm_bad_pages_num(smu, size); 436 437 } 437 438 438 439 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, ··· 447 444 448 445 switch (type) { 449 446 case PP_SCLK: 450 - return smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, min, max); 447 + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); 451 448 default: 452 449 return -EINVAL; 453 450 } ··· 458 455 uint32_t min, 459 456 uint32_t max) 460 457 { 458 + struct smu_context *smu = adev->powerplay.pp_handle; 459 + 461 460 if (!is_support_sw_smu(adev)) 462 461 return -EOPNOTSUPP; 463 462 464 463 switch (type) { 465 464 case PP_SCLK: 466 - return smu_set_soft_freq_range(&adev->smu, SMU_SCLK, min, max); 465 + return smu_set_soft_freq_range(smu, SMU_SCLK, min, max); 467 466 default: 468 467 return -EINVAL; 469 468 } ··· 473 468 474 469 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 475 470 { 471 + struct smu_context *smu = adev->powerplay.pp_handle; 472 + 476 473 if (!is_support_sw_smu(adev)) 477 474 return 0; 478 475 479 - return smu_write_watermarks_table(&adev->smu); 476 + return smu_write_watermarks_table(smu); 480 477 } 481 478 482 479 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, 483 480 enum smu_event_type event, 484 481 uint64_t event_arg) 485 482 { 483 + struct smu_context *smu = adev->powerplay.pp_handle; 484 + 486 485 if (!is_support_sw_smu(adev)) 487 486 return -EOPNOTSUPP; 488 487 489 - return smu_wait_for_event(&adev->smu, event, event_arg); 488 + return smu_wait_for_event(smu, event, event_arg); 490 489 } 491 490 492 491 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 493 492 { 493 + struct smu_context *smu = adev->powerplay.pp_handle; 494 + 494 495 if (!is_support_sw_smu(adev)) 495 496 return -EOPNOTSUPP; 496 497 497 - return smu_get_status_gfxoff(&adev->smu, value); 498 + return smu_get_status_gfxoff(smu, value); 498 499 } 499 500 500 501 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 501 502 { 502 - return atomic64_read(&adev->smu.throttle_int_counter); 503 + struct smu_context *smu = adev->powerplay.pp_handle; 504 + 505 + return atomic64_read(&smu->throttle_int_counter); 503 506 } 504 507 505 508 /* amdgpu_dpm_gfx_state_change - Handle gfx power state change set ··· 529 516 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 530 517 void *umc_ecc) 531 518 { 519 + struct smu_context *smu = adev->powerplay.pp_handle; 520 + 532 521 if (!is_support_sw_smu(adev)) 533 522 return -EOPNOTSUPP; 534 523 535 - return smu_get_ecc_info(&adev->smu, umc_ecc); 524 + return smu_get_ecc_info(smu, umc_ecc); 536 525 } 537 526 538 527 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, ··· 958 943 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 959 944 { 960 945 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 946 + struct smu_context *smu = adev->powerplay.pp_handle; 961 947 962 - if ((is_support_sw_smu(adev) && adev->smu.od_enabled) || 963 - (is_support_sw_smu(adev) && adev->smu.is_apu) || 948 + if ((is_support_sw_smu(adev) && smu->od_enabled) || 949 + (is_support_sw_smu(adev) && smu->is_apu) || 964 950 (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 965 951 return true; 966 952 ··· 984 968 985 969 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 986 970 { 987 - return adev->smu.cpu_core_num; 971 + struct smu_context *smu = adev->powerplay.pp_handle; 972 + 973 + return smu->cpu_core_num; 988 974 } 989 975 990 976 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev)

+1 -1

drivers/gpu/drm/amd/pm/amdgpu_pm.c

··· 2869 2869 int limit_type = to_sensor_dev_attr(attr)->index; 2870 2870 2871 2871 return sysfs_emit(buf, "%s\n", 2872 - limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT"); 2872 + limit_type == PP_PWR_TYPE_FAST ? "fastPPT" : "slowPPT"); 2873 2873 } 2874 2874 2875 2875 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,

-4

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

··· 1390 1390 1391 1391 extern const struct amd_ip_funcs smu_ip_funcs; 1392 1392 1393 - extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 1394 - extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 1395 - extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 1396 - 1397 1393 bool is_support_sw_smu(struct amdgpu_device *adev); 1398 1394 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1399 1395 int smu_write_watermarks_table(struct smu_context *smu);

+30 -18

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 468 468 469 469 bool is_support_cclk_dpm(struct amdgpu_device *adev) 470 470 { 471 - struct smu_context *smu = &adev->smu; 471 + struct smu_context *smu = adev->powerplay.pp_handle; 472 472 473 473 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 474 474 return false; ··· 572 572 573 573 static int smu_set_funcs(struct amdgpu_device *adev) 574 574 { 575 - struct smu_context *smu = &adev->smu; 575 + struct smu_context *smu = adev->powerplay.pp_handle; 576 576 577 577 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 578 578 smu->od_enabled = true; ··· 624 624 static int smu_early_init(void *handle) 625 625 { 626 626 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 627 - struct smu_context *smu = &adev->smu; 627 + struct smu_context *smu; 628 + 629 + smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 630 + if (!smu) 631 + return -ENOMEM; 628 632 629 633 smu->adev = adev; 630 634 smu->pm_enabled = !!amdgpu_dpm; ··· 688 684 static int smu_late_init(void *handle) 689 685 { 690 686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691 - struct smu_context *smu = &adev->smu; 687 + struct smu_context *smu = adev->powerplay.pp_handle; 692 688 int ret = 0; 693 689 694 690 smu_set_fine_grain_gfx_freq_parameters(smu); ··· 734 730 735 731 smu_get_fan_parameters(smu); 736 732 737 - smu_handle_task(&adev->smu, 733 + smu_handle_task(smu, 738 734 smu->smu_dpm.dpm_level, 739 735 AMD_PP_TASK_COMPLETE_INIT, 740 736 false); ··· 1024 1020 static int smu_sw_init(void *handle) 1025 1021 { 1026 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027 - struct smu_context *smu = &adev->smu; 1023 + struct smu_context *smu = adev->powerplay.pp_handle; 1028 1024 int ret; 1029 1025 1030 1026 smu->pool_size = adev->pm.smu_prv_buffer_size; ··· 1099 1095 static int smu_sw_fini(void *handle) 1100 1096 { 1101 1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 - struct smu_context *smu = &adev->smu; 1098 + struct smu_context *smu = adev->powerplay.pp_handle; 1103 1099 int ret; 1104 1100 1105 1101 ret = smu_smc_table_sw_fini(smu); ··· 1334 1330 { 1335 1331 int ret; 1336 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337 - struct smu_context *smu = &adev->smu; 1333 + struct smu_context *smu = adev->powerplay.pp_handle; 1338 1334 1339 1335 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1340 1336 smu->pm_enabled = false; ··· 1350 1346 if (smu->is_apu) { 1351 1347 smu_dpm_set_vcn_enable(smu, true); 1352 1348 smu_dpm_set_jpeg_enable(smu, true); 1353 - smu_set_gfx_cgpg(&adev->smu, true); 1349 + smu_set_gfx_cgpg(smu, true); 1354 1350 } 1355 1351 1356 1352 if (!smu->pm_enabled) ··· 1510 1506 static int smu_hw_fini(void *handle) 1511 1507 { 1512 1508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1513 - struct smu_context *smu = &adev->smu; 1509 + struct smu_context *smu = adev->powerplay.pp_handle; 1514 1510 1515 1511 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1516 1512 return 0; ··· 1527 1523 adev->pm.dpm_enabled = false; 1528 1524 1529 1525 return smu_smc_hw_cleanup(smu); 1526 + } 1527 + 1528 + static void smu_late_fini(void *handle) 1529 + { 1530 + struct amdgpu_device *adev = handle; 1531 + struct smu_context *smu = adev->powerplay.pp_handle; 1532 + 1533 + kfree(smu); 1530 1534 } 1531 1535 1532 1536 static int smu_reset(struct smu_context *smu) ··· 1564 1552 static int smu_suspend(void *handle) 1565 1553 { 1566 1554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1567 - struct smu_context *smu = &adev->smu; 1555 + struct smu_context *smu = adev->powerplay.pp_handle; 1568 1556 int ret; 1569 1557 1570 1558 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) ··· 1581 1569 1582 1570 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1583 1571 1584 - smu_set_gfx_cgpg(&adev->smu, false); 1572 + smu_set_gfx_cgpg(smu, false); 1585 1573 1586 1574 return 0; 1587 1575 } ··· 1590 1578 { 1591 1579 int ret; 1592 1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1593 - struct smu_context *smu = &adev->smu; 1581 + struct smu_context *smu = adev->powerplay.pp_handle; 1594 1582 1595 1583 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1596 1584 return 0; ··· 1612 1600 return ret; 1613 1601 } 1614 1602 1615 - smu_set_gfx_cgpg(&adev->smu, true); 1603 + smu_set_gfx_cgpg(smu, true); 1616 1604 1617 1605 smu->disable_uclk_switch = 0; 1618 1606 ··· 2144 2132 .sw_fini = smu_sw_fini, 2145 2133 .hw_init = smu_hw_init, 2146 2134 .hw_fini = smu_hw_fini, 2135 + .late_fini = smu_late_fini, 2147 2136 .suspend = smu_suspend, 2148 2137 .resume = smu_resume, 2149 2138 .is_idle = NULL, ··· 3209 3196 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3210 3197 { 3211 3198 struct amdgpu_device *adev = filp->f_inode->i_private; 3212 - struct smu_context *smu = &adev->smu; 3199 + struct smu_context *smu = adev->powerplay.pp_handle; 3213 3200 unsigned char *buf; 3214 3201 int r; 3215 3202 ··· 3234 3221 loff_t *pos) 3235 3222 { 3236 3223 struct amdgpu_device *adev = filp->f_inode->i_private; 3237 - struct smu_context *smu = &adev->smu; 3224 + struct smu_context *smu = adev->powerplay.pp_handle; 3238 3225 3239 3226 3240 3227 if (!filp->private_data) ··· 3275 3262 { 3276 3263 #if defined(CONFIG_DEBUG_FS) 3277 3264 3278 - struct smu_context *smu = &adev->smu; 3265 + struct smu_context *smu = adev->powerplay.pp_handle; 3279 3266 3280 3267 if (!smu->stb_context.stb_buf_size) 3281 3268 return; ··· 3287 3274 &smu_stb_debugfs_fops, 3288 3275 smu->stb_context.stb_buf_size); 3289 3276 #endif 3290 - 3291 3277 } 3292 3278 3293 3279 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)

+5 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

··· 2072 2072 struct i2c_msg *msg, int num_msgs) 2073 2073 { 2074 2074 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 2075 - struct smu_table_context *smu_table = &adev->smu.smu_table; 2075 + struct smu_context *smu = adev->powerplay.pp_handle; 2076 + struct smu_table_context *smu_table = &smu->smu_table; 2076 2077 struct smu_table *table = &smu_table->driver_table; 2077 2078 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2078 2079 int i, j, r, c; ··· 2119 2118 } 2120 2119 } 2121 2120 } 2122 - mutex_lock(&adev->smu.mutex); 2123 - r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2124 - mutex_unlock(&adev->smu.mutex); 2121 + mutex_lock(&smu->mutex); 2122 + r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2123 + mutex_unlock(&smu->mutex); 2125 2124 if (r) 2126 2125 goto fail; 2127 2126

+5 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

··· 2779 2779 struct i2c_msg *msg, int num_msgs) 2780 2780 { 2781 2781 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 2782 - struct smu_table_context *smu_table = &adev->smu.smu_table; 2782 + struct smu_context *smu = adev->powerplay.pp_handle; 2783 + struct smu_table_context *smu_table = &smu->smu_table; 2783 2784 struct smu_table *table = &smu_table->driver_table; 2784 2785 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2785 2786 int i, j, r, c; ··· 2826 2825 } 2827 2826 } 2828 2827 } 2829 - mutex_lock(&adev->smu.mutex); 2830 - r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2831 - mutex_unlock(&adev->smu.mutex); 2828 + mutex_lock(&smu->mutex); 2829 + r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2830 + mutex_unlock(&smu->mutex); 2832 2831 if (r) 2833 2832 goto fail; 2834 2833

+5 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 3459 3459 struct i2c_msg *msg, int num_msgs) 3460 3460 { 3461 3461 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 3462 - struct smu_table_context *smu_table = &adev->smu.smu_table; 3462 + struct smu_context *smu = adev->powerplay.pp_handle; 3463 + struct smu_table_context *smu_table = &smu->smu_table; 3463 3464 struct smu_table *table = &smu_table->driver_table; 3464 3465 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3465 3466 int i, j, r, c; ··· 3506 3505 } 3507 3506 } 3508 3507 } 3509 - mutex_lock(&adev->smu.mutex); 3510 - r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3511 - mutex_unlock(&adev->smu.mutex); 3508 + mutex_lock(&smu->mutex); 3509 + r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3510 + mutex_unlock(&smu->mutex); 3512 3511 if (r) 3513 3512 goto fail; 3514 3513

+2 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

··· 1372 1372 unsigned tyep, 1373 1373 enum amdgpu_interrupt_state state) 1374 1374 { 1375 - struct smu_context *smu = &adev->smu; 1375 + struct smu_context *smu = adev->powerplay.pp_handle; 1376 1376 uint32_t low, high; 1377 1377 uint32_t val = 0; 1378 1378 ··· 1441 1441 struct amdgpu_irq_src *source, 1442 1442 struct amdgpu_iv_entry *entry) 1443 1443 { 1444 - struct smu_context *smu = &adev->smu; 1444 + struct smu_context *smu = adev->powerplay.pp_handle; 1445 1445 uint32_t client_id = entry->client_id; 1446 1446 uint32_t src_id = entry->src_id; 1447 1447 /*

+5 -4

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

··· 1475 1475 struct i2c_msg *msg, int num_msgs) 1476 1476 { 1477 1477 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 1478 - struct smu_table_context *smu_table = &adev->smu.smu_table; 1478 + struct smu_context *smu = adev->powerplay.pp_handle; 1479 + struct smu_table_context *smu_table = &smu->smu_table; 1479 1480 struct smu_table *table = &smu_table->driver_table; 1480 1481 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1481 1482 int i, j, r, c; ··· 1522 1521 } 1523 1522 } 1524 1523 } 1525 - mutex_lock(&adev->smu.mutex); 1526 - r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1527 - mutex_unlock(&adev->smu.mutex); 1524 + mutex_lock(&smu->mutex); 1525 + r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1526 + mutex_unlock(&smu->mutex); 1528 1527 if (r) 1529 1528 goto fail; 1530 1529

+4 -4

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

··· 1200 1200 unsigned tyep, 1201 1201 enum amdgpu_interrupt_state state) 1202 1202 { 1203 - struct smu_context *smu = &adev->smu; 1203 + struct smu_context *smu = adev->powerplay.pp_handle; 1204 1204 uint32_t low, high; 1205 1205 uint32_t val = 0; 1206 1206 ··· 1275 1275 struct amdgpu_irq_src *source, 1276 1276 struct amdgpu_iv_entry *entry) 1277 1277 { 1278 - struct smu_context *smu = &adev->smu; 1278 + struct smu_context *smu = adev->powerplay.pp_handle; 1279 1279 uint32_t client_id = entry->client_id; 1280 1280 uint32_t src_id = entry->src_id; 1281 1281 /* ··· 1321 1321 switch (ctxid) { 1322 1322 case 0x3: 1323 1323 dev_dbg(adev->dev, "Switched to AC mode!\n"); 1324 - smu_v13_0_ack_ac_dc_interrupt(&adev->smu); 1324 + smu_v13_0_ack_ac_dc_interrupt(smu); 1325 1325 break; 1326 1326 case 0x4: 1327 1327 dev_dbg(adev->dev, "Switched to DC mode!\n"); 1328 - smu_v13_0_ack_ac_dc_interrupt(&adev->smu); 1328 + smu_v13_0_ack_ac_dc_interrupt(smu); 1329 1329 break; 1330 1330 case 0x7: 1331 1331 /*

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