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phy: qcom: qmp-combo: extract common function to setup clocks

Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY
clocks depending on the selected link rate.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-8-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul ec17373a 31a4ac68

+26 -37
+26 -37
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 2074 2074 return reverse; 2075 2075 } 2076 2076 2077 - static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2077 + static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2078 2078 { 2079 2079 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2080 - const struct qmp_phy_cfg *cfg = qmp->cfg; 2081 - u32 phy_vco_div, status; 2080 + u32 phy_vco_div; 2082 2081 unsigned long pixel_freq; 2083 - 2084 - qmp_combo_configure_dp_mode(qmp); 2085 - 2086 - writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2087 - writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2088 2082 2089 2083 switch (dp_opts->link_rate) { 2090 2084 case 1620: ··· 2101 2107 /* Other link rates aren't supported */ 2102 2108 return -EINVAL; 2103 2109 } 2104 - writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV); 2110 + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2105 2111 2106 2112 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2107 2113 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2114 + 2115 + return 0; 2116 + } 2117 + 2118 + static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2119 + { 2120 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2121 + u32 status; 2122 + int ret; 2123 + 2124 + qmp_combo_configure_dp_mode(qmp); 2125 + 2126 + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2127 + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2128 + 2129 + ret = qmp_combo_configure_dp_clocks(qmp); 2130 + if (ret) 2131 + return ret; 2108 2132 2109 2133 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2110 2134 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); ··· 2222 2210 2223 2211 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2224 2212 { 2225 - const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2226 2213 const struct qmp_phy_cfg *cfg = qmp->cfg; 2227 - u32 phy_vco_div, status; 2228 - unsigned long pixel_freq; 2214 + u32 status; 2215 + int ret; 2229 2216 2230 2217 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2231 2218 ··· 2236 2225 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2237 2226 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2238 2227 2239 - switch (dp_opts->link_rate) { 2240 - case 1620: 2241 - phy_vco_div = 0x1; 2242 - pixel_freq = 1620000000UL / 2; 2243 - break; 2244 - case 2700: 2245 - phy_vco_div = 0x1; 2246 - pixel_freq = 2700000000UL / 2; 2247 - break; 2248 - case 5400: 2249 - phy_vco_div = 0x2; 2250 - pixel_freq = 5400000000UL / 4; 2251 - break; 2252 - case 8100: 2253 - phy_vco_div = 0x0; 2254 - pixel_freq = 8100000000UL / 6; 2255 - break; 2256 - default: 2257 - /* Other link rates aren't supported */ 2258 - return -EINVAL; 2259 - } 2260 - writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2261 - 2262 - clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2263 - clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2228 + ret = qmp_combo_configure_dp_clocks(qmp); 2229 + if (ret) 2230 + return ret; 2264 2231 2265 2232 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2266 2233 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);