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Merge tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.6 Part 2

T-Head:
Add a second minimal devicetree for the second board using the th1520
SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient
only for booting to a console, with work on the mmc, clocks and ethernet
sides of things under way. A relicense to a dual licence for the
existing devicetree files is also done, for good measure.
RISC-V Devicetrees for v6.6-pt2

StarFive:
Fix the sort order of some nodes that I resolved incorrectly during a
merge conflict.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
riscv: dts: starfive: fix jh7110 qspi sort order

Link: https://lore.kernel.org/r/20230819-unwieldy-railing-9bba2b176aa7@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann ecd2dc2f 6522fbd4

+88 -23
+4
Documentation/devicetree/bindings/riscv/thead.yaml
··· 17 17 const: '/' 18 18 compatible: 19 19 oneOf: 20 + - description: BeagleV Ahead single board computer 21 + items: 22 + - const: beagle,beaglev-ahead 23 + - const: thead,th1520 20 24 - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A 21 25 items: 22 26 - enum:
+19 -19
arch/riscv/boot/dts/starfive/jh7110.dtsi
··· 676 676 status = "disabled"; 677 677 }; 678 678 679 - qspi: spi@13010000 { 680 - compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; 681 - reg = <0x0 0x13010000 0x0 0x10000>, 682 - <0x0 0x21000000 0x0 0x400000>; 683 - interrupts = <25>; 684 - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, 685 - <&syscrg JH7110_SYSCLK_QSPI_AHB>, 686 - <&syscrg JH7110_SYSCLK_QSPI_APB>; 687 - clock-names = "ref", "ahb", "apb"; 688 - resets = <&syscrg JH7110_SYSRST_QSPI_APB>, 689 - <&syscrg JH7110_SYSRST_QSPI_AHB>, 690 - <&syscrg JH7110_SYSRST_QSPI_REF>; 691 - reset-names = "qspi", "qspi-ocp", "rstc_ref"; 692 - cdns,fifo-depth = <256>; 693 - cdns,fifo-width = <4>; 694 - cdns,trigger-address = <0x0>; 695 - status = "disabled"; 696 - }; 697 - 698 679 spi3: spi@12070000 { 699 680 compatible = "arm,pl022", "arm,primecell"; 700 681 reg = <0x0 0x12070000 0x0 0x10000>; ··· 746 765 <&syscrg JH7110_SYSRST_TEMP_APB>; 747 766 reset-names = "sense", "bus"; 748 767 #thermal-sensor-cells = <0>; 768 + }; 769 + 770 + qspi: spi@13010000 { 771 + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; 772 + reg = <0x0 0x13010000 0x0 0x10000>, 773 + <0x0 0x21000000 0x0 0x400000>; 774 + interrupts = <25>; 775 + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, 776 + <&syscrg JH7110_SYSCLK_QSPI_AHB>, 777 + <&syscrg JH7110_SYSCLK_QSPI_APB>; 778 + clock-names = "ref", "ahb", "apb"; 779 + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, 780 + <&syscrg JH7110_SYSRST_QSPI_AHB>, 781 + <&syscrg JH7110_SYSRST_QSPI_REF>; 782 + reset-names = "qspi", "qspi-ocp", "rstc_ref"; 783 + cdns,fifo-depth = <256>; 784 + cdns,fifo-width = <4>; 785 + cdns,trigger-address = <0x0>; 786 + status = "disabled"; 749 787 }; 750 788 751 789 syscrg: clock-controller@13020000 {
+1 -1
arch/riscv/boot/dts/thead/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb 2 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb
+61
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /* 3 + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 + * Copyright (C) 2023 Drew Fustini <dfustini@baylibre.com> 5 + */ 6 + 7 + /dts-v1/; 8 + 9 + #include "th1520.dtsi" 10 + 11 + / { 12 + model = "BeagleV Ahead"; 13 + compatible = "beagle,beaglev-ahead", "thead,th1520"; 14 + 15 + aliases { 16 + gpio0 = &gpio0; 17 + gpio1 = &gpio1; 18 + gpio2 = &gpio2; 19 + gpio3 = &gpio3; 20 + serial0 = &uart0; 21 + serial1 = &uart1; 22 + serial2 = &uart2; 23 + serial3 = &uart3; 24 + serial4 = &uart4; 25 + serial5 = &uart5; 26 + }; 27 + 28 + chosen { 29 + stdout-path = "serial0:115200n8"; 30 + }; 31 + 32 + memory@0 { 33 + device_type = "memory"; 34 + reg = <0x0 0x00000000 0x1 0x00000000>; 35 + 36 + }; 37 + }; 38 + 39 + &osc { 40 + clock-frequency = <24000000>; 41 + }; 42 + 43 + &osc_32k { 44 + clock-frequency = <32768>; 45 + }; 46 + 47 + &apb_clk { 48 + clock-frequency = <62500000>; 49 + }; 50 + 51 + &uart_sclk { 52 + clock-frequency = <100000000>; 53 + }; 54 + 55 + &dmac0 { 56 + status = "okay"; 57 + }; 58 + 59 + &uart0 { 60 + status = "okay"; 61 + };
+1 -1
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 2 /* 3 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 4 */
+1 -1
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 2 /* 3 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 4 */
+1 -1
arch/riscv/boot/dts/thead/th1520.dtsi
··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 2 /* 3 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>