Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
serial: 8250_exar: Decrease indentation level
Decrease indentation level in some places.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Parker Newman <pnewman@connecttech.com>
Link: https://lore.kernel.org/r/20240503171917.2921250-9-andriy.shevchenko@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Andy Shevchenko
and committed by
Greg Kroah-Hartman
ee6c49a7
709bb045
+50
-50
+50
-50
drivers/tty/serial/8250/8250_exar.c
+50
-50
drivers/tty/serial/8250/8250_exar.c
···
607
607
writeb(32, p + UART_EXAR_TXTRG);
608
608
writeb(32, p + UART_EXAR_RXTRG);
609
609
610
+
/* Skip the initial (per device) setup */
611
+
if (idx)
612
+
return 0;
613
+
610
614
/*
611
615
* Setup Multipurpose Input/Output pins.
612
616
*/
613
-
if (idx == 0) {
614
-
switch (pcidev->device) {
615
-
case PCI_DEVICE_ID_COMMTECH_4222PCI335:
616
-
case PCI_DEVICE_ID_COMMTECH_4224PCI335:
617
-
writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
618
-
writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
619
-
writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
620
-
break;
621
-
case PCI_DEVICE_ID_COMMTECH_2324PCI335:
622
-
case PCI_DEVICE_ID_COMMTECH_2328PCI335:
623
-
writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
624
-
writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
625
-
writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
626
-
break;
627
-
}
628
-
writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
629
-
writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
630
-
writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
617
+
switch (pcidev->device) {
618
+
case PCI_DEVICE_ID_COMMTECH_4222PCI335:
619
+
case PCI_DEVICE_ID_COMMTECH_4224PCI335:
620
+
writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
621
+
writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
622
+
writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
623
+
break;
624
+
case PCI_DEVICE_ID_COMMTECH_2324PCI335:
625
+
case PCI_DEVICE_ID_COMMTECH_2328PCI335:
626
+
writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
627
+
writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
628
+
writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
629
+
break;
631
630
}
631
+
writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
632
+
writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
633
+
writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
632
634
633
635
return 0;
634
636
}
···
855
853
port_flags = exar_ee_read(priv, offset);
856
854
857
855
port_type = FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags);
858
-
if (!CTI_PORT_TYPE_VALID(port_type)) {
859
-
/*
860
-
* If the port type is missing the card assume it is a
861
-
* RS232/RS422/RS485 card to be safe.
862
-
*
863
-
* There is one known board (BEG013) that only has
864
-
* 3 of 4 port types written to the EEPROM so this
865
-
* acts as a work around.
866
-
*/
867
-
dev_warn(&pcidev->dev,
868
-
"failed to get port %d type from EEPROM\n", port_num);
869
-
port_type = CTI_PORT_TYPE_RS232_422_485_HW;
870
-
}
856
+
if (CTI_PORT_TYPE_VALID(port_type))
857
+
return port_type;
871
858
872
-
return port_type;
859
+
/*
860
+
* If the port type is missing the card assume it is a
861
+
* RS232/RS422/RS485 card to be safe.
862
+
*
863
+
* There is one known board (BEG013) that only has 3 of 4 port types
864
+
* written to the EEPROM so this acts as a work around.
865
+
*/
866
+
dev_warn(&pcidev->dev, "failed to get port %d type from EEPROM\n", port_num);
867
+
868
+
return CTI_PORT_TYPE_RS232_422_485_HW;
873
869
}
874
870
875
871
static int cti_rs485_config_mpio_tristate(struct uart_port *port,
···
1190
1190
* devices will export them as GPIOs, so we pre-configure them safely
1191
1191
* as inputs.
1192
1192
*/
1193
-
1194
1193
u8 dir = 0x00;
1195
1194
1196
1195
if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
1197
-
(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
1196
+
(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
1198
1197
// Configure GPIO as inputs for Commtech adapters
1199
1198
dir = 0xff;
1200
1199
} else {
···
1283
1284
if (ret)
1284
1285
return ret;
1285
1286
1286
-
if (rs485->flags & SER_RS485_ENABLED) {
1287
-
old_lcr = readb(p + UART_LCR);
1287
+
if (!(rs485->flags & SER_RS485_ENABLED))
1288
+
return 0;
1288
1289
1289
-
/* Set EFR[4]=1 to enable enhanced feature registers */
1290
-
efr = readb(p + UART_XR_EFR);
1291
-
efr |= UART_EFR_ECB;
1292
-
writeb(efr, p + UART_XR_EFR);
1290
+
old_lcr = readb(p + UART_LCR);
1293
1291
1294
-
/* Set MCR to use DTR as Auto-RS485 Enable signal */
1295
-
writeb(UART_MCR_OUT1, p + UART_MCR);
1292
+
/* Set EFR[4]=1 to enable enhanced feature registers */
1293
+
efr = readb(p + UART_XR_EFR);
1294
+
efr |= UART_EFR_ECB;
1295
+
writeb(efr, p + UART_XR_EFR);
1296
1296
1297
-
/* Set LCR[7]=1 to enable access to DLD register */
1298
-
writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
1297
+
/* Set MCR to use DTR as Auto-RS485 Enable signal */
1298
+
writeb(UART_MCR_OUT1, p + UART_MCR);
1299
1299
1300
-
/* Set DLD[7]=1 for inverted RS485 Enable logic */
1301
-
dld = readb(p + UART_EXAR_DLD);
1302
-
dld |= UART_EXAR_DLD_485_POLARITY;
1303
-
writeb(dld, p + UART_EXAR_DLD);
1300
+
/* Set LCR[7]=1 to enable access to DLD register */
1301
+
writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
1304
1302
1305
-
writeb(old_lcr, p + UART_LCR);
1306
-
}
1303
+
/* Set DLD[7]=1 for inverted RS485 Enable logic */
1304
+
dld = readb(p + UART_EXAR_DLD);
1305
+
dld |= UART_EXAR_DLD_485_POLARITY;
1306
+
writeb(dld, p + UART_EXAR_DLD);
1307
+
1308
+
writeb(old_lcr, p + UART_LCR);
1307
1309
1308
1310
return 0;
1309
1311
}