Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'ata-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
Pull ata updates from Damien Le Moal:
- Simplify ata_print_version_once() using dev_dbg_once() (Heiner)
- Some cleanups of libata-sata code to simplify the sense data fetching
code and use BIT() macro for tag bit handling (Niklas)
- Fix variable name spelling in the sata_sx4 driver (Colin)
- Improve sense data information field handling for passthrough
commands (Igor)
- Add Rockchip RK3576 SoC compatible to the Designware AHCI DT bindings
(Nicolas)
- Add a message to indicate if a port is marked as external or not, to
help with debugging potential issues with LPM (Niklas)
- Convert DT bindings for "ti,dm816-ahci", "apm,xgene-ahci",
"cavium,ebt3000-compact-flash", "marvell,orion-sata", and
"arasan,cf-spear1340" to DT schema (Rob)
- Cleanup and improve the code and related comments for HIPM and DIPM
(host initiated and device initiated power managent) handling.
In particular, keep DIPM disabled while modifying the allowed LPM
states to avoid races with the device initiating power state changes
(Niklas)
* tag 'ata-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux:
ata: libata-eh: Keep DIPM disabled while modifying the allowed LPM states
ata: libata-eh: Rename no_dipm variable to be more clear
ata: libata-eh: Rename hipm and dipm variables
ata: libata-eh: Add ata_eh_set_lpm() WARN_ON_ONCE
ata: libata-eh: Update DIPM comments to reflect reality
dt-bindings: ata: Convert arasan,cf-spear1340 to DT schema
dt-bindings: ata: Convert marvell,orion-sata to DT schema
dt-bindings: ata: Convert cavium,ebt3000-compact-flash to DT schema
dt-bindings: ata: Convert apm,xgene-ahci to DT schema
dt-bindings: ata: Convert st,ahci to DT schema
dt-bindings: ata: Convert ti,dm816-ahci to DT schema
ata: libata: Print if port is external on boot
dt-bindings: ata: rockchip-dwc-ahci: add RK3576 compatible
ata: libata-scsi: Do not set the INFORMATION field twice for ATA PT
ata: sata_sx4: Fix spelling mistake "parttern" -> "pattern"
ata: libata-sata: Use BIT() macro to convert tag to bit field
ata: libata-sata: Simplify sense_valid fetching
ata: libata-core: Simplify ata_print_version_once
+455
-295
-21
Documentation/devicetree/bindings/ata/ahci-dm816.txt
-21
Documentation/devicetree/bindings/ata/ahci-dm816.txt
···
1
-
Device tree binding for the TI DM816 AHCI SATA Controller
2
-
---------------------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible: must be "ti,dm816-ahci"
6
-
- reg: physical base address and size of the register region used by
7
-
the controller (as defined by the AHCI 1.1 standard)
8
-
- interrupts: interrupt specifier (refer to the interrupt binding)
9
-
- clocks: list of phandle and clock specifier pairs (or only
10
-
phandles for clock providers with '0' defined for
11
-
#clock-cells); two clocks must be specified: the functional
12
-
clock and an external reference clock
13
-
14
-
Example:
15
-
16
-
sata: sata@4a140000 {
17
-
compatible = "ti,dm816-ahci";
18
-
reg = <0x4a140000 0x10000>;
19
-
interrupts = <16>;
20
-
clocks = <&sysclk5_ck>, <&sata_refclk>;
21
-
};
-35
Documentation/devicetree/bindings/ata/ahci-st.txt
-35
Documentation/devicetree/bindings/ata/ahci-st.txt
···
1
-
STMicroelectronics STi SATA controller
2
-
3
-
This binding describes a SATA device.
4
-
5
-
Required properties:
6
-
- compatible : Must be "st,ahci"
7
-
- reg : Physical base addresses and length of register sets
8
-
- interrupts : Interrupt associated with the SATA device
9
-
- interrupt-names : Associated name must be; "hostc"
10
-
- clocks : The phandle for the clock
11
-
- clock-names : Associated name must be; "ahci_clk"
12
-
- phys : The phandle for the PHY port
13
-
- phy-names : Associated name must be; "ahci_phy"
14
-
15
-
Optional properties:
16
-
- resets : The power-down, soft-reset and power-reset lines of SATA IP
17
-
- reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
18
-
19
-
Example:
20
-
21
-
/* Example for stih407 family silicon */
22
-
sata0: sata@9b20000 {
23
-
compatible = "st,ahci";
24
-
reg = <0x9b20000 0x1000>;
25
-
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
26
-
interrupt-names = "hostc";
27
-
phys = <&phy_port0 PHY_TYPE_SATA>;
28
-
phy-names = "ahci_phy";
29
-
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
30
-
<&softreset STIH407_SATA0_SOFTRESET>,
31
-
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
32
-
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
33
-
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
34
-
clock-names = "ahci_clk";
35
-
};
+58
Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml
+58
Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/apm,xgene-ahci.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: APM X-Gene 6.0 Gb/s SATA host controller
8
+
9
+
maintainers:
10
+
- Rob Herring <robh@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: ahci-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- apm,xgene-ahci
19
+
- apm,xgene-ahci-pcie
20
+
21
+
reg:
22
+
minItems: 4
23
+
items:
24
+
- description: AHCI memory resource
25
+
- description: Host controller core
26
+
- description: Host controller diagnostic
27
+
- description: Host controller AXI
28
+
- description: Host controller MUX
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
clocks:
34
+
maxItems: 1
35
+
36
+
required:
37
+
- compatible
38
+
- clocks
39
+
- phys
40
+
- phy-names
41
+
42
+
unevaluatedProperties: false
43
+
44
+
examples:
45
+
- |
46
+
sata@1a400000 {
47
+
compatible = "apm,xgene-ahci";
48
+
reg = <0x1a400000 0x1000>,
49
+
<0x1f220000 0x1000>,
50
+
<0x1f22d000 0x1000>,
51
+
<0x1f22e000 0x1000>,
52
+
<0x1f227000 0x1000>;
53
+
clocks = <&sataclk 0>;
54
+
dma-coherent;
55
+
interrupts = <0x0 0x87 0x4>;
56
+
phys = <&phy2 0>;
57
+
phy-names = "sata-phy";
58
+
};
-77
Documentation/devicetree/bindings/ata/apm-xgene.txt
-77
Documentation/devicetree/bindings/ata/apm-xgene.txt
···
1
-
* APM X-Gene 6.0 Gb/s SATA host controller nodes
2
-
3
-
SATA host controller nodes are defined to describe on-chip Serial ATA
4
-
controllers. Each SATA controller (pair of ports) have its own node.
5
-
6
-
Required properties:
7
-
- compatible : Shall contain:
8
-
* "apm,xgene-ahci"
9
-
- reg : First memory resource shall be the AHCI memory
10
-
resource.
11
-
Second memory resource shall be the host controller
12
-
core memory resource.
13
-
Third memory resource shall be the host controller
14
-
diagnostic memory resource.
15
-
4th memory resource shall be the host controller
16
-
AXI memory resource.
17
-
5th optional memory resource shall be the host
18
-
controller MUX memory resource if required.
19
-
- interrupts : Interrupt-specifier for SATA host controller IRQ.
20
-
- clocks : Reference to the clock entry.
21
-
- phys : A list of phandles + phy-specifiers, one for each
22
-
entry in phy-names.
23
-
- phy-names : Should contain:
24
-
* "sata-phy" for the SATA 6.0Gbps PHY
25
-
26
-
Optional properties:
27
-
- dma-coherent : Present if dma operations are coherent
28
-
- status : Shall be "ok" if enabled or "disabled" if disabled.
29
-
Default is "ok".
30
-
31
-
Example:
32
-
sataclk: sataclk {
33
-
compatible = "fixed-clock";
34
-
#clock-cells = <1>;
35
-
clock-frequency = <100000000>;
36
-
clock-output-names = "sataclk";
37
-
};
38
-
39
-
phy2: phy@1f22a000 {
40
-
compatible = "apm,xgene-phy";
41
-
reg = <0x0 0x1f22a000 0x0 0x100>;
42
-
#phy-cells = <1>;
43
-
};
44
-
45
-
phy3: phy@1f23a000 {
46
-
compatible = "apm,xgene-phy";
47
-
reg = <0x0 0x1f23a000 0x0 0x100>;
48
-
#phy-cells = <1>;
49
-
};
50
-
51
-
sata2: sata@1a400000 {
52
-
compatible = "apm,xgene-ahci";
53
-
reg = <0x0 0x1a400000 0x0 0x1000>,
54
-
<0x0 0x1f220000 0x0 0x1000>,
55
-
<0x0 0x1f22d000 0x0 0x1000>,
56
-
<0x0 0x1f22e000 0x0 0x1000>,
57
-
<0x0 0x1f227000 0x0 0x1000>;
58
-
interrupts = <0x0 0x87 0x4>;
59
-
dma-coherent;
60
-
clocks = <&sataclk 0>;
61
-
phys = <&phy2 0>;
62
-
phy-names = "sata-phy";
63
-
};
64
-
65
-
sata3: sata@1a800000 {
66
-
compatible = "apm,xgene-ahci-pcie";
67
-
reg = <0x0 0x1a800000 0x0 0x1000>,
68
-
<0x0 0x1f230000 0x0 0x1000>,
69
-
<0x0 0x1f23d000 0x0 0x1000>,
70
-
<0x0 0x1f23e000 0x0 0x1000>,
71
-
<0x0 0x1f237000 0x0 0x1000>;
72
-
interrupts = <0x0 0x88 0x4>;
73
-
dma-coherent;
74
-
clocks = <&sataclk 0>;
75
-
phys = <&phy3 0>;
76
-
phy-names = "sata-phy";
77
-
};
+70
Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml
+70
Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/arasan,cf-spear1340.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Arasan PATA Compact Flash Controller
8
+
9
+
maintainers:
10
+
- Viresh Kumar <viresh.kumar@linaro.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: arasan,cf-spear1340
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
interrupts:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
maxItems: 1
24
+
25
+
arasan,broken-udma:
26
+
description: UDMA mode is unusable
27
+
type: boolean
28
+
29
+
arasan,broken-mwdma:
30
+
description: MWDMA mode is unusable
31
+
type: boolean
32
+
33
+
arasan,broken-pio:
34
+
description: PIO mode is unusable
35
+
type: boolean
36
+
37
+
dmas:
38
+
maxItems: 1
39
+
40
+
dma-names:
41
+
items:
42
+
- const: data
43
+
44
+
required:
45
+
- compatible
46
+
- reg
47
+
- interrupts
48
+
49
+
additionalProperties: false
50
+
51
+
allOf:
52
+
- if:
53
+
not:
54
+
required:
55
+
- arasan,broken-udma
56
+
- arasan,broken-mwdma
57
+
then:
58
+
required:
59
+
- dmas
60
+
- dma-names
61
+
62
+
examples:
63
+
- |
64
+
cf@fc000000 {
65
+
compatible = "arasan,cf-spear1340";
66
+
reg = <0xfc000000 0x1000>;
67
+
interrupts = <12>;
68
+
dmas = <&dma 23>;
69
+
dma-names = "data";
70
+
};
+59
Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml
+59
Documentation/devicetree/bindings/ata/cavium,ebt3000-compact-flash.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/cavium,ebt3000-compact-flash.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cavium Compact Flash
8
+
9
+
maintainers:
10
+
- Rob Herring <robh@kernel.org>
11
+
12
+
description:
13
+
The Cavium Compact Flash device is connected to the Octeon Boot Bus, and is
14
+
thus a child of the Boot Bus device. It can read and write industry standard
15
+
compact flash devices.
16
+
17
+
properties:
18
+
compatible:
19
+
const: cavium,ebt3000-compact-flash
20
+
21
+
reg:
22
+
description: The base address of the CF chip select banks.
23
+
items:
24
+
- description: CF chip select bank 0
25
+
- description: CF chip select bank 1
26
+
27
+
cavium,bus-width:
28
+
description: The width of the connection to the CF devices.
29
+
$ref: /schemas/types.yaml#/definitions/uint32
30
+
enum: [8, 16]
31
+
32
+
cavium,true-ide:
33
+
description: True IDE mode when present.
34
+
type: boolean
35
+
36
+
cavium,dma-engine-handle:
37
+
description: A phandle for the DMA Engine connected to this device.
38
+
$ref: /schemas/types.yaml#/definitions/phandle
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
bus {
49
+
#address-cells = <2>;
50
+
#size-cells = <1>;
51
+
52
+
compact-flash@5,0 {
53
+
compatible = "cavium,ebt3000-compact-flash";
54
+
reg = <5 0 0x10000>, <6 0 0x10000>;
55
+
cavium,bus-width = <16>;
56
+
cavium,true-ide;
57
+
cavium,dma-engine-handle = <&dma0>;
58
+
};
59
+
};
-30
Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
-30
Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
···
1
-
* Compact Flash
2
-
3
-
The Cavium Compact Flash device is connected to the Octeon Boot Bus,
4
-
and is thus a child of the Boot Bus device. It can read and write
5
-
industry standard compact flash devices.
6
-
7
-
Properties:
8
-
- compatible: "cavium,ebt3000-compact-flash";
9
-
10
-
Compatibility with many Cavium evaluation boards.
11
-
12
-
- reg: The base address of the CF chip select banks. Depending on
13
-
the device configuration, there may be one or two banks.
14
-
15
-
- cavium,bus-width: The width of the connection to the CF devices. Valid
16
-
values are 8 and 16.
17
-
18
-
- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
19
-
20
-
- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
21
-
to this device.
22
-
23
-
Example:
24
-
compact-flash@5,0 {
25
-
compatible = "cavium,ebt3000-compact-flash";
26
-
reg = <5 0 0x10000>, <6 0 0x10000>;
27
-
cavium,bus-width = <16>;
28
-
cavium,true-ide;
29
-
cavium,dma-engine-handle = <&dma0>;
30
-
};
+83
Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml
+83
Documentation/devicetree/bindings/ata/marvell,orion-sata.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/marvell,orion-sata.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell Orion SATA
8
+
9
+
maintainers:
10
+
- Andrew Lunn <andrew@lunn.ch>
11
+
- Gregory Clement <gregory.clement@bootlin.com>
12
+
13
+
allOf:
14
+
- $ref: sata-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- marvell,orion-sata
20
+
- marvell,armada-370-sata
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
clocks:
26
+
minItems: 1
27
+
maxItems: 8
28
+
29
+
clock-names:
30
+
minItems: 1
31
+
items:
32
+
- const: '0'
33
+
- const: '1'
34
+
- const: '2'
35
+
- const: '3'
36
+
- const: '4'
37
+
- const: '5'
38
+
- const: '6'
39
+
- const: '7'
40
+
41
+
interrupts:
42
+
maxItems: 1
43
+
44
+
nr-ports:
45
+
description:
46
+
Number of SATA ports in use.
47
+
$ref: /schemas/types.yaml#/definitions/uint32
48
+
maximum: 8
49
+
50
+
phys:
51
+
minItems: 1
52
+
maxItems: 8
53
+
54
+
phy-names:
55
+
minItems: 1
56
+
items:
57
+
- const: port0
58
+
- const: port1
59
+
- const: port2
60
+
- const: port3
61
+
- const: port4
62
+
- const: port5
63
+
- const: port6
64
+
- const: port7
65
+
66
+
required:
67
+
- compatible
68
+
- reg
69
+
- interrupts
70
+
- nr-ports
71
+
72
+
unevaluatedProperties: false
73
+
74
+
examples:
75
+
- |
76
+
sata@80000 {
77
+
compatible = "marvell,orion-sata";
78
+
reg = <0x80000 0x5000>;
79
+
interrupts = <21>;
80
+
phys = <&sata_phy0>, <&sata_phy1>;
81
+
phy-names = "port0", "port1";
82
+
nr-ports = <2>;
83
+
};
-22
Documentation/devicetree/bindings/ata/marvell.txt
-22
Documentation/devicetree/bindings/ata/marvell.txt
···
1
-
* Marvell Orion SATA
2
-
3
-
Required Properties:
4
-
- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5
-
- reg : Address range of controller
6
-
- interrupts : Interrupt controller is using
7
-
- nr-ports : Number of SATA ports in use.
8
-
9
-
Optional Properties:
10
-
- phys : List of phandles to sata phys
11
-
- phy-names : Should be "0", "1", etc, one number per phandle
12
-
13
-
Example:
14
-
15
-
sata@80000 {
16
-
compatible = "marvell,orion-sata";
17
-
reg = <0x80000 0x5000>;
18
-
interrupts = <21>;
19
-
phys = <&sata_phy0>, <&sata_phy1>;
20
-
phy-names = "0", "1";
21
-
nr-ports = <2>;
22
-
}
-37
Documentation/devicetree/bindings/ata/pata-arasan.txt
-37
Documentation/devicetree/bindings/ata/pata-arasan.txt
···
1
-
* ARASAN PATA COMPACT FLASH CONTROLLER
2
-
3
-
Required properties:
4
-
- compatible: "arasan,cf-spear1340"
5
-
- reg: Address range of the CF registers
6
-
- interrupt: Should contain the CF interrupt number
7
-
- clock-frequency: Interface clock rate, in Hz, one of
8
-
25000000
9
-
33000000
10
-
40000000
11
-
50000000
12
-
66000000
13
-
75000000
14
-
100000000
15
-
125000000
16
-
150000000
17
-
166000000
18
-
200000000
19
-
20
-
Optional properties:
21
-
- arasan,broken-udma: if present, UDMA mode is unusable
22
-
- arasan,broken-mwdma: if present, MWDMA mode is unusable
23
-
- arasan,broken-pio: if present, PIO mode is unusable
24
-
- dmas: one DMA channel, as described in bindings/dma/dma.txt
25
-
required unless both UDMA and MWDMA mode are broken
26
-
- dma-names: the corresponding channel name, must be "data"
27
-
28
-
Example:
29
-
30
-
cf@fc000000 {
31
-
compatible = "arasan,cf-spear1340";
32
-
reg = <0xfc000000 0x1000>;
33
-
interrupt-parent = <&vic1>;
34
-
interrupts = <12>;
35
-
dmas = <&dma-controller 23>;
36
-
dma-names = "data";
37
-
};
+3
Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
+3
Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml
···
20
20
contains:
21
21
enum:
22
22
- rockchip,rk3568-dwc-ahci
23
+
- rockchip,rk3576-dwc-ahci
23
24
- rockchip,rk3588-dwc-ahci
24
25
required:
25
26
- compatible
···
30
29
items:
31
30
- enum:
32
31
- rockchip,rk3568-dwc-ahci
32
+
- rockchip,rk3576-dwc-ahci
33
33
- rockchip,rk3588-dwc-ahci
34
34
- const: snps,dwc-ahci
35
35
···
85
83
contains:
86
84
enum:
87
85
- rockchip,rk3568-dwc-ahci
86
+
- rockchip,rk3576-dwc-ahci
88
87
then:
89
88
properties:
90
89
clocks:
+72
Documentation/devicetree/bindings/ata/st,ahci.yaml
+72
Documentation/devicetree/bindings/ata/st,ahci.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/st,ahci.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STMicroelectronics STi SATA controller
8
+
9
+
maintainers:
10
+
- Patrice Chotard <patrice.chotard@foss.st.com>
11
+
12
+
allOf:
13
+
- $ref: ahci-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: st,ahci
18
+
19
+
interrupt-names:
20
+
items:
21
+
- const: hostc
22
+
23
+
clocks:
24
+
maxItems: 1
25
+
26
+
clock-names:
27
+
items:
28
+
- const: ahci_clk
29
+
30
+
resets:
31
+
items:
32
+
- description: Power-down line
33
+
- description: Soft-reset line
34
+
- description: Power-reset line
35
+
36
+
reset-names:
37
+
items:
38
+
- const: pwr-dwn
39
+
- const: sw-rst
40
+
- const: pwr-rst
41
+
42
+
required:
43
+
- compatible
44
+
- interrupt-names
45
+
- phys
46
+
- phy-names
47
+
- clocks
48
+
- clock-names
49
+
50
+
unevaluatedProperties: false
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
55
+
#include <dt-bindings/phy/phy.h>
56
+
#include <dt-bindings/reset/stih407-resets.h>
57
+
#include <dt-bindings/clock/stih407-clks.h>
58
+
59
+
sata@9b20000 {
60
+
compatible = "st,ahci";
61
+
reg = <0x9b20000 0x1000>;
62
+
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
63
+
interrupt-names = "hostc";
64
+
phys = <&phy_port0 PHY_TYPE_SATA>;
65
+
phy-names = "sata-phy";
66
+
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
67
+
<&softreset STIH407_SATA0_SOFTRESET>,
68
+
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
69
+
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
70
+
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
71
+
clock-names = "ahci_clk";
72
+
};
+43
Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml
+43
Documentation/devicetree/bindings/ata/ti,dm816-ahci.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/ata/ti,dm816-ahci.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI DM816 AHCI SATA Controller
8
+
9
+
maintainers:
10
+
- Bartosz Golaszewski <brgl@bgdev.pl>
11
+
12
+
allOf:
13
+
- $ref: ahci-common.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: ti,dm816-ahci
18
+
19
+
reg:
20
+
maxItems: 1
21
+
22
+
clocks:
23
+
items:
24
+
- description: functional clock
25
+
- description: external reference clock
26
+
27
+
ti,hwmods:
28
+
const: sata
29
+
30
+
required:
31
+
- compatible
32
+
- clocks
33
+
34
+
unevaluatedProperties: false
35
+
36
+
examples:
37
+
- |
38
+
sata@4a140000 {
39
+
compatible = "ti,dm816-ahci";
40
+
reg = <0x4a140000 0x10000>;
41
+
interrupts = <16>;
42
+
clocks = <&sysclk5_ck>, <&sata_refclk>;
43
+
};
-6
drivers/ata/libata-core.c
-6
drivers/ata/libata-core.c
···
6682
6682
};
6683
6683
EXPORT_SYMBOL_GPL(ata_dummy_port_info);
6684
6684
6685
-
void ata_print_version(const struct device *dev, const char *version)
6686
-
{
6687
-
dev_printk(KERN_DEBUG, dev, "version %s\n", version);
6688
-
}
6689
-
EXPORT_SYMBOL(ata_print_version);
6690
-
6691
6685
EXPORT_TRACEPOINT_SYMBOL_GPL(ata_tf_load);
6692
6686
EXPORT_TRACEPOINT_SYMBOL_GPL(ata_exec_command);
6693
6687
EXPORT_TRACEPOINT_SYMBOL_GPL(ata_bmdma_setup);
+26
-13
drivers/ata/libata-eh.c
+26
-13
drivers/ata/libata-eh.c
···
3432
3432
struct ata_eh_context *ehc = &link->eh_context;
3433
3433
struct ata_device *dev, *link_dev = NULL, *lpm_dev = NULL;
3434
3434
enum ata_lpm_policy old_policy = link->lpm_policy;
3435
-
bool no_dipm = link->ap->flags & ATA_FLAG_NO_DIPM;
3435
+
bool host_has_dipm = !(link->ap->flags & ATA_FLAG_NO_DIPM);
3436
3436
unsigned int hints = ATA_LPM_EMPTY | ATA_LPM_HIPM;
3437
3437
unsigned int err_mask;
3438
3438
int rc;
···
3443
3443
return 0;
3444
3444
3445
3445
/*
3446
-
* DIPM is enabled only for MIN_POWER as some devices
3447
-
* misbehave when the host NACKs transition to SLUMBER. Order
3448
-
* device and link configurations such that the host always
3449
-
* allows DIPM requests.
3446
+
* This function currently assumes that it will never be supplied policy
3447
+
* ATA_LPM_UNKNOWN.
3448
+
*/
3449
+
if (WARN_ON_ONCE(policy == ATA_LPM_UNKNOWN))
3450
+
return 0;
3451
+
3452
+
/*
3453
+
* DIPM is enabled only for ATA_LPM_MIN_POWER,
3454
+
* ATA_LPM_MIN_POWER_WITH_PARTIAL, and ATA_LPM_MED_POWER_WITH_DIPM, as
3455
+
* some devices misbehave when the host NACKs transition to SLUMBER.
3450
3456
*/
3451
3457
ata_for_each_dev(dev, link, ENABLED) {
3452
-
bool hipm = ata_id_has_hipm(dev->id);
3453
-
bool dipm = ata_id_has_dipm(dev->id) && !no_dipm;
3458
+
bool dev_has_hipm = ata_id_has_hipm(dev->id);
3459
+
bool dev_has_dipm = ata_id_has_dipm(dev->id);
3454
3460
3455
3461
/* find the first enabled and LPM enabled devices */
3456
3462
if (!link_dev)
3457
3463
link_dev = dev;
3458
3464
3459
-
if (!lpm_dev && (hipm || dipm))
3465
+
if (!lpm_dev &&
3466
+
(dev_has_hipm || (dev_has_dipm && host_has_dipm)))
3460
3467
lpm_dev = dev;
3461
3468
3462
3469
hints &= ~ATA_LPM_EMPTY;
3463
-
if (!hipm)
3470
+
if (!dev_has_hipm)
3464
3471
hints &= ~ATA_LPM_HIPM;
3465
3472
3466
3473
/* disable DIPM before changing link config */
3467
-
if (policy < ATA_LPM_MED_POWER_WITH_DIPM && dipm) {
3474
+
if (dev_has_dipm) {
3468
3475
err_mask = ata_dev_set_feature(dev,
3469
3476
SETFEATURES_SATA_DISABLE, SATA_DIPM);
3470
3477
if (err_mask && err_mask != AC_ERR_DEV) {
···
3512
3505
if (ap && ap->slave_link)
3513
3506
ap->slave_link->lpm_policy = policy;
3514
3507
3515
-
/* host config updated, enable DIPM if transitioning to MIN_POWER */
3508
+
/*
3509
+
* Host config updated, enable DIPM if transitioning to
3510
+
* ATA_LPM_MIN_POWER, ATA_LPM_MIN_POWER_WITH_PARTIAL, or
3511
+
* ATA_LPM_MED_POWER_WITH_DIPM.
3512
+
*/
3516
3513
ata_for_each_dev(dev, link, ENABLED) {
3517
-
if (policy >= ATA_LPM_MED_POWER_WITH_DIPM && !no_dipm &&
3518
-
ata_id_has_dipm(dev->id)) {
3514
+
bool dev_has_dipm = ata_id_has_dipm(dev->id);
3515
+
3516
+
if (policy >= ATA_LPM_MED_POWER_WITH_DIPM && host_has_dipm &&
3517
+
dev_has_dipm) {
3519
3518
err_mask = ata_dev_set_feature(dev,
3520
3519
SETFEATURES_SATA_ENABLE, SATA_DIPM);
3521
3520
if (err_mask && err_mask != AC_ERR_DEV) {
+5
-7
drivers/ata/libata-sata.c
+5
-7
drivers/ata/libata-sata.c
···
1509
1509
struct ata_queued_cmd *qc;
1510
1510
unsigned int err_mask, tag;
1511
1511
u8 *sense, sk = 0, asc = 0, ascq = 0;
1512
-
u64 sense_valid, val;
1513
1512
u16 extended_sense;
1514
1513
bool aux_icc_valid;
1514
+
u32 sense_valid;
1515
+
u64 val;
1515
1516
int ret = 0;
1516
1517
1517
1518
err_mask = ata_read_log_page(dev, ATA_LOG_SENSE_NCQ, 0, buf, 2);
···
1530
1529
return -EIO;
1531
1530
}
1532
1531
1533
-
sense_valid = (u64)buf[8] | ((u64)buf[9] << 8) |
1534
-
((u64)buf[10] << 16) | ((u64)buf[11] << 24);
1532
+
sense_valid = get_unaligned_le32(&buf[8]);
1535
1533
extended_sense = get_unaligned_le16(&buf[14]);
1536
1534
aux_icc_valid = extended_sense & BIT(15);
1537
1535
···
1545
1545
* If the command does not have any sense data, clear ATA_SENSE.
1546
1546
* Keep ATA_QCFLAG_EH_SUCCESS_CMD so that command is finished.
1547
1547
*/
1548
-
if (!(sense_valid & (1ULL << tag))) {
1548
+
if (!(sense_valid & BIT(tag))) {
1549
1549
qc->result_tf.status &= ~ATA_SENSE;
1550
1550
continue;
1551
1551
}
···
1634
1634
return;
1635
1635
}
1636
1636
1637
-
if (!(link->sactive & (1 << tag))) {
1637
+
if (!(link->sactive & BIT(tag))) {
1638
1638
ata_link_err(link, "log page 10h reported inactive tag %d\n",
1639
1639
tag);
1640
1640
return;
···
1659
1659
if (ata_scsi_sense_is_valid(sense_key, asc, ascq)) {
1660
1660
ata_scsi_set_sense(dev, qc->scsicmd, sense_key, asc,
1661
1661
ascq);
1662
-
ata_scsi_set_sense_information(dev, qc->scsicmd,
1663
-
&qc->result_tf);
1664
1662
qc->flags |= ATA_QCFLAG_SENSE_VALID;
1665
1663
}
1666
1664
}
+14
-17
drivers/ata/libata-scsi.c
+14
-17
drivers/ata/libata-scsi.c
···
216
216
scsi_build_sense(cmd, d_sense, sk, asc, ascq);
217
217
}
218
218
219
-
void ata_scsi_set_sense_information(struct ata_device *dev,
220
-
struct scsi_cmnd *cmd,
221
-
const struct ata_taskfile *tf)
219
+
static void ata_scsi_set_sense_information(struct ata_queued_cmd *qc)
222
220
{
223
221
u64 information;
224
222
225
-
information = ata_tf_read_block(tf, dev);
223
+
if (!(qc->flags & ATA_QCFLAG_RTF_FILLED)) {
224
+
ata_dev_dbg(qc->dev,
225
+
"missing result TF: can't set INFORMATION sense field\n");
226
+
return;
227
+
}
228
+
229
+
information = ata_tf_read_block(&qc->result_tf, qc->dev);
226
230
if (information == U64_MAX)
227
231
return;
228
232
229
-
scsi_set_sense_information(cmd->sense_buffer,
233
+
scsi_set_sense_information(qc->scsicmd->sense_buffer,
230
234
SCSI_SENSE_BUFFERSIZE, information);
231
235
}
232
236
···
975
971
* ata_gen_ata_sense - generate a SCSI fixed sense block
976
972
* @qc: Command that we are erroring out
977
973
*
978
-
* Generate sense block for a failed ATA command @qc. Descriptor
979
-
* format is used to accommodate LBA48 block address.
974
+
* Generate sense block for a failed ATA command @qc.
980
975
*
981
976
* LOCKING:
982
977
* None.
···
985
982
struct ata_device *dev = qc->dev;
986
983
struct scsi_cmnd *cmd = qc->scsicmd;
987
984
struct ata_taskfile *tf = &qc->result_tf;
988
-
unsigned char *sb = cmd->sense_buffer;
989
-
u64 block;
990
985
u8 sense_key, asc, ascq;
991
986
992
987
if (ata_dev_disabled(dev)) {
···
1015
1014
ata_scsi_set_sense(dev, cmd, ABORTED_COMMAND, 0, 0);
1016
1015
return;
1017
1016
}
1018
-
1019
-
block = ata_tf_read_block(&qc->result_tf, dev);
1020
-
if (block == U64_MAX)
1021
-
return;
1022
-
1023
-
scsi_set_sense_information(sb, SCSI_SENSE_BUFFERSIZE, block);
1024
1017
}
1025
1018
1026
1019
void ata_scsi_sdev_config(struct scsi_device *sdev)
···
1674
1679
ata_scsi_set_passthru_sense_fields(qc);
1675
1680
if (is_ck_cond_request)
1676
1681
set_status_byte(qc->scsicmd, SAM_STAT_CHECK_CONDITION);
1677
-
} else if (is_error && !have_sense) {
1678
-
ata_gen_ata_sense(qc);
1682
+
} else if (is_error) {
1683
+
if (!have_sense)
1684
+
ata_gen_ata_sense(qc);
1685
+
ata_scsi_set_sense_information(qc);
1679
1686
}
1680
1687
1681
1688
ata_qc_done(qc);
-3
drivers/ata/libata.h
-3
drivers/ata/libata.h
···
141
141
extern bool ata_scsi_sense_is_valid(u8 sk, u8 asc, u8 ascq);
142
142
extern void ata_scsi_set_sense(struct ata_device *dev,
143
143
struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq);
144
-
extern void ata_scsi_set_sense_information(struct ata_device *dev,
145
-
struct scsi_cmnd *cmd,
146
-
const struct ata_taskfile *tf);
147
144
extern void ata_scsi_media_change_notify(struct ata_device *dev);
148
145
extern void ata_scsi_hotplug(struct work_struct *work);
149
146
extern void ata_scsi_dev_rescan(struct work_struct *work);
+15
-15
drivers/ata/sata_sx4.c
+15
-15
drivers/ata/sata_sx4.c
···
1301
1301
}
1302
1302
1303
1303
if (dimm_test) {
1304
-
u8 test_parttern1[40] =
1304
+
u8 test_pattern1[40] =
1305
1305
{0x55,0xAA,'P','r','o','m','i','s','e',' ',
1306
1306
'N','o','t',' ','Y','e','t',' ',
1307
1307
'D','e','f','i','n','e','d',' ',
1308
1308
'1','.','1','0',
1309
1309
'9','8','0','3','1','6','1','2',0,0};
1310
-
u8 test_parttern2[40] = {0};
1310
+
u8 test_pattern2[40] = {0};
1311
1311
1312
-
pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1313
-
pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1312
+
pdc20621_put_to_dimm(host, test_pattern2, 0x10040, 40);
1313
+
pdc20621_put_to_dimm(host, test_pattern2, 0x40, 40);
1314
1314
1315
-
pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1316
-
pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1317
-
dev_info(host->dev, "DIMM test pattern 1: %x, %x, %s\n", test_parttern2[0],
1318
-
test_parttern2[1], &(test_parttern2[2]));
1319
-
pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1315
+
pdc20621_put_to_dimm(host, test_pattern1, 0x10040, 40);
1316
+
pdc20621_get_from_dimm(host, test_pattern2, 0x40, 40);
1317
+
dev_info(host->dev, "DIMM test pattern 1: %x, %x, %s\n", test_pattern2[0],
1318
+
test_pattern2[1], &(test_pattern2[2]));
1319
+
pdc20621_get_from_dimm(host, test_pattern2, 0x10040,
1320
1320
40);
1321
1321
dev_info(host->dev, "DIMM test pattern 2: %x, %x, %s\n",
1322
-
test_parttern2[0],
1323
-
test_parttern2[1], &(test_parttern2[2]));
1322
+
test_pattern2[0],
1323
+
test_pattern2[1], &(test_pattern2[2]));
1324
1324
1325
-
pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1326
-
pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1325
+
pdc20621_put_to_dimm(host, test_pattern1, 0x40, 40);
1326
+
pdc20621_get_from_dimm(host, test_pattern2, 0x40, 40);
1327
1327
dev_info(host->dev, "DIMM test pattern 3: %x, %x, %s\n",
1328
-
test_parttern2[0],
1329
-
test_parttern2[1], &(test_parttern2[2]));
1328
+
test_pattern2[0],
1329
+
test_pattern2[1], &(test_pattern2[2]));
1330
1330
}
1331
1331
1332
1332
/* ECC initiliazation. */
+7
-12
include/linux/libata.h
+7
-12
include/linux/libata.h
···
41
41
*/
42
42
#undef ATA_IRQ_TRAP /* define to ack screaming irqs */
43
43
44
-
45
-
#define ata_print_version_once(dev, version) \
46
-
({ \
47
-
static bool __print_once; \
48
-
\
49
-
if (!__print_once) { \
50
-
__print_once = true; \
51
-
ata_print_version(dev, version); \
52
-
} \
53
-
})
54
-
55
44
/* defines only for the constants which don't work well as enums */
56
45
#define ATA_TAG_POISON 0xfafbfcfdU
57
46
···
1582
1593
#define ata_dev_dbg(dev, fmt, ...) \
1583
1594
ata_dev_printk(debug, dev, fmt, ##__VA_ARGS__)
1584
1595
1585
-
void ata_print_version(const struct device *dev, const char *version);
1596
+
static inline void ata_print_version_once(const struct device *dev,
1597
+
const char *version)
1598
+
{
1599
+
dev_dbg_once(dev, "version %s\n", version);
1600
+
}
1586
1601
1587
1602
/*
1588
1603
* ata_eh_info helpers
···
1618
1625
{
1619
1626
ata_port_desc(ap, "irq %d", irq);
1620
1627
ata_port_desc(ap, "lpm-pol %d", ap->target_lpm_policy);
1628
+
if (ap->pflags & ATA_PFLAG_EXTERNAL)
1629
+
ata_port_desc(ap, "ext");
1621
1630
}
1622
1631
1623
1632
static inline bool ata_tag_internal(unsigned int tag)