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arm64: dts: lg: Add missing PL011 "uartclk"

The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
LG131x SoCs are missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Link: https://lore.kernel.org/r/20250609-dt-lg-fixes-v1-2-e210e797c2d7@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

authored by

Rob Herring (Arm) and committed by
Arnd Bergmann f060fee2 caec3157

+6 -6
+6 -6
arch/arm64/boot/dts/lg/lg131x.dtsi
··· 128 128 compatible = "arm,pl011", "arm,primecell"; 129 129 reg = <0x0 0xfe000000 0x1000>; 130 130 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 131 - clocks = <&clk_bus>; 132 - clock-names = "apb_pclk"; 131 + clocks = <&clk_bus>, <&clk_bus>; 132 + clock-names = "uartclk", "apb_pclk"; 133 133 status = "disabled"; 134 134 }; 135 135 uart1: serial@fe100000 { 136 136 compatible = "arm,pl011", "arm,primecell"; 137 137 reg = <0x0 0xfe100000 0x1000>; 138 138 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 - clocks = <&clk_bus>; 140 - clock-names = "apb_pclk"; 139 + clocks = <&clk_bus>, <&clk_bus>; 140 + clock-names = "uartclk", "apb_pclk"; 141 141 status = "disabled"; 142 142 }; 143 143 uart2: serial@fe200000 { 144 144 compatible = "arm,pl011", "arm,primecell"; 145 145 reg = <0x0 0xfe200000 0x1000>; 146 146 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 147 - clocks = <&clk_bus>; 148 - clock-names = "apb_pclk"; 147 + clocks = <&clk_bus>, <&clk_bus>; 148 + clock-names = "uartclk", "apb_pclk"; 149 149 status = "disabled"; 150 150 }; 151 151 spi0: spi@fe800000 {