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drm/xe/mtl: Fix PAT table coherency settings

Re-sync our MTL PAT table with the bspec. 1-way coherency should only
be set on table entry 3. We do not want an incorrect setting here to
accidentally paper over other bugs elsewhere in the driver.

Bspec: 45101
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-6-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

authored by

Matt Roper and committed by
Rodrigo Vivi f16a3f63 366974e4

+2 -2
+2 -2
drivers/gpu/drm/xe/xe_pat.c
··· 54 54 55 55 const u32 mtl_pat_table[] = { 56 56 [0] = MTL_PAT_0_WB, 57 - [1] = MTL_PAT_1_WT | MTL_2_COH_1W, 58 - [2] = MTL_PAT_3_UC | MTL_2_COH_1W, 57 + [1] = MTL_PAT_1_WT, 58 + [2] = MTL_PAT_3_UC, 59 59 [3] = MTL_PAT_0_WB | MTL_2_COH_1W, 60 60 [4] = MTL_PAT_0_WB | MTL_3_COH_2W, 61 61 };