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arm64: dts: qcom: msm8996: Add interconnect support

Add interconnect providers for the multiple NoCs available on the platform,
and assign interconnects used by some blocks.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211021132329.234942-6-y.oudjana@protonmail.com

authored by

Yassine Oudjana and committed by
Bjorn Andersson
f35aaef1 817c2f35

+93
+93
arch/arm64/boot/dts/qcom/msm8996.dtsi
··· 6 6 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 7 7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 + #include <dt-bindings/interconnect/qcom,msm8996.h> 9 10 #include <dt-bindings/power/qcom-rpmpd.h> 10 11 #include <dt-bindings/soc/qcom,apr.h> 11 12 #include <dt-bindings/thermal/thermal.h> ··· 692 691 clock-names = "cxo", "cxo2", "sleep_clk"; 693 692 }; 694 693 694 + bimc: interconnect@408000 { 695 + compatible = "qcom,msm8996-bimc"; 696 + reg = <0x00408000 0x5a000>; 697 + #interconnect-cells = <1>; 698 + clock-names = "bus", "bus_a"; 699 + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 700 + <&rpmcc RPM_SMD_BIMC_A_CLK>; 701 + }; 702 + 695 703 tsens0: thermal-sensor@4a9000 { 696 704 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 697 705 reg = <0x004a9000 0x1000>, /* TM */ ··· 743 733 clock-names = "iface", "bus", "core"; 744 734 dmas = <&cryptobam 6>, <&cryptobam 7>; 745 735 dma-names = "rx", "tx"; 736 + }; 737 + 738 + cnoc: interconnect@500000 { 739 + compatible = "qcom,msm8996-cnoc"; 740 + reg = <0x00500000 0x1000>; 741 + #interconnect-cells = <1>; 742 + clock-names = "bus", "bus_a"; 743 + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 744 + <&rpmcc RPM_SMD_CNOC_A_CLK>; 745 + }; 746 + 747 + snoc: interconnect@524000 { 748 + compatible = "qcom,msm8996-snoc"; 749 + reg = <0x00524000 0x1c000>; 750 + #interconnect-cells = <1>; 751 + clock-names = "bus", "bus_a"; 752 + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 753 + <&rpmcc RPM_SMD_SNOC_A_CLK>; 754 + }; 755 + 756 + a0noc: interconnect@543000 { 757 + compatible = "qcom,msm8996-a0noc"; 758 + reg = <0x00543000 0x6000>; 759 + #interconnect-cells = <1>; 760 + clock-names = "aggre0_snoc_axi", 761 + "aggre0_cnoc_ahb", 762 + "aggre0_noc_mpu_cfg"; 763 + clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 764 + <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 765 + <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 766 + power-domains = <&gcc AGGRE0_NOC_GDSC>; 767 + }; 768 + 769 + a1noc: interconnect@562000 { 770 + compatible = "qcom,msm8996-a1noc"; 771 + reg = <0x00562000 0x5000>; 772 + #interconnect-cells = <1>; 773 + clock-names = "bus", "bus_a"; 774 + clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 775 + <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 776 + }; 777 + 778 + a2noc: interconnect@583000 { 779 + compatible = "qcom,msm8996-a2noc"; 780 + reg = <0x00583000 0x7000>; 781 + #interconnect-cells = <1>; 782 + clock-names = "bus", "bus_a"; 783 + clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 784 + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 785 + }; 786 + 787 + mnoc: interconnect@5a4000 { 788 + compatible = "qcom,msm8996-mnoc"; 789 + reg = <0x005a4000 0x1c000>; 790 + #interconnect-cells = <1>; 791 + clock-names = "bus", "bus_a", "iface"; 792 + clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 793 + <&rpmcc RPM_SMD_MMAXI_A_CLK>, 794 + <&mmcc AHB_CLK_SRC>; 795 + }; 796 + 797 + pnoc: interconnect@5c0000 { 798 + compatible = "qcom,msm8996-pnoc"; 799 + reg = <0x005c0000 0x3000>; 800 + #interconnect-cells = <1>; 801 + clock-names = "bus", "bus_a"; 802 + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 803 + <&rpmcc RPM_SMD_PCNOC_A_CLK>; 746 804 }; 747 805 748 806 tcsr_mutex_regs: syscon@740000 { ··· 908 830 <&mmcc MDSS_VSYNC_CLK>; 909 831 assigned-clock-rates = <300000000>, 910 832 <19200000>; 833 + 834 + interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 835 + <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 836 + <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 837 + interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 911 838 912 839 ports { 913 840 #address-cells = <1>; ··· 1159 1076 "rbbmtimer", 1160 1077 "mem", 1161 1078 "mem_iface"; 1079 + 1080 + interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1081 + interconnect-names = "gfx-mem"; 1162 1082 1163 1083 power-domains = <&mmcc GPU_GX_GDSC>; 1164 1084 iommus = <&adreno_smmu 0>; ··· 2188 2102 <&mmcc VIDEO_AXI_CLK>, 2189 2103 <&mmcc VIDEO_MAXI_CLK>; 2190 2104 clock-names = "core", "iface", "bus", "mbus"; 2105 + interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2106 + <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2107 + interconnect-names = "video-mem", "cpu-cfg"; 2191 2108 iommus = <&venus_smmu 0x00>, 2192 2109 <&venus_smmu 0x01>, 2193 2110 <&venus_smmu 0x0a>, ··· 2909 2820 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2910 2821 <&gcc GCC_USB30_MASTER_CLK>; 2911 2822 assigned-clock-rates = <19200000>, <120000000>; 2823 + 2824 + interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2825 + <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2826 + interconnect-names = "usb-ddr", "apps-usb"; 2912 2827 2913 2828 power-domains = <&gcc USB30_GDSC>; 2914 2829 status = "disabled";