tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()

Along with the introduction Perfmon v6, pmu counters could be
incontinuous, like fixed counters on CWF, only fixed counters 0-3 and
5-7 are supported, there is no fixed counter 4 on CWF. To accommodate
this change, archPerfmonExt CPUID (0x23) leaves are introduced to
enumerate the true-view of counters bitmap.

Current perf code already supports archPerfmonExt CPUID and uses
counters-bitmap to enumerate HW really supported counters, but
x86_pmu_show_pmu_cap() still only dumps the absolute counter number
instead of true-view bitmap, it's out-dated and may mislead readers.

So dump counters true-view bitmap in x86_pmu_show_pmu_cap() and
opportunistically change the dump sequence and words.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-8-dapeng1.mi@linux.intel.com

authored by

Dapeng Mi and committed by
Peter Zijlstra f49e1be1 2676dbf9

+9 -7
+9 -7
arch/x86/events/core.c
··· 2069 2069 2070 2070 void x86_pmu_show_pmu_cap(struct pmu *pmu) 2071 2071 { 2072 - pr_info("... version: %d\n", x86_pmu.version); 2073 - pr_info("... bit width: %d\n", x86_pmu.cntval_bits); 2074 - pr_info("... generic registers: %d\n", x86_pmu_num_counters(pmu)); 2075 - pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); 2076 - pr_info("... max period: %016Lx\n", x86_pmu.max_period); 2077 - pr_info("... fixed-purpose events: %d\n", x86_pmu_num_counters_fixed(pmu)); 2078 - pr_info("... event mask: %016Lx\n", hybrid(pmu, intel_ctrl)); 2072 + pr_info("... version: %d\n", x86_pmu.version); 2073 + pr_info("... bit width: %d\n", x86_pmu.cntval_bits); 2074 + pr_info("... generic counters: %d\n", x86_pmu_num_counters(pmu)); 2075 + pr_info("... generic bitmap: %016llx\n", hybrid(pmu, cntr_mask64)); 2076 + pr_info("... fixed-purpose counters: %d\n", x86_pmu_num_counters_fixed(pmu)); 2077 + pr_info("... fixed-purpose bitmap: %016llx\n", hybrid(pmu, fixed_cntr_mask64)); 2078 + pr_info("... value mask: %016llx\n", x86_pmu.cntval_mask); 2079 + pr_info("... max period: %016llx\n", x86_pmu.max_period); 2080 + pr_info("... global_ctrl mask: %016llx\n", hybrid(pmu, intel_ctrl)); 2079 2081 } 2080 2082 2081 2083 static int __init init_hw_perf_events(void)