Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.20, version 3
- dt-bindings updates:
- Add intel,socfpga-agilex5-socdk-modular for the Agilex5 mod board
- Add intel,socfpga-agilex-emmc for the Agilex eMMC daughter board
- Move entries in intel,socfpga.yaml into altera.yaml
- Add syscon as a fallback for sys-mgr
- Add dma-cohrerent property for Agilex5 NAND and DMA
- Add support for the Agilex5 modular board
- Add IOMMUS property for ethernet nodes for Agilex5
- Use lowercase hex for dts files
- Add #address-cells and #size-cells for sram
- Fix dtbs_check warning for fpga-region
- Move dma controller node for Agilex5 under simple-bus
- Add support for the Agilex eMMC daughter board
* tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
dt-bindings: intel: Add Agilex eMMC support
arm64: dts: socfpga: agilex: add emmc support
arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
ARM: dts: socfpga: fix dtbs_check warning for fpga-region
ARM: dts: socfpga: add #address-cells and #size-cells for sram node
dt-bindings: altera: document syscon as fallback for sys-mgr
arm64: dts: altera: Use lowercase hex
dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
arm64: dts: socfpga: agilex5: add support for modular board
dt-bindings: intel: Add Agilex5 SoCFPGA modular board
arm64: dts: socfpga: agilex5: Add dma-coherent property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+335
-108
+27
Documentation/devicetree/bindings/arm/altera.yaml
+27
Documentation/devicetree/bindings/arm/altera.yaml
···
9
9
maintainers:
10
10
- Dinh Nguyen <dinguyen@kernel.org>
11
11
12
+
description:
13
+
Altera/Intel boards with ARM 32/64 bits cores
14
+
12
15
properties:
13
16
$nodename:
14
17
const: "/"
···
83
80
- altr,socfpga-stratix10-socdk
84
81
- altr,socfpga-stratix10-swvp
85
82
- const: altr,socfpga-stratix10
83
+
84
+
- description: AgileX boards
85
+
items:
86
+
- enum:
87
+
- intel,n5x-socdk
88
+
- intel,socfpga-agilex-n6000
89
+
- intel,socfpga-agilex-socdk
90
+
- intel,socfpga-agilex-socdk-emmc
91
+
- const: intel,socfpga-agilex
92
+
93
+
- description: Agilex3 boards
94
+
items:
95
+
- enum:
96
+
- intel,socfpga-agilex3-socdk
97
+
- const: intel,socfpga-agilex3
98
+
- const: intel,socfpga-agilex5
99
+
100
+
- description: Agilex5 boards
101
+
items:
102
+
- enum:
103
+
- intel,socfpga-agilex5-socdk
104
+
- intel,socfpga-agilex5-socdk-013b
105
+
- intel,socfpga-agilex5-socdk-nand
106
+
- const: intel,socfpga-agilex5
86
107
87
108
- description: SoCFPGA VT
88
109
items:
-40
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
-40
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Intel SoCFPGA platform
8
-
9
-
maintainers:
10
-
- Dinh Nguyen <dinguyen@kernel.org>
11
-
12
-
properties:
13
-
$nodename:
14
-
const: "/"
15
-
compatible:
16
-
oneOf:
17
-
- description: AgileX boards
18
-
items:
19
-
- enum:
20
-
- intel,n5x-socdk
21
-
- intel,socfpga-agilex-n6000
22
-
- intel,socfpga-agilex-socdk
23
-
- const: intel,socfpga-agilex
24
-
- description: Agilex3 boards
25
-
items:
26
-
- enum:
27
-
- intel,socfpga-agilex3-socdk
28
-
- const: intel,socfpga-agilex3
29
-
- const: intel,socfpga-agilex5
30
-
- description: Agilex5 boards
31
-
items:
32
-
- enum:
33
-
- intel,socfpga-agilex5-socdk
34
-
- intel,socfpga-agilex5-socdk-013b
35
-
- intel,socfpga-agilex5-socdk-nand
36
-
- const: intel,socfpga-agilex5
37
-
38
-
additionalProperties: true
39
-
40
-
...
+4
-2
Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml
+4
-2
Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml
···
13
13
compatible:
14
14
oneOf:
15
15
- description: Cyclone5/Arria5/Arria10
16
-
const: altr,sys-mgr
16
+
items:
17
+
- const: altr,sys-mgr
18
+
- const: syscon
17
19
- description: Stratix10 SoC
18
20
items:
19
21
- const: altr,sys-mgr-s10
···
47
45
examples:
48
46
- |
49
47
sysmgr@ffd08000 {
50
-
compatible = "altr,sys-mgr";
48
+
compatible = "altr,sys-mgr", "syscon";
51
49
reg = <0xffd08000 0x1000>;
52
50
cpu1-start-addr = <0xffd080c4>;
53
51
};
+5
-1
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
+5
-1
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
···
87
87
};
88
88
};
89
89
90
-
base_fpga_region {
90
+
base_fpga_region: fpga-region {
91
91
compatible = "fpga-region";
92
92
fpga-mgr = <&fpgamgr0>;
93
93
94
94
#address-cells = <0x1>;
95
95
#size-cells = <0x1>;
96
+
ranges;
96
97
};
97
98
98
99
can0: can@ffc00000 {
···
786
785
ocram: sram@ffff0000 {
787
786
compatible = "mmio-sram";
788
787
reg = <0xffff0000 0x10000>;
788
+
#address-cells = <0x1>;
789
+
#size-cells = <0x1>;
790
+
ranges;
789
791
};
790
792
791
793
qspi: spi@ff705000 {
+5
-1
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
+5
-1
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
···
80
80
};
81
81
};
82
82
83
-
base_fpga_region {
83
+
base_fpga_region: fpga-region {
84
84
#address-cells = <0x1>;
85
85
#size-cells = <0x1>;
86
86
87
87
compatible = "fpga-region";
88
88
fpga-mgr = <&fpga_mgr>;
89
+
ranges;
89
90
};
90
91
91
92
clkmgr@ffd04000 {
···
687
686
ocram: sram@ffe00000 {
688
687
compatible = "mmio-sram";
689
688
reg = <0xffe00000 0x40000>;
689
+
#address-cells = <1>;
690
+
#size-cells = <1>;
691
+
ranges;
690
692
};
691
693
692
694
eccmgr: eccmgr {
+1
-1
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+1
-1
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+1
-1
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+1
-1
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+2
-2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+2
-2
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
···
174
174
175
175
qspi_boot: partition@0 {
176
176
label = "Boot and fpga data";
177
-
reg = <0x0 0x03FE0000>;
177
+
reg = <0x0 0x03fe0000>;
178
178
};
179
179
180
180
qspi_rootfs: partition@3fe0000 {
181
181
label = "Root Filesystem - JFFS2";
182
-
reg = <0x03FE0000 0x0C020000>;
182
+
reg = <0x03fe0000 0x0c020000>;
183
183
};
184
184
};
185
185
};
+2
arch/arm64/boot/dts/intel/Makefile
+2
arch/arm64/boot/dts/intel/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0-only
2
2
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
3
3
socfpga_agilex_socdk.dtb \
4
+
socfpga_agilex_socdk_emmc.dtb \
4
5
socfpga_agilex_socdk_nand.dtb \
5
6
socfpga_agilex3_socdk.dtb \
6
7
socfpga_agilex5_socdk.dtb \
7
8
socfpga_agilex5_socdk_013b.dtb \
9
+
socfpga_agilex5_socdk_modular.dtb \
8
10
socfpga_agilex5_socdk_nand.dtb \
9
11
socfpga_n5x_socdk.dtb
10
12
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
+71
-57
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+71
-57
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
···
312
312
clock-names = "nf_clk";
313
313
cdns,board-delay-ps = <4830>;
314
314
iommus = <&smmu 4>;
315
+
dma-coherent;
315
316
status = "disabled";
316
317
};
317
318
···
324
323
#size-cells = <1>;
325
324
};
326
325
327
-
dmac0: dma-controller@10db0000 {
328
-
compatible = "snps,axi-dma-1.01a";
329
-
reg = <0x10db0000 0x500>;
330
-
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
331
-
<&clkmgr AGILEX5_L4_MP_CLK>;
332
-
clock-names = "core-clk", "cfgr-clk";
333
-
interrupt-parent = <&intc>;
334
-
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
335
-
#dma-cells = <1>;
336
-
dma-channels = <4>;
337
-
snps,dma-masters = <1>;
338
-
snps,data-width = <2>;
339
-
snps,block-size = <32767 32767 32767 32767>;
340
-
snps,priority = <0 1 2 3>;
341
-
snps,axi-max-burst-len = <8>;
342
-
iommus = <&smmu 8>;
343
-
};
326
+
dma: dma-bus@10db0000 {
327
+
compatible = "simple-bus";
328
+
#address-cells = <1>;
329
+
#size-cells = <2>;
330
+
ranges = <0x00 0x10db0000 0x00 0x20000>;
331
+
dma-ranges = <0x00 0x00 0x100 0x00>;
344
332
345
-
dmac1: dma-controller@10dc0000 {
346
-
compatible = "snps,axi-dma-1.01a";
347
-
reg = <0x10dc0000 0x500>;
348
-
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
349
-
<&clkmgr AGILEX5_L4_MP_CLK>;
350
-
clock-names = "core-clk", "cfgr-clk";
351
-
interrupt-parent = <&intc>;
352
-
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
353
-
#dma-cells = <1>;
354
-
dma-channels = <4>;
355
-
snps,dma-masters = <1>;
356
-
snps,data-width = <2>;
357
-
snps,block-size = <32767 32767 32767 32767>;
358
-
snps,priority = <0 1 2 3>;
359
-
snps,axi-max-burst-len = <8>;
360
-
iommus = <&smmu 9>;
333
+
dmac0: dma-controller@0 {
334
+
compatible = "altr,agilex5-axi-dma",
335
+
"snps,axi-dma-1.01a";
336
+
reg = <0x0 0x0 0x500>;
337
+
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
338
+
<&clkmgr AGILEX5_L4_MP_CLK>;
339
+
clock-names = "core-clk", "cfgr-clk";
340
+
interrupt-parent = <&intc>;
341
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
342
+
#dma-cells = <1>;
343
+
dma-channels = <4>;
344
+
snps,dma-masters = <1>;
345
+
snps,data-width = <2>;
346
+
snps,block-size = <32767 32767 32767 32767>;
347
+
snps,priority = <0 1 2 3>;
348
+
snps,axi-max-burst-len = <8>;
349
+
iommus = <&smmu 8>;
350
+
};
351
+
352
+
dmac1: dma-controller@10000 {
353
+
compatible = "altr,agilex5-axi-dma",
354
+
"snps,axi-dma-1.01a";
355
+
reg = <0x10000 0x0 0x500>;
356
+
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
357
+
<&clkmgr AGILEX5_L4_MP_CLK>;
358
+
clock-names = "core-clk", "cfgr-clk";
359
+
interrupt-parent = <&intc>;
360
+
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
361
+
#dma-cells = <1>;
362
+
dma-channels = <4>;
363
+
snps,dma-masters = <1>;
364
+
snps,data-width = <2>;
365
+
snps,block-size = <32767 32767 32767 32767>;
366
+
snps,priority = <0 1 2 3>;
367
+
snps,axi-max-burst-len = <8>;
368
+
iommus = <&smmu 9>;
369
+
};
361
370
};
362
371
363
372
rst: rstmgr@10d11000 {
···
576
565
snps,tso;
577
566
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
578
567
snps,clk-csr = <0>;
568
+
iommus = <&smmu 1>;
579
569
status = "disabled";
580
570
581
571
stmmac_axi_emac0_setup: stmmac-axi-config {
···
630
618
snps,dcb-algorithm;
631
619
};
632
620
queue1 {
633
-
snps,weight = <0x0A>;
621
+
snps,weight = <0x0a>;
634
622
snps,dcb-algorithm;
635
623
};
636
624
queue2 {
637
-
snps,weight = <0x0B>;
625
+
snps,weight = <0x0b>;
638
626
snps,coe-unsupported;
639
627
snps,dcb-algorithm;
640
628
};
641
629
queue3 {
642
-
snps,weight = <0x0C>;
630
+
snps,weight = <0x0c>;
643
631
snps,coe-unsupported;
644
632
snps,dcb-algorithm;
645
633
};
646
634
queue4 {
647
-
snps,weight = <0x0D>;
635
+
snps,weight = <0x0d>;
648
636
snps,coe-unsupported;
649
637
snps,dcb-algorithm;
650
638
};
651
639
queue5 {
652
-
snps,weight = <0x0E>;
640
+
snps,weight = <0x0e>;
653
641
snps,coe-unsupported;
654
642
snps,dcb-algorithm;
655
643
};
656
644
queue6 {
657
-
snps,weight = <0x0F>;
645
+
snps,weight = <0x0f>;
658
646
snps,coe-unsupported;
659
647
snps,dcb-algorithm;
660
648
};
···
689
677
snps,tso;
690
678
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
691
679
snps,clk-csr = <0>;
680
+
iommus = <&smmu 2>;
692
681
status = "disabled";
693
682
694
683
stmmac_axi_emac1_setup: stmmac-axi-config {
···
743
730
snps,dcb-algorithm;
744
731
};
745
732
queue1 {
746
-
snps,weight = <0x0A>;
733
+
snps,weight = <0x0a>;
747
734
snps,dcb-algorithm;
748
735
};
749
736
queue2 {
750
-
snps,weight = <0x0B>;
737
+
snps,weight = <0x0b>;
751
738
snps,coe-unsupported;
752
739
snps,dcb-algorithm;
753
740
};
754
741
queue3 {
755
-
snps,weight = <0x0C>;
742
+
snps,weight = <0x0c>;
756
743
snps,coe-unsupported;
757
744
snps,dcb-algorithm;
758
745
};
759
746
queue4 {
760
-
snps,weight = <0x0D>;
747
+
snps,weight = <0x0d>;
761
748
snps,coe-unsupported;
762
749
snps,dcb-algorithm;
763
750
};
764
751
queue5 {
765
-
snps,weight = <0x0E>;
752
+
snps,weight = <0x0e>;
766
753
snps,coe-unsupported;
767
754
snps,dcb-algorithm;
768
755
};
769
756
queue6 {
770
-
snps,weight = <0x0F>;
757
+
snps,weight = <0x0f>;
771
758
snps,coe-unsupported;
772
759
snps,dcb-algorithm;
773
760
};
···
802
789
snps,tso;
803
790
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
804
791
snps,clk-csr = <0>;
792
+
iommus = <&smmu 3>;
805
793
status = "disabled";
806
794
807
795
stmmac_axi_emac2_setup: stmmac-axi-config {
···
856
842
snps,dcb-algorithm;
857
843
};
858
844
queue1 {
859
-
snps,weight = <0x0A>;
845
+
snps,weight = <0x0a>;
860
846
snps,dcb-algorithm;
861
847
};
862
848
queue2 {
863
-
snps,weight = <0x0B>;
849
+
snps,weight = <0x0b>;
864
850
snps,coe-unsupported;
865
851
snps,dcb-algorithm;
866
852
};
867
853
queue3 {
868
-
snps,weight = <0x0C>;
854
+
snps,weight = <0x0c>;
869
855
snps,coe-unsupported;
870
856
snps,dcb-algorithm;
871
857
};
872
858
queue4 {
873
-
snps,weight = <0x0D>;
859
+
snps,weight = <0x0d>;
874
860
snps,coe-unsupported;
875
861
snps,dcb-algorithm;
876
862
};
877
863
queue5 {
878
-
snps,weight = <0x0E>;
864
+
snps,weight = <0x0e>;
879
865
snps,coe-unsupported;
880
866
snps,dcb-algorithm;
881
867
};
882
868
queue6 {
883
-
snps,weight = <0x0F>;
869
+
snps,weight = <0x0f>;
884
870
snps,coe-unsupported;
885
871
snps,dcb-algorithm;
886
872
};
···
926
912
927
913
pmu0_tbu3: pmu@160a2000 {
928
914
compatible = "arm,smmu-v3-pmcg";
929
-
reg = <0x160A2000 0x1000>,
930
-
<0x160B2000 0x1000>;
915
+
reg = <0x160a2000 0x1000>,
916
+
<0x160b2000 0x1000>;
931
917
interrupt-parent = <&intc>;
932
918
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
933
919
};
934
920
935
921
pmu0_tbu4: pmu@160c2000 {
936
922
compatible = "arm,smmu-v3-pmcg";
937
-
reg = <0x160C2000 0x1000>,
938
-
<0x160D2000 0x1000>;
923
+
reg = <0x160c2000 0x1000>,
924
+
<0x160d2000 0x1000>;
939
925
interrupt-parent = <&intc>;
940
926
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
941
927
};
942
928
943
929
pmu0_tbu5: pmu@160e2000 {
944
930
compatible = "arm,smmu-v3-pmcg";
945
-
reg = <0x160E2000 0x1000>,
946
-
<0x160F2000 0x1000>;
931
+
reg = <0x160e2000 0x1000>,
932
+
<0x160f2000 0x1000>;
947
933
interrupt-parent = <&intc>;
948
934
interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
949
935
};
+109
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+109
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025, Altera Corporation
4
+
*/
5
+
#include "socfpga_agilex5.dtsi"
6
+
7
+
/ {
8
+
model = "SoCFPGA Agilex5 SoCDK - Modular development kit";
9
+
compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5";
10
+
11
+
aliases {
12
+
serial0 = &uart0;
13
+
ethernet2 = &gmac2;
14
+
};
15
+
16
+
chosen {
17
+
stdout-path = "serial0:115200n8";
18
+
};
19
+
20
+
leds {
21
+
compatible = "gpio-leds";
22
+
23
+
led0 {
24
+
label = "hps_led0";
25
+
gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>;
26
+
linux,default-trigger = "heartbeat";
27
+
};
28
+
};
29
+
30
+
memory@80000000 {
31
+
device_type = "memory";
32
+
/* We expect the bootloader to fill in the reg */
33
+
reg = <0x0 0x80000000 0x0 0x0>;
34
+
};
35
+
};
36
+
37
+
&gpio0 {
38
+
status = "okay";
39
+
};
40
+
41
+
&gpio1 {
42
+
status = "okay";
43
+
};
44
+
45
+
&gmac2 {
46
+
status = "okay";
47
+
phy-mode = "rgmii-id";
48
+
phy-handle = <&emac2_phy0>;
49
+
max-frame-size = <9000>;
50
+
51
+
mdio0 {
52
+
compatible = "snps,dwmac-mdio";
53
+
#address-cells = <1>;
54
+
#size-cells = <0>;
55
+
56
+
emac2_phy0: ethernet-phy@0 {
57
+
reg = <0>;
58
+
};
59
+
};
60
+
};
61
+
62
+
&osc1 {
63
+
clock-frequency = <25000000>;
64
+
};
65
+
66
+
&qspi {
67
+
status = "okay";
68
+
flash@0 {
69
+
compatible = "micron,mt25qu02g", "jedec,spi-nor";
70
+
reg = <0>;
71
+
spi-max-frequency = <100000000>;
72
+
m25p,fast-read;
73
+
cdns,read-delay = <2>;
74
+
cdns,tshsl-ns = <50>;
75
+
cdns,tsd2d-ns = <50>;
76
+
cdns,tchsh-ns = <4>;
77
+
cdns,tslch-ns = <4>;
78
+
spi-tx-bus-width = <4>;
79
+
spi-rx-bus-width = <4>;
80
+
81
+
partitions {
82
+
compatible = "fixed-partitions";
83
+
#address-cells = <1>;
84
+
#size-cells = <1>;
85
+
86
+
qspi_boot: partition@0 {
87
+
label = "u-boot";
88
+
reg = <0x0 0x04200000>;
89
+
};
90
+
91
+
root: partition@4200000 {
92
+
label = "root";
93
+
reg = <0x04200000 0x0be00000>;
94
+
};
95
+
};
96
+
};
97
+
};
98
+
99
+
&smmu {
100
+
status = "okay";
101
+
};
102
+
103
+
&uart0 {
104
+
status = "okay";
105
+
};
106
+
107
+
&watchdog0 {
108
+
status = "okay";
109
+
};
+1
-1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+1
-1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+105
arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts
+105
arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2026, Altera Corporation
4
+
*/
5
+
#include "socfpga_agilex.dtsi"
6
+
7
+
/ {
8
+
model = "SoCFPGA Agilex SoCDK eMMC daughter board";
9
+
compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex";
10
+
11
+
aliases {
12
+
serial0 = &uart0;
13
+
ethernet0 = &gmac0;
14
+
ethernet1 = &gmac1;
15
+
ethernet2 = &gmac2;
16
+
};
17
+
18
+
chosen {
19
+
stdout-path = "serial0:115200n8";
20
+
};
21
+
22
+
leds {
23
+
compatible = "gpio-leds";
24
+
led0 {
25
+
label = "hps_led0";
26
+
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
27
+
};
28
+
29
+
led1 {
30
+
label = "hps_led1";
31
+
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
32
+
};
33
+
34
+
led2 {
35
+
label = "hps_led2";
36
+
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
37
+
};
38
+
};
39
+
40
+
memory@80000000 {
41
+
device_type = "memory";
42
+
/* We expect the bootloader to fill in the reg */
43
+
reg = <0 0x80000000 0 0>;
44
+
};
45
+
};
46
+
47
+
&gpio1 {
48
+
status = "okay";
49
+
};
50
+
51
+
&gmac2 {
52
+
status = "okay";
53
+
/* PHY delays is configured via skew properties */
54
+
phy-mode = "rgmii";
55
+
phy-handle = <&phy0>;
56
+
57
+
max-frame-size = <9000>;
58
+
59
+
mdio0 {
60
+
#address-cells = <1>;
61
+
#size-cells = <0>;
62
+
compatible = "snps,dwmac-mdio";
63
+
phy0: ethernet-phy@4 {
64
+
reg = <4>;
65
+
66
+
txd0-skew-ps = <0>; /* -420ps */
67
+
txd1-skew-ps = <0>; /* -420ps */
68
+
txd2-skew-ps = <0>; /* -420ps */
69
+
txd3-skew-ps = <0>; /* -420ps */
70
+
rxd0-skew-ps = <420>; /* 0ps */
71
+
rxd1-skew-ps = <420>; /* 0ps */
72
+
rxd2-skew-ps = <420>; /* 0ps */
73
+
rxd3-skew-ps = <420>; /* 0ps */
74
+
txen-skew-ps = <0>; /* -420ps */
75
+
txc-skew-ps = <900>; /* 0ps */
76
+
rxdv-skew-ps = <420>; /* 0ps */
77
+
rxc-skew-ps = <1680>; /* 780ps */
78
+
};
79
+
};
80
+
};
81
+
82
+
&mmc {
83
+
status = "okay";
84
+
cap-mmc-highspeed;
85
+
broken-cd;
86
+
bus-width = <4>;
87
+
clk-phase-sd-hs = <0>, <135>;
88
+
};
89
+
90
+
&osc1 {
91
+
clock-frequency = <25000000>;
92
+
};
93
+
94
+
&uart0 {
95
+
status = "okay";
96
+
};
97
+
98
+
&usb0 {
99
+
status = "okay";
100
+
disable-over-current;
101
+
};
102
+
103
+
&watchdog0 {
104
+
status = "okay";
105
+
};
+2
-2
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+2
-2
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
···
103
103
104
104
qspi_boot: partition@0 {
105
105
label = "Boot and fpga data";
106
-
reg = <0x0 0x03FE0000>;
106
+
reg = <0x0 0x03fe0000>;
107
107
};
108
108
109
109
qspi_rootfs: partition@3fe0000 {
110
110
label = "Root Filesystem - JFFS2";
111
-
reg = <0x03FE0000 0x0C020000>;
111
+
reg = <0x03fe0000 0x0c020000>;
112
112
};
113
113
};
114
114
};