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spi: sh-msiof: Correct RX FIFO size for R-Car Gen3

According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 28, 2017, the MSIOF receive FIFOs on R-Car Gen3 SoCs have room
for 256 words of 32 bits.

Note that this change has no actual impact on the behavior of the
driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty
limited to the minimum of the transmit and receive FIFO sizes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/6f74508ea4681aa0b7c6bf6810eab026725e75a3.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown f669c282 1ab2c8c4

+2 -2
+2 -2
drivers/spi/spi-sh-msiof.c
··· 1108 1108 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1109 1109 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1110 1110 .tx_fifo_size = 64, 1111 - .rx_fifo_size = 64, 1111 + .rx_fifo_size = 256, 1112 1112 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1113 1113 .min_div_pow = 1, 1114 1114 }; ··· 1117 1117 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1118 1118 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1119 1119 .tx_fifo_size = 64, 1120 - .rx_fifo_size = 64, 1120 + .rx_fifo_size = 256, 1121 1121 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1122 1122 .min_div_pow = 1, 1123 1123 .flags = SH_MSIOF_FLAG_FIXED_DTDL_200,