drm/radeon: Add support for RLC init on CIK (v4)

+189

2 changed files

expand all

drivers

gpu

drm

radeon

cik.c

cikd.h

+142

drivers/gpu/drm/radeon/cik.c

··· 2777 2777 radeon_ring_write(ring, 0x0); 2778 2778 } 2779 2779 2780 + /* 2781 + * RLC 2782 + * The RLC is a multi-purpose microengine that handles a 2783 + * variety of functions, the most important of which is 2784 + * the interrupt controller. 2785 + */ 2786 + /** 2787 + * cik_rlc_stop - stop the RLC ME 2788 + * 2789 + * @rdev: radeon_device pointer 2790 + * 2791 + * Halt the RLC ME (MicroEngine) (CIK). 2792 + */ 2793 + static void cik_rlc_stop(struct radeon_device *rdev) 2794 + { 2795 + int i, j, k; 2796 + u32 mask, tmp; 2797 + 2798 + tmp = RREG32(CP_INT_CNTL_RING0); 2799 + tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2800 + WREG32(CP_INT_CNTL_RING0, tmp); 2801 + 2802 + RREG32(CB_CGTT_SCLK_CTRL); 2803 + RREG32(CB_CGTT_SCLK_CTRL); 2804 + RREG32(CB_CGTT_SCLK_CTRL); 2805 + RREG32(CB_CGTT_SCLK_CTRL); 2806 + 2807 + tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc; 2808 + WREG32(RLC_CGCG_CGLS_CTRL, tmp); 2809 + 2810 + WREG32(RLC_CNTL, 0); 2811 + 2812 + for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { 2813 + for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { 2814 + cik_select_se_sh(rdev, i, j); 2815 + for (k = 0; k < rdev->usec_timeout; k++) { 2816 + if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0) 2817 + break; 2818 + udelay(1); 2819 + } 2820 + } 2821 + } 2822 + cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); 2823 + 2824 + mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY; 2825 + for (k = 0; k < rdev->usec_timeout; k++) { 2826 + if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2827 + break; 2828 + udelay(1); 2829 + } 2830 + } 2831 + 2832 + /** 2833 + * cik_rlc_start - start the RLC ME 2834 + * 2835 + * @rdev: radeon_device pointer 2836 + * 2837 + * Unhalt the RLC ME (MicroEngine) (CIK). 2838 + */ 2839 + static void cik_rlc_start(struct radeon_device *rdev) 2840 + { 2841 + u32 tmp; 2842 + 2843 + WREG32(RLC_CNTL, RLC_ENABLE); 2844 + 2845 + tmp = RREG32(CP_INT_CNTL_RING0); 2846 + tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2847 + WREG32(CP_INT_CNTL_RING0, tmp); 2848 + 2849 + udelay(50); 2850 + } 2851 + 2852 + /** 2853 + * cik_rlc_resume - setup the RLC hw 2854 + * 2855 + * @rdev: radeon_device pointer 2856 + * 2857 + * Initialize the RLC registers, load the ucode, 2858 + * and start the RLC (CIK). 2859 + * Returns 0 for success, -EINVAL if the ucode is not available. 2860 + */ 2861 + static int cik_rlc_resume(struct radeon_device *rdev) 2862 + { 2863 + u32 i, size; 2864 + u32 clear_state_info[3]; 2865 + const __be32 *fw_data; 2866 + 2867 + if (!rdev->rlc_fw) 2868 + return -EINVAL; 2869 + 2870 + switch (rdev->family) { 2871 + case CHIP_BONAIRE: 2872 + default: 2873 + size = BONAIRE_RLC_UCODE_SIZE; 2874 + break; 2875 + case CHIP_KAVERI: 2876 + size = KV_RLC_UCODE_SIZE; 2877 + break; 2878 + case CHIP_KABINI: 2879 + size = KB_RLC_UCODE_SIZE; 2880 + break; 2881 + } 2882 + 2883 + cik_rlc_stop(rdev); 2884 + 2885 + WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC); 2886 + RREG32(GRBM_SOFT_RESET); 2887 + udelay(50); 2888 + WREG32(GRBM_SOFT_RESET, 0); 2889 + RREG32(GRBM_SOFT_RESET); 2890 + udelay(50); 2891 + 2892 + WREG32(RLC_LB_CNTR_INIT, 0); 2893 + WREG32(RLC_LB_CNTR_MAX, 0x00008000); 2894 + 2895 + cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); 2896 + WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); 2897 + WREG32(RLC_LB_PARAMS, 0x00600408); 2898 + WREG32(RLC_LB_CNTL, 0x80000004); 2899 + 2900 + WREG32(RLC_MC_CNTL, 0); 2901 + WREG32(RLC_UCODE_CNTL, 0); 2902 + 2903 + fw_data = (const __be32 *)rdev->rlc_fw->data; 2904 + WREG32(RLC_GPM_UCODE_ADDR, 0); 2905 + for (i = 0; i < size; i++) 2906 + WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); 2907 + WREG32(RLC_GPM_UCODE_ADDR, 0); 2908 + 2909 + /* XXX */ 2910 + clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr); 2911 + clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr; 2912 + clear_state_info[2] = 0;//cik_default_size; 2913 + WREG32(RLC_GPM_SCRATCH_ADDR, 0x3d); 2914 + for (i = 0; i < 3; i++) 2915 + WREG32(RLC_GPM_SCRATCH_DATA, clear_state_info[i]); 2916 + WREG32(RLC_DRIVER_DMA_STATUS, 0); 2917 + 2918 + cik_rlc_start(rdev); 2919 + 2920 + return 0; 2921 + }

+47

drivers/gpu/drm/radeon/cikd.h

··· 497 497 #define CP_MEC_ME2_UCODE_ADDR 0xC178 498 498 #define CP_MEC_ME2_UCODE_DATA 0xC17C 499 499 500 + #define CP_INT_CNTL_RING0 0xC1A8 501 + # define CNTX_BUSY_INT_ENABLE (1 << 19) 502 + # define CNTX_EMPTY_INT_ENABLE (1 << 20) 503 + # define PRIV_INSTR_INT_ENABLE (1 << 22) 504 + # define PRIV_REG_INT_ENABLE (1 << 23) 505 + # define TIME_STAMP_INT_ENABLE (1 << 26) 506 + # define CP_RINGID2_INT_ENABLE (1 << 29) 507 + # define CP_RINGID1_INT_ENABLE (1 << 30) 508 + # define CP_RINGID0_INT_ENABLE (1 << 31) 509 + 500 510 #define CP_MAX_CONTEXT 0xC2B8 501 511 502 512 #define CP_RB0_BASE_HI 0xC2C4 513 + 514 + #define RLC_CNTL 0xC300 515 + # define RLC_ENABLE (1 << 0) 516 + 517 + #define RLC_MC_CNTL 0xC30C 518 + 519 + #define RLC_LB_CNTR_MAX 0xC348 520 + 521 + #define RLC_LB_CNTL 0xC364 522 + 523 + #define RLC_LB_CNTR_INIT 0xC36C 524 + 525 + #define RLC_SAVE_AND_RESTORE_BASE 0xC374 526 + #define RLC_DRIVER_DMA_STATUS 0xC378 527 + 528 + #define RLC_GPM_UCODE_ADDR 0xC388 529 + #define RLC_GPM_UCODE_DATA 0xC38C 530 + 531 + #define RLC_UCODE_CNTL 0xC39C 532 + 533 + #define RLC_CGCG_CGLS_CTRL 0xC424 534 + 535 + #define RLC_LB_INIT_CU_MASK 0xC43C 536 + 537 + #define RLC_LB_PARAMS 0xC444 538 + 539 + #define RLC_SERDES_CU_MASTER_BUSY 0xC484 540 + #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 541 + # define SE_MASTER_BUSY_MASK 0x0000ffff 542 + # define GC_MASTER_BUSY (1 << 16) 543 + # define TC0_MASTER_BUSY (1 << 17) 544 + # define TC1_MASTER_BUSY (1 << 18) 545 + 546 + #define RLC_GPM_SCRATCH_ADDR 0xC4B0 547 + #define RLC_GPM_SCRATCH_DATA 0xC4B4 503 548 504 549 #define PA_SC_RASTER_CONFIG 0x28350 505 550 # define RASTER_CONFIG_RB_MAP_0 0 ··· 643 598 #define CGTS_USER_TCC_DISABLE 0x3c010 644 599 #define TCC_DISABLE_MASK 0xFFFF0000 645 600 #define TCC_DISABLE_SHIFT 16 601 + 602 + #define CB_CGTT_SCLK_CTRL 0x3c2a0 646 603 647 604 /* 648 605 * PM4

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