Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/radeon: implement async vm_flush for the CP (v7)
Update the page table base address and flush the
VM TLB using the CP.
v2: update for 2 level PTs
v3: use new packet for invalidate
v4: update SH_MEM* regs when flushing the VM
v5: add pfp sync, go back to old style vm TLB invalidate
v6: fix hdp flush packet count
v7: use old style HDP flush
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+79
+79
drivers/gpu/drm/radeon/cik.c
+79
drivers/gpu/drm/radeon/cik.c
···
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{
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}
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/**
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* cik_vm_flush - cik vm flush using the CP
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*
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* @rdev: radeon_device pointer
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*
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* Update the page table base and flush the VM TLB
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* using the CP (CIK).
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*/
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void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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{
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struct radeon_ring *ring = &rdev->ring[ridx];
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+
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if (vm == NULL)
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return;
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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if (vm->id < 8) {
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radeon_ring_write(ring,
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(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
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} else {
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radeon_ring_write(ring,
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(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
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}
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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/* update SH_MEM_* regs */
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, VMID(vm->id));
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, SH_MEM_BASES >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0); /* SH_MEM_BASES */
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radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
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radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
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radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, VMID(0));
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/* HDP flush */
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/* We should be using the WAIT_REG_MEM packet here like in
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* cik_fence_ring_emit(), but it causes the CP to hang in this
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* context...
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*/
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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/* bits 0-15 are the VM contexts0-15 */
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 1 << vm->id);
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/* sync PFP to ME, otherwise we might get invalid PFP reads */
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radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
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radeon_ring_write(ring, 0x0);
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}
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