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phy: phy-rockchip-samsung-hdptx: Supplement some register names with their full version

Complete the register names of CMN_REG(0081) and CMN_REG(0087) to their
full version, and it can help to better match the datasheet.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-3-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Damon Ding and committed by
Vinod Koul f7060241 2947c806

+3 -3
+3 -3
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 82 82 #define ROPLL_SSC_EN BIT(0) 83 83 /* CMN_REG(0081) */ 84 84 #define OVRD_PLL_CD_CLK_EN BIT(8) 85 - #define PLL_CD_HSCLK_EAST_EN BIT(0) 85 + #define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) 86 86 /* CMN_REG(0086) */ 87 87 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) 88 88 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) 89 89 #define PLL_PCG_CLK_EN BIT(0) 90 90 /* CMN_REG(0087) */ 91 - #define PLL_FRL_MODE_EN BIT(3) 92 - #define PLL_TX_HS_CLK_EN BIT(2) 91 + #define ANA_PLL_FRL_MODE_EN BIT(3) 92 + #define ANA_PLL_TX_HS_CLK_EN BIT(2) 93 93 /* CMN_REG(0089) */ 94 94 #define LCPLL_ALONE_MODE BIT(1) 95 95 /* CMN_REG(0097) */